AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Commit Graph

  • f4c0185f31 Merge pull request #8 from paulscherrerinstitute/feature/se32 master Waldemar Koprek 2024-08-08 12:41:58 +02:00
  • 01de9bd1a9 Add register to control caching behavior on AXI link that performs the dma transfer feature/se32 Elmar Schmid 2024-08-08 11:53:32 +02:00
  • 16f13e64d7 Add internal data width as generic parameter Elmar Schmid 2024-08-08 11:49:45 +02:00
  • 0dfa3ef76b Merge pull request #7 from paulscherrerinstitute/6-interrupts-not-reliably-generated-when-window-is-switched Waldemar Koprek 2024-07-30 08:47:23 +02:00
  • 3957ce32b5 Adapt interrupt generation logic to solve problem with missing interrupts. 6-interrupts-not-reliably-generated-when-window-is-switched Elmar Schmid 2024-07-25 15:39:24 +02:00
  • a0f4eddf91 Updated instantiation of psi_common_async_fifo due to change of the port name KW82 2024-01-26 10:48:07 +01:00
  • 69a9c03486 Merge pull request #5 from paulscherrerinstitute/feature/timeout_ctrl Waldemar Koprek 2023-09-21 12:47:32 +02:00
  • 12c010fe45 Add timeout control bits and logic to ignore timeout or configure framebased timeout in input logic. feature/timeout_ctrl Elmar Schmid 2023-09-19 16:09:12 +02:00
  • f6178e9dbd Refactoring and compliant with 3.0.0 release psi_common 2.0.0 stef_b 2023-04-14 17:36:50 +02:00
  • 5249ac7223 DEVEL: support for 1024bit bus feature/1024bus Radoslaw Rybaniec 2021-04-28 13:03:56 +02:00
  • 28b79e93a9 DOC: Updated Changelog.md 1.2.3 Daniele Felici 2020-09-30 14:28:16 +02:00
  • 7a45fa8df8 DOC: Updated Readme.md Daniele Felici 2020-04-02 10:47:05 +02:00
  • a0464c6a9d DOC: Updated Readme.md Oliver Bründler 2019-12-19 07:57:00 +01:00
  • 5390c0c3c0 BUGFIX: Workaround for ISE tools implementing memory as FFs in case of 1 stream 1.2.2 Oliver Bruendler 2019-11-25 10:23:36 +01:00
  • cec193edca DEVEL: Updated documentation for release 1.2.1 Oliver Bruendler 2019-11-19 10:58:25 +01:00
  • 141d54dd4f DEVEL: Fix testbench (tolerate additional IRQs on stream2) develop Oliver Bruendler 2019-11-15 13:57:05 +01:00
  • 8b2211d07a FEATURE: Added claring of the maximum level FIFO to the driver Oliver Bruendler 2019-11-14 07:56:38 +01:00
  • 7de31cc946 DOC: Fixed documentation (WINCNTw is in samples, not bytes) Oliver Bruendler 2019-11-12 14:39:54 +01:00
  • 2838d1e3e9 DOC: Fixed documentation (use strHandle instead of ipHandle in example code) Oliver Bruendler 2019-11-12 14:38:42 +01:00
  • 404af6d979 BUGFIX: Fix data unwrapping (bug found in HIPA LLRF bringup) Oliver Bruendler 2019-11-12 14:37:39 +01:00
  • df29e19f6d TIMING: Optimized timing on critical path between input FIFO and DMA Added pipeline stage after FIFO to reduce requirements of fall-through interface Oliver Bruendler 2019-11-07 07:46:37 +01:00
  • 7f22ec9050 BUGFIX: Made design working for 1 stream Oliver Bruendler 2019-10-30 11:02:11 +01:00
  • 3efc256530 Merge branch 'master' of https://github.com/paulscherrerinstitute/psi_multi_stream_daq Oliver Bruendler 2019-10-30 08:06:15 +01:00
  • be272f611c DEVEL: Made driver C++ tolerant Oliver Bruendler 2019-10-21 17:41:29 +02:00
  • 9ad003bc41 DEVEL: Made driver C++ compatible Oliver Bruendler 2019-10-21 17:39:21 +02:00
  • 6b60029bf7 Repository moved to https://github.com/paulscherrerinstitute/psi_multi_stream_daq PreGitHub Oliver Bruendler 2019-08-02 13:49:50 +02:00
  • d455112276 DEVEL: First open source release 1.2.0 Oliver Bruendler 2019-08-02 10:03:58 +02:00
  • f5dc56dce5 DEVEL: Use AXI slave from psi_common instead of legacy version 1.1.0 Oliver Bruendler 2019-07-22 09:29:01 +02:00
  • 0a6476d7fd DOC: Removed needless folder level in Dependencies Oliver Bruendler 2019-07-03 10:37:21 +02:00
  • a8f4b821bd FEATURE: Added dependency resolution script Oliver Bruendler 2019-07-03 10:33:57 +02:00
  • 33915d6457 DOC: Generated PDF Oliver Bruendler 2019-06-24 08:25:23 +02:00
  • 841236f53d DEVEL: Added continuous integration files Oliver Bruendler 2019-06-21 07:26:53 +02:00
  • a576b2a7c9 BUGFIX: Remove /* in comments (confuses tools) 1.0.0 Oliver Bruendler 2019-06-19 16:45:04 +02:00
  • 657b22aa9c DOC: Updated documentation for release Oliver Bruendler 2019-06-19 14:57:09 +02:00
  • 1f551fbac2 BUGFIX: Fix code from bringup Oliver Bruendler 2019-06-19 12:51:01 +02:00
  • f80dfbc584 DEVEL: Added driver and related documentation Oliver Bruendler 2019-06-19 09:04:08 +02:00
  • 828759a5a6 BUGFIX: Bugfixes from bringup Oliver Bruendler 2019-06-18 13:45:09 +02:00
  • 4399e89830 DEVEL: Made IP Vivado Compatible - Add ID Ports to axi slave interface - Simplified some expressions in psi_ms_daq_daq_sm.vhd Oliver Bruendler 2019-06-14 07:52:10 +02:00
  • 1a75cd16a5 BUGFIX: Added various simplifications to make code synthesizable by Vivado Oliver Bruendler 2019-06-06 18:19:56 +02:00
  • 388d241783 DEVEL: Moved Tosca component to separate repository 0.9.0 Oliver Bruendler 2019-06-06 15:21:48 +02:00
  • c409f8ea36 FEATURE: Added AXI implementation and implemented LASTWINn Register Oliver Bruendler 2019-06-05 13:51:51 +02:00
  • 0a791bcb05 UPDATE: Update to new library versions after open sourcing 0.2.0 Oliver Bruendler 2018-10-17 09:13:45 +02:00
  • 415c743f14 DOC: Documented clean clock crossing implementation Oliver Bruendler 2018-09-11 08:25:14 +02:00
  • 59716bf3bc DEVEL: Allow different clocks for TMEM and SMEM Oliver Bruendler 2018-09-11 07:49:33 +02:00
  • ddf28d6596 DOC: Update Changelog.md 0.1.0 Oliver Bruendler 2018-09-05 11:00:20 +02:00
  • b64745dcbb DOC: Updated documentation Oliver Bruendler 2018-09-05 10:58:32 +02:00
  • d53b4c2c14 FEATURE: Added END-BY-TRIG flag to window context RAM Oliver Bruendler 2018-09-05 08:53:43 +02:00
  • 1a78759524 BUGFIX: Tolerate Priority-Level with zero Streams assigned Oliver Bruendler 2018-09-05 08:52:35 +02:00
  • ed98a54676 DEVEL: Always request maximum burst size (independent of input FIFO level) Oliver Bruendler 2018-09-05 08:51:01 +02:00
  • ecae623b53 DEVEL: Added stream numbers to TB messages Oliver Bruendler 2018-09-05 08:50:27 +02:00
  • 5c56188a96 DEVEL: Added testbench for stream 3 (trigger mask mode) Oliver Bruendler 2018-09-04 16:36:39 +02:00
  • 8034aec5e4 CLEANUP: Cleanup top level TB Oliver Bruendler 2018-09-04 15:22:19 +02:00
  • 7e4a621f24 BUGFIX: Prevent TB from stimulating zero size transfers unwantendly (IRQs are suppressed in this case) Oliver Bruendler 2018-09-04 13:14:49 +02:00
  • fca85cbfd7 DEVEL: Implemented stream 2 in top-level TB Oliver Bruendler 2018-09-04 13:05:23 +02:00
  • 6ee4dfe4c2 BUGFIX: Do only generate IRQs for streams that are enabled Oliver Bruendler 2018-09-04 13:05:04 +02:00
  • 2cae5276fb BUGFIX: Do not expect responses for zero size transfers since they are suppressed Oliver Bruendler 2018-09-04 13:04:41 +02:00
  • dc076a3e7c BUGFIX: Do ontly go for TLAST check in Statemachine if window is not protected Otherwise the SM is blocked because it will repeatedly go for the TLAST handling instead of checking for a response. Oliver Bruendler 2018-09-04 13:04:04 +02:00
  • 08736d54ba FEATURE: Added "IS RECORDING" to status register Oliver Bruendler 2018-09-04 13:02:51 +02:00
  • b9f343ad13 DEVEL: Check if stram 1 tests really complete Oliver Bruendler 2018-09-04 09:19:26 +02:00
  • 8c925be1f8 DEVEL: Added stream 1 to top level TB Oliver Bruendler 2018-09-04 09:07:10 +02:00
  • 7b0dc7eb45 BUGFIX: Fixed handling of TLAST remaining in DMA engine buffer Oliver Bruendler 2018-09-04 08:32:52 +02:00
  • 3061386f00 CLEANUP: Split top-level TB into multiple files Oliver Bruendler 2018-09-03 14:50:20 +02:00
  • befcc9f36b DEVEL: Top level TB works for stream 0 Oliver Bruendler 2018-09-03 14:21:16 +02:00
  • e96dddc623 DEVEL: Made Project compiling using ISE Oliver Bruendler 2018-08-31 15:39:35 +02:00
  • b2ff03c1db DEVEL: Work on top level TB Oliver Bruendler 2018-08-31 15:10:28 +02:00
  • b64efa1f22 DEVEL: Top-Level Compiles Oliver Bruendler 2018-08-31 10:57:23 +02:00
  • 46bc02e36f DEVEL: Implemented TMEM Interface (not yet tested) Oliver Bruendler 2018-08-31 10:42:50 +02:00
  • 2c987611ab DEVEL: Implemented Top-Level (not yet complete) Oliver Bruendler 2018-08-31 08:30:19 +02:00
  • a773e82ee9 DEVEL: TB for data buffer full Oliver Bruendler 2018-08-31 07:47:35 +02:00
  • 0813b9c0da DEVEL: Testcase for memory command full Oliver Bruendler 2018-08-31 07:36:13 +02:00
  • 8eede7e216 DEVEL: TB for empty timeout frame Oliver Bruendler 2018-08-30 17:08:15 +02:00
  • 550d451684 DEVEL: Implemented test for the case of empty input FIFO Oliver Bruendler 2018-08-30 16:52:15 +02:00
  • 8001511e7d CLEANUP: Removed RemRam address latch not required anymore (no pipeline delay between state machine and RAM write) Oliver Bruendler 2018-08-29 13:43:01 +02:00
  • 6ef2687cf4 DEVEL: Implemented handling for starting a command when input is empty Oliver Bruendler 2018-08-29 13:41:27 +02:00
  • 62c654bc1e CLEANUP: Removed testcases not required because embedded in other cases Oliver Bruendler 2018-08-29 11:59:00 +02:00
  • 40ccc0ddad DEVEL: Work on DAQ DMA TB Oliver Bruendler 2018-08-29 11:53:27 +02:00
  • 659fe51314 DEVEL: Simplified daq_dma Oliver Bruendler 2018-08-29 11:53:18 +02:00
  • e0205add63 DEVEL: Work on handling of unaligned transfers Oliver Bruendler 2018-08-06 10:44:08 +02:00
  • f6ec0a087a DEVEL: Worked on DMA (unaligned transfers) Oliver Bruendler 2018-07-16 16:32:59 +02:00
  • eb882a9724 DEVEL: First DMA tests Oliver Bruendler 2018-07-16 14:43:49 +02:00
  • 46ea654cbd DEVEL: Initial implementation of the DMA engine Oliver Bruendler 2018-07-16 11:10:10 +02:00
  • b6b6094f0f DEVEL: Added skeleton for DMA engine Oliver Bruendler 2018-07-13 11:40:33 +02:00
  • 13871baefb CLEANUP: Cleaned up all testbenches Oliver Bruendler 2018-07-13 11:40:17 +02:00
  • 140d5c17e1 DEVEL: Implemented different input modes Oliver Bruendler 2018-07-12 11:45:14 +02:00
  • 8f553f3601 DEVEL: Set up everything for implementing recorder modes Oliver Bruendler 2018-07-12 09:57:19 +02:00
  • f90e2adff0 CLEANUP: Removed duplicate code of TrigLatch handling Oliver Bruendler 2018-07-12 09:08:12 +02:00
  • 6b11752736 DOC: Updated documentation Oliver Bruendler 2018-07-12 09:01:10 +02:00
  • 55b7da5de4 CLEANUP: removed todos from source file Oliver Bruendler 2018-07-11 14:22:59 +02:00
  • 2411504ff0 TIMING: Timing optimization for pointer calculation Oliver Bruendler 2018-07-11 14:22:43 +02:00
  • 1a77b43b39 DEVEL: Replaced round-robing arbiters by priority arbitters (less logic) Oliver Bruendler 2018-07-11 14:22:18 +02:00
  • 53f1b15bd8 DEVEL: Implemented test for timestamp handling Oliver Bruendler 2018-07-11 11:52:34 +02:00
  • 4c26626d43 DEVEL: Tested IRQ functionality Oliver Bruendler 2018-07-11 10:58:02 +02:00
  • cca1c36361 DEVEL: Implemented IRQ handling (not tested yet) Oliver Bruendler 2018-07-11 07:52:27 +02:00
  • 7e6b610f92 DEVEL: Implemented enable/disable tests Oliver Bruendler 2018-07-10 13:41:47 +02:00
  • cac231412b DEVEL: Implemented handling for first access after enable (not tested yet) Oliver Bruendler 2018-07-10 10:03:06 +02:00
  • fd2790c6e6 CLEANUP: Cleaned up testbench and removed testcases not required Oliver Bruendler 2018-07-10 09:25:28 +02:00
  • c20e4c8770 DEVEL: Implemented Multi-Stream Tests Oliver Bruendler 2018-07-10 07:52:16 +02:00
  • faea3628a9 Moved repository from git@git.psi.ch:DigitaleSignalVerarbeitung/Libraries/VHDL/psi_multi_stream_daq.git bruendler_o 2018-07-09 08:54:52 +02:00
  • b26489eebf DEVEL: Tests for single window mode Oliver Bruendler 2018-07-06 16:56:26 +02:00
  • eed6158a1f DEVEL: Finished testbench for priority handling Oliver Bruendler 2018-07-06 11:39:12 +02:00