DEVEL: Worked on DMA (unaligned transfers)
This commit is contained in:
Oliver Bruendler
@ -78,7 +78,7 @@ architecture rtl of psi_ms_daq_daq_dma is
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signal Rem_Data : std_logic_vector(63 downto 0);
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-- Types
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type State_t is (Idle_s, RemRd1_s, RemRd2_s, Transfer_s, Done_s, Cmd_s);
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type State_t is (Idle_s, RemRd1_s, RemRd2_s, Start_s, Transfer_s, Done_s, Cmd_s);
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-- Two process method
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type two_process_r is record
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@ -99,14 +99,14 @@ architecture rtl of psi_ms_daq_daq_dma is
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DataLast : std_logic_vector(63 downto 0);
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DataCur : std_logic_vector(63 downto 0);
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DataCurVld : std_logic;
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UpdateLast : std_logic;
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HndlSft : unsigned(2 downto 0);
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FirstDma : std_logic_vector(Streams_g-1 downto 0);
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DataMux : std_logic_vector(63 downto 0);
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MuxInVld : std_logic;
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DataMuxVld : std_logic;
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Inp_Rdy : std_logic_vector(Streams_g-1 downto 0);
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Mem_CmdVld : std_logic;
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Trigger : std_logic;
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DataRaw : std_logic_vector(63 downto 0);
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end record;
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signal r, r_next : two_process_r;
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@ -120,16 +120,19 @@ begin
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variable v : two_process_r;
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variable ThisByte_v : std_logic_vector(7 downto 0);
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variable ByteIdx_v : integer range 0 to 7;
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variable MuxInVld_v : std_logic;
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begin
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-- *** Hold variables stable ***
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v := r;
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-- *** Default Values ***
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v.CmdFifo_Rdy := '0';
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v.Inp_Rdy := (others => '0');
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Inp_Rdy <= (others => '0');
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v.Mem_DataVld := '0';
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v.RspFifo_Vld := '0';
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v.MuxInVld := '0';
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MuxInVld_v := '0';
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v.RemWen := '0';
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v.UpdateLast := '0';
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-- *** State Machine ***
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case r.State is
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@ -150,18 +153,23 @@ begin
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when RemRd2_s =>
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-- TODO: Handle empty timeout sample
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-- TODO: Very short TFs (no read from FIFO)
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-- TODO: Handle end of transfer because no more data
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-- Prevent RAM data from before reset to have an influence
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if r.FirstDma(r.HndlStream) = '1' then
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v.HndlSft := (others => '0');
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v.HndlSize := (others => '0');
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else
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v.HndlSft := unsigned(Rem_RdBytes);
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v.HndlSft := to_unsigned(0, 3) - unsigned(Rem_RdBytes);
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v.DataLast := Rem_Data;
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v.HndlSize := resize(unsigned(Rem_RdBytes), v.HndlMaxSize'length);
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end if;
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v.FirstDma(r.HndlStream) := '0';
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v.State := Transfer_s;
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v.State := Start_s;
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when Start_s =>
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v.State := Transfer_s;
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v.UpdateLast := '1';
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when Transfer_s =>
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-- TF done because of maximum size reached
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@ -172,8 +180,9 @@ begin
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v.Trigger := Inp_Data(r.HndlStream).IsTrig;
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elsif DatFifo_AlmFull = '0' then
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v.HndlSize := r.HndlSize + unsigned(Inp_Data(r.HndlStream).Bytes);
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v.Inp_Rdy(r.HndlStream) := '1';
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v.MuxInVld := '1';
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-- Combinatorial handling because of fall-through interface at input
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Inp_Rdy(r.HndlStream) <= '1';
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MuxInVld_v := '1';
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end if;
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when Done_s =>
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@ -189,6 +198,7 @@ begin
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when Cmd_s =>
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if Mem_CmdRdy = '1' then
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v.State := Idle_s;
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v.RemWen := '1';
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v.Mem_CmdVld := '0';
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v.RspFifo_Vld := '1';
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v.RspFifo_Data.Size := std_logic_vector(r.HndlSize);
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@ -200,31 +210,38 @@ begin
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end case;
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-- *** Data Multiplexer ***
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v.DataMux := Inp_Data(r.HndlStream).Data;
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v.DataMuxVld := r.MuxInVld;
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if r.State = RemRd2_s then
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v.DataMux := Rem_Data;
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else
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v.DataMux := Inp_Data(r.HndlStream).Data;
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end if;
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v.DataMuxVld := MuxInVld_v;
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if r.DataMuxVld = '1' then
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v.DataRaw := r.DataMux;
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end if;
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-- *** Data Alignment ***
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v.DataCurVld := '0';
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if r.DataMuxVld = '1' then
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v.DataCurVld := '1';
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v.DataCurVld := r.DataMuxVld;
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if r.DataMuxVld = '1' or r.State = Start_s then
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for i in 0 to 7 loop
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ByteIdx_v := (i-to_integer(r.HndlSft)+8) mod 8;
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ByteIdx_v := (i+to_integer(r.HndlSft)) mod 8;
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v.DataCur(8*(i+1)-1 downto 8*i) := r.DataMux(8*(ByteIdx_v+1)-1 downto 8*ByteIdx_v);
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end loop;
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end if;
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if r.DataCurVld = '1' then
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v.Mem_DataVld := r.DataCurVld;
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if (r.DataCurVld = '1') or (r.UpdateLast = '1') then
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for i in 0 to 7 loop
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if i < r.HndlSft then
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if i < 8-r.HndlSft then
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ThisByte_v := r.DataLast(8*(i+1)-1 downto 8*i);
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else
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ThisByte_v := r.DataCur(8*(i+1)-1 downto 8*i);
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end if;
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v.Mem_Data(8*(i+1)-1 downto 8*i) := ThisByte_v;
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end loop;
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v.Mem_DataVld := '1';
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v.DataLast := r.DataCur;
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end if;
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-- *** Assign to signal ***
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r_next <= v;
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@ -234,7 +251,6 @@ begin
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Mem_CmdAddr <= r.HndlAddress;
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Mem_CmdSize(r.HndlSize'range) <= std_logic_vector(r.HndlSize);
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Mem_CmdSize(Mem_CmdSize'high downto r.HndlSize'high+1) <= (others => '0');
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Inp_Rdy <= r.Inp_Rdy;
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Mem_CmdVld <= r.Mem_CmdVld;
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--------------------------------------------
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@ -251,11 +267,9 @@ begin
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r.RemWen <= '0';
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r.State <= Idle_s;
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r.FirstDma <= (others => '1');
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r.Inp_Rdy <= (others => '0');
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r.DataMuxVld <= '0';
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r.DataCurVld <= '0';
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r.Mem_CmdVld <= '0';
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r.MuxInVld <= '0';
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end if;
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end if;
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end process;
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@ -342,7 +356,7 @@ begin
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WrAddr => r.RemWrAddr,
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Wr => r.RemWen,
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WrData(66 downto 64) => r.RemWrBytes,
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WrData(63 downto 0) => r.DataLast,
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WrData(63 downto 0) => r.DataRaw,
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RdAddr => r.RemRdAddr,
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RdData(66 downto 64) => Rem_RdBytes,
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RdData(63 downto 0) => Rem_Data
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@ -72,7 +72,53 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
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signal DaqSm_Resp_Rdy : inout std_logic;
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constant Generics_c : Generics_t) is
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begin
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assert false report "Case UNALIGNED Procedure CONTROL: No Content added yet!" severity warning;
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InitCase(Clk, Rst);
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print(">> -- Unaligned --");
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-- End Unaligned
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print(">> End Unaligned");
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InitCase(Clk, Rst);
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InitSubCase(0);
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ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01230000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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ApplyCmd(2, 16#01231000#, 29, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01231000#, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01232000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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WaitAllProc(Clk);
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-- QWord Split
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print(">> QWord Split");
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InitCase(Clk, Rst);
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InitSubCase(1);
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ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01230000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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ApplyCmd(2, 16#01231000#, 29, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01231000#, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01232000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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WaitAllProc(Clk);
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-- QWord Split, Rdy Toggling
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print(">> QWord Split, Rdy Toggling");
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InitCase(Clk, Rst);
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InitSubCase(2);
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ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01230000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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ApplyCmd(2, 16#01231000#, 29, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01231000#, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
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CheckResp(2, 16#01232000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
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WaitAllProc(Clk);
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-- mixed streams
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-- End Aligned
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-- Unaligned end by trigger (leads to flush)
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-- Unaligned end by timeout (leads to flush)
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end procedure;
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procedure input (
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@ -82,7 +128,22 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
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signal Inp_Data : inout Input2Daq_Data_a;
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constant Generics_c : Generics_t) is
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begin
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assert false report "Case UNALIGNED Procedure INPUT: No Content added yet!" severity warning;
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-- End Unaligned
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WaitForCase(0, Clk);
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ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
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ApplyData(2, 29, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 30);
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ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 30+29);
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ProcDone_V(0) := '1';
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-- QWord Split
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WaitForCase(1, Clk);
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ApplyData(2, 30+29+30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
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ProcDone_V(0) := '1';
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-- QWord Split, Rdy Toggling
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WaitForCase(2, Clk);
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ApplyData(2, 30+29+30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
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ProcDone_V(0) := '1';
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end procedure;
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procedure mem_cmd (
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@ -93,7 +154,26 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
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signal Mem_CmdRdy : inout std_logic;
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constant Generics_c : Generics_t) is
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begin
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assert false report "Case UNALIGNED Procedure MEM_CMD: No Content added yet!" severity warning;
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-- End Unaligned
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WaitForCase(0, Clk);
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CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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CheckMemCmd( 16#01231000#, 29, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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ProcDone_V(1) := '1';
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-- QWord Split
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WaitForCase(1, Clk);
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CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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CheckMemCmd( 16#01231000#, 29, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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ProcDone_V(1) := '1';
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-- QWord Split, Rdy Toggling
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WaitForCase(2, Clk);
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CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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CheckMemCmd( 16#01231000#, 29, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
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ProcDone_V(1) := '1';
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end procedure;
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procedure mem_dat (
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@ -103,7 +183,26 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
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signal Mem_DatRdy : inout std_logic;
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constant Generics_c : Generics_t) is
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begin
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assert false report "Case UNALIGNED Procedure MEM_DAT: No Content added yet!" severity warning;
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-- End Unaligned
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WaitForCase(0, Clk);
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CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
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CheckMemData(29, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30);
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CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29);
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ProcDone_V(2) := '1';
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-- QWord Split
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WaitForCase(1, Clk);
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CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
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CheckMemData(29, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30);
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CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29);
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ProcDone_V(2) := '1';
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-- QWord Split, Rdy Toggling
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WaitForCase(2, Clk);
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CheckMemData(30, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
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CheckMemData(29, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30);
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CheckMemData(30, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29);
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ProcDone_V(2) := '1';
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end procedure;
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end;
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@ -57,14 +57,16 @@ package psi_ms_daq_daq_dma_tb_pkg is
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signal Inp_Vld : out std_logic_vector;
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signal Inp_Rdy : in std_logic_vector;
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signal Inp_Data : out Input2Daq_Data_a;
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signal Clk : in std_logic);
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signal Clk : in std_logic;
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Offset : in integer := 0);
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procedure CheckMemData( Bytes : in integer;
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RdyDelay : in integer := 0;
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signal Mem_DatData : in std_logic_vector;
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signal Mem_DatVld : in std_logic;
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signal Mem_DatRdy : out std_logic;
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signal Clk : in std_logic);
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signal Clk : in std_logic;
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Offset : in integer := 0);
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procedure CheckMemCmd( Address : in integer;
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Bytes : in integer;
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@ -139,8 +141,9 @@ package body psi_ms_daq_daq_dma_tb_pkg is
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signal Inp_Vld : out std_logic_vector;
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signal Inp_Rdy : in std_logic_vector;
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signal Inp_Data : out Input2Daq_Data_a;
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signal Clk : in std_logic) is
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variable DataCnt_v : unsigned(7 downto 0) := (others => '0');
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signal Clk : in std_logic;
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Offset : in integer := 0) is
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variable DataCnt_v : unsigned(7 downto 0) := to_unsigned(Offset, 8);
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begin
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assert EndType = NoEnd_s report "###ERROR###: EndType not yet implemented" severity error;
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Inp_Vld(Stream) <= '1';
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@ -171,8 +174,9 @@ package body psi_ms_daq_daq_dma_tb_pkg is
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signal Mem_DatData : in std_logic_vector;
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signal Mem_DatVld : in std_logic;
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signal Mem_DatRdy : out std_logic;
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signal Clk : in std_logic) is
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variable DataCnt_v : integer := 0;
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signal Clk : in std_logic;
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Offset : in integer := 0) is
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variable DataCnt_v : integer := Offset;
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begin
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for dw in 0 to (Bytes+7)/8-1 loop
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if RdyDelay > 0 then
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@ -183,6 +187,7 @@ package body psi_ms_daq_daq_dma_tb_pkg is
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end if;
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Mem_DatRdy <= '1';
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wait until rising_edge(Clk) and Mem_DatVld = '1';
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Mem_DatRdy <= '0';
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for byte in 0 to 7 loop
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if dw*8+byte >= Bytes then
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-- nothing to compare
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@ -192,8 +197,6 @@ package body psi_ms_daq_daq_dma_tb_pkg is
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end if;
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end loop;
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end loop;
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wait until rising_edge(Clk);
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StdlCompare(0, Mem_DatVld, "Mem_DatVld did not go low");
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end procedure;
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procedure CheckMemCmd( Address : in integer;
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Reference in New Issue
Block a user