AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: First DMA tests

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This commit is contained in:
Oliver Bruendler
2018-07-16 14:43:49 +02:00
parent 46ea654cbd
commit eb882a9724
15 changed files with 653 additions and 105 deletions
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37
hdl/psi_ms_daq_daq_dma.vhd
View File

@ -20,7 +20,7 @@ library work;
-- Entity Declaration
------------------------------------------------------------------------------
-- $$ testcases=aligned,unaligned,odd_size,no_data_read,input_empty,timetout,empty_timeout,trigger,cmd_full,data_full $$
-- $$ processes=control,input,mem $$
-- $$ processes=control,input,mem_cmd,mem_dat $$
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg,work.psi_tb_activity_pkg $$
entity psi_ms_daq_daq_dma is
generic (
@ -28,8 +28,8 @@ entity psi_ms_daq_daq_dma is
);
port (
-- Control signals
Clk : in std_logic; -- $$ type=clk; freq=200e6 $$
Rst : in std_logic; -- $$ type=rst; clk=Clk $$
Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=control,input,mem_dat,mem_cmd $$
Rst : in std_logic; -- $$ type=rst; clk=Clk; proc=control $$
-- DAQ Statemachione Connections
DaqSm_Cmd : in DaqSm2DaqDma_Cmd_t; -- $$ proc=control $$
@ -44,13 +44,13 @@ entity psi_ms_daq_daq_dma is
Inp_Data : in Input2Daq_Data_a(Streams_g-1 downto 0); -- $$ proc=input $$
-- Memory interface connections
Mem_CmdAddr : out std_logic_vector(31 downto 0); -- $$ proc=mem $$
Mem_CmdSize : out std_logic_vector(31 downto 0); -- $$ proc=mem $$
Mem_CmdVld : out std_logic; -- $$ proc=mem $$
Mem_CmdRdy : in std_logic; -- $$ proc=mem $$
Mem_DatData : out std_logic_vector(63 downto 0); -- $$ proc=mem $$
Mem_DatVld : out std_logic; -- $$ proc=mem $$
Mem_DatRdy : in std_logic -- $$ proc=mem $$
Mem_CmdAddr : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
Mem_CmdSize : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
Mem_CmdVld : out std_logic; -- $$ proc=mem_cmd $$
Mem_CmdRdy : in std_logic; -- $$ proc=mem_cmd $$
Mem_DatData : out std_logic_vector(63 downto 0); -- $$ proc=mem_dat $$
Mem_DatVld : out std_logic; -- $$ proc=mem_dat $$
Mem_DatRdy : in std_logic -- $$ proc=mem_dat $$
);
end entity;
@ -102,6 +102,7 @@ architecture rtl of psi_ms_daq_daq_dma is
HndlSft : unsigned(2 downto 0);
FirstDma : std_logic_vector(Streams_g-1 downto 0);
DataMux : std_logic_vector(63 downto 0);
MuxInVld : std_logic;
DataMuxVld : std_logic;
Inp_Rdy : std_logic_vector(Streams_g-1 downto 0);
Mem_CmdVld : std_logic;
@ -127,8 +128,8 @@ begin
v.CmdFifo_Rdy := '0';
v.Inp_Rdy := (others => '0');
v.Mem_DataVld := '0';
v.Mem_CmdVld := '0';
v.RspFifo_Vld := '0';
v.MuxInVld := '0';
-- *** State Machine ***
case r.State is
@ -172,7 +173,7 @@ begin
elsif DatFifo_AlmFull = '0' then
v.HndlSize := r.HndlSize + unsigned(Inp_Data(r.HndlStream).Bytes);
v.Inp_Rdy(r.HndlStream) := '1';
v.DataMuxVld := '1';
v.MuxInVld := '1';
end if;
when Done_s =>
@ -199,7 +200,8 @@ begin
end case;
-- *** Data Multiplexer ***
v.DataMux := Inp_Data(r.HndlStream).Data;
v.DataMux := Inp_Data(r.HndlStream).Data;
v.DataMuxVld := r.MuxInVld;
-- *** Data Alignment ***
v.DataCurVld := '0';
@ -213,11 +215,11 @@ begin
if r.DataCurVld = '1' then
for i in 0 to 7 loop
if i < r.HndlSft then
ThisByte_v := r.DataLast(8*(i+1) downto 8*i);
ThisByte_v := r.DataLast(8*(i+1)-1 downto 8*i);
else
ThisByte_v := r.DataCur(8*(i+1) downto 8*i);
ThisByte_v := r.DataCur(8*(i+1)-1 downto 8*i);
end if;
v.Mem_Data(8*(i+1) downto 8*i) := ThisByte_v;
v.Mem_Data(8*(i+1)-1 downto 8*i) := ThisByte_v;
end loop;
v.Mem_DataVld := '1';
v.DataLast := r.DataCur;
@ -232,6 +234,8 @@ begin
Mem_CmdAddr <= r.HndlAddress;
Mem_CmdSize(r.HndlSize'range) <= std_logic_vector(r.HndlSize);
Mem_CmdSize(Mem_CmdSize'high downto r.HndlSize'high+1) <= (others => '0');
Inp_Rdy <= r.Inp_Rdy;
Mem_CmdVld <= r.Mem_CmdVld;
--------------------------------------------
-- Sequential Process
@ -251,6 +255,7 @@ begin
r.DataMuxVld <= '0';
r.DataCurVld <= '0';
r.Mem_CmdVld <= '0';
r.MuxInVld <= '0';
end if;
end if;
end process;

2
hdl/psi_ms_daq_pkg.vhd
View File

@ -46,7 +46,7 @@ package psi_ms_daq_pkg is
Trigger : std_logic;
Stream : integer range 0 to MaxStreams_c-1;
end record;
constant DaqDma2DaqSm_Resp_Size_c : integer := 15+1+MaxStreamsBits_c;
constant DaqDma2DaqSm_Resp_Size_c : integer := 16+1+MaxStreamsBits_c;
function DaqDma2DaqSm_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector;
function DaqDme2DaqSm_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t;

3
sim/config.tcl
View File

@ -85,6 +85,9 @@ add_tb_run
create_tb_run "psi_ms_daq_daq_sm_tb"
add_tb_run
create_tb_run "psi_ms_daq_daq_dma_tb"
add_tb_run

178
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd
View File

@ -58,11 +58,12 @@ architecture sim of psi_ms_daq_daq_dma_tb is
-- *** TB Control ***
signal TbRunning : boolean := True;
signal NextCase : integer := -1;
signal ProcessDone : std_logic_vector(0 to 2) := (others => '0');
constant AllProcessesDone_c : std_logic_vector(0 to 2) := (others => '1');
signal ProcessDone : std_logic_vector(0 to 3) := (others => '0');
constant AllProcessesDone_c : std_logic_vector(0 to 3) := (others => '1');
constant TbProcNr_control_c : integer := 0;
constant TbProcNr_input_c : integer := 1;
constant TbProcNr_mem_c : integer := 2;
constant TbProcNr_mem_cmd_c : integer := 2;
constant TbProcNr_mem_dat_c : integer := 3;
-- *** DUT Signals ***
signal Clk : std_logic := '1';
@ -116,7 +117,6 @@ begin
------------------------------------------------------------
p_tb_control : process
begin
wait until Rst = '0';
-- aligned
NextCase <= 0;
wait until ProcessDone = AllProcessesDone_c;
@ -188,61 +188,61 @@ begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_aligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_unaligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_odd_size.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_no_data_read.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_input_empty.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_timetout.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_trigger.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_cmd_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_data_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
wait;
@ -254,129 +254,195 @@ begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_aligned.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_unaligned.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_odd_size.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_no_data_read.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_input_empty.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_timetout.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_trigger.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_cmd_full.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
work.psi_ms_daq_daq_dma_tb_case_data_full.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
wait;
end process;
-- *** mem ***
p_mem : process
-- *** mem_cmd ***
p_mem_cmd : process
begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
wait;
end process;
-- *** mem_dat ***
p_mem_dat : process
begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_mem_dat_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_dat_c) <= '1';
wait;
end process;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_aligned is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_aligned is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_aligned is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -62,29 +72,99 @@ package body psi_ms_daq_daq_dma_tb_case_aligned is
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ALIGNED Procedure CONTROL: No Content added yet!" severity warning;
InitCase(Clk, Rst);
print(">> -- Aligned --");
-- Ready always high
print(">> Ready always high");
InitSubCase(0);
ApplyCmd(2, 16#01230000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01230000#, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- Data Ready toggling
print(">> Data Ready toggling");
InitSubCase(1);
ApplyCmd(2, 16#01231000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01231000#, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- Cmd Ready toggling
print(">> Cmd Ready toggling");
InitSubCase(2);
ApplyCmd(2, 16#01232000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01232000#, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case ALIGNED Procedure INPUT: No Content added yet!" severity warning;
-- Ready always high
WaitForCase(0, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ProcDone_V(0) := '1';
-- Data Ready toggling
WaitForCase(1, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ProcDone_V(0) := '1';
-- Cmd Ready toggling
WaitForCase(2, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ProcDone_V(0) := '1';
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
-- Ready always high
WaitForCase(0, Clk);
CheckMemCmd( 16#01230000#, 32, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
-- Data Ready toggling
WaitForCase(1, Clk);
CheckMemCmd( 16#01231000#, 32, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
-- Cmd Ready toggling
WaitForCase(2, Clk);
CheckMemCmd( 16#01232000#, 32, 5, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ALIGNED Procedure MEM: No Content added yet!" severity warning;
-- Ready always high
WaitForCase(0, Clk);
CheckMemData(32, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
ProcDone_V(2) := '1';
-- Data Ready toggling
WaitForCase(1, Clk);
CheckMemData(32, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
ProcDone_V(2) := '1';
-- Ready always high
WaitForCase(2, Clk);
CheckMemData(32, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
ProcDone_V(2) := '1';
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_cmd_full.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_cmd_full is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_cmd_full is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_cmd_full is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_cmd_full is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_cmd_full is
assert false report "Case CMD_FULL Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case CMD_FULL Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case CMD_FULL Procedure MEM: No Content added yet!" severity warning;
assert false report "Case CMD_FULL Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_data_full.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_data_full is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_data_full is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_data_full is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_data_full is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_data_full is
assert false report "Case DATA_FULL Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case DATA_FULL Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case DATA_FULL Procedure MEM: No Content added yet!" severity warning;
assert false report "Case DATA_FULL Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_empty_timeout.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_empty_timeout is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_empty_timeout is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
assert false report "Case EMPTY_TIMEOUT Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure MEM: No Content added yet!" severity warning;
assert false report "Case EMPTY_TIMEOUT Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_input_empty.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_input_empty is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_input_empty is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_input_empty is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
assert false report "Case INPUT_EMPTY Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure MEM: No Content added yet!" severity warning;
assert false report "Case INPUT_EMPTY Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_no_data_read.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_no_data_read is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_no_data_read is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_no_data_read is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_no_data_read is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_no_data_read is
assert false report "Case NO_DATA_READ Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case NO_DATA_READ Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case NO_DATA_READ Procedure MEM: No Content added yet!" severity warning;
assert false report "Case NO_DATA_READ Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_odd_size.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_odd_size is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_odd_size is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_odd_size is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_odd_size is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_odd_size is
assert false report "Case ODD_SIZE Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ODD_SIZE Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ODD_SIZE Procedure MEM: No Content added yet!" severity warning;
assert false report "Case ODD_SIZE Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_timetout.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_timetout is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_timetout is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_timetout is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_timetout is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_timetout is
assert false report "Case TIMETOUT Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TIMETOUT Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TIMETOUT Procedure MEM: No Content added yet!" severity warning;
assert false report "Case TIMETOUT Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_trigger.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_trigger is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_trigger is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_trigger is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_trigger is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_trigger is
assert false report "Case TRIGGER Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TRIGGER Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TRIGGER Procedure MEM: No Content added yet!" severity warning;
assert false report "Case TRIGGER Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

25
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_unaligned.vhd
View File

@ -25,6 +25,8 @@ library work;
package psi_ms_daq_daq_dma_tb_case_unaligned is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -33,16 +35,22 @@ package psi_ms_daq_daq_dma_tb_case_unaligned is
constant Generics_c : Generics_t);
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t);
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
@ -55,6 +63,8 @@ end package;
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_unaligned is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,6 +76,7 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
end procedure;
procedure input (
signal Clk : in std_logic;
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
@ -74,17 +85,25 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
assert false report "Case UNALIGNED Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
procedure mem_cmd (
signal Clk : in std_logic;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case UNALIGNED Procedure MEM_CMD: No Content added yet!" severity warning;
end procedure;
procedure mem_dat (
signal Clk : in std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case UNALIGNED Procedure MEM: No Content added yet!" severity warning;
assert false report "Case UNALIGNED Procedure MEM_DAT: No Content added yet!" severity warning;
end procedure;
end;

223
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_pkg.vhd
View File

@ -30,6 +30,63 @@ package psi_ms_daq_daq_dma_tb_pkg is
-- Not exported Generics
------------------------------------------------------------
constant Streams_g : positive := 4;
------------------------------------------------------------
-- Procedures
------------------------------------------------------------
type EndType_s is (Trigger_s, Timeout_s, NoData_s, NoEnd_s);
procedure ApplyCmd( Stream : in integer;
Address : in integer;
MaxSize : in integer;
signal DaqSm_Cmd : out DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : out std_logic;
signal Clk : in std_logic);
procedure CheckResp( Stream : in integer;
Address : in integer;
Size : in integer;
EndType : in EndType_s;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : out std_logic;
signal Clk : in std_logic);
procedure ApplyData( Stream : in integer;
Bytes : in integer;
EndType : in EndType_s;
signal Inp_Vld : out std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : out Input2Daq_Data_a;
signal Clk : in std_logic);
procedure CheckMemData( Bytes : in integer;
RdyDelay : in integer := 0;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : out std_logic;
signal Clk : in std_logic);
procedure CheckMemCmd( Address : in integer;
Bytes : in integer;
RdyDelay : in integer := 0;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : out std_logic;
signal Clk : in std_logic);
shared variable TestCase_v : integer := -1;
shared variable ProcDone_V : std_logic_vector(0 to 2);
procedure InitCase( signal Clk : in std_logic;
signal Rst : out std_logic);
procedure InitSubCase(CaseNr : in integer);
procedure WaitForCase( CaseNr : in integer;
signal Clk : in std_logic);
procedure WaitAllProc( signal Clk : in std_logic);
end package;
@ -37,4 +94,170 @@ end package;
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_pkg is
procedure ApplyCmd( Stream : in integer;
Address : in integer;
MaxSize : in integer;
signal DaqSm_Cmd : out DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : out std_logic;
signal Clk : in std_logic) is
begin
wait until rising_edge(Clk);
DaqSm_Cmd_Vld <= '1';
DaqSm_Cmd.Address <= std_logic_vector(to_unsigned(Address, 32));
DaqSm_Cmd.MaxSize <= std_logic_vector(to_unsigned(MaxSize, 16));
DaqSm_Cmd.Stream <= Stream;
wait until rising_edge(Clk);
DaqSm_Cmd_Vld <= '0';
end procedure;
procedure CheckResp( Stream : in integer;
Address : in integer;
Size : in integer;
EndType : in EndType_s;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : out std_logic;
signal Clk : in std_logic) is
begin
DaqSm_Resp_Rdy <= '1';
wait until rising_edge(Clk) and DaqSm_Resp_Vld = '1';
if Trigger_s = EndType then
StdlCompare(1, DaqSm_Resp.Trigger, "Response has not set TRIGGER");
else
StdlCompare(0, DaqSm_Resp.Trigger, "Response has not cleared TRIGGER");
end if;
StdlvCompareInt(Size, DaqSm_Resp.Size, "Wrong size in response");
IntCompare(Stream, DaqSm_Resp.Stream, "Wrong stream number in response");
wait until rising_edge(Clk);
StdlCompare(0, DaqSm_Resp_Vld, "Response valid did not go low");
end procedure;
procedure ApplyData( Stream : in integer;
Bytes : in integer;
EndType : in EndType_s;
signal Inp_Vld : out std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : out Input2Daq_Data_a;
signal Clk : in std_logic) is
variable DataCnt_v : unsigned(7 downto 0) := (others => '0');
begin
assert EndType = NoEnd_s report "###ERROR###: EndType not yet implemented" severity error;
Inp_Vld(Stream) <= '1';
for dw in 0 to (Bytes+7)/8-1 loop
for byte in 0 to 7 loop
if dw*8+byte >= Bytes then
Inp_Data(Stream).Data(8*(byte+1)-1 downto 8*byte) <= (others => '0');
else
Inp_Data(Stream).Data(8*(byte+1)-1 downto 8*byte) <= std_logic_vector(DataCnt_v);
DataCnt_v := DataCnt_v + 1;
end if;
end loop;
Inp_Data(Stream).Last <= '0';
Inp_Data(Stream).IsTo <= '0';
Inp_Data(Stream).IsTrig <= '0';
if Bytes-dw*8 > 8 then
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(8, 4));
else
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(Bytes-dw*8, 4));
end if;
wait until rising_edge(Clk) and Inp_Rdy(Stream) = '1';
end loop;
Inp_Vld(Stream) <= '0';
end procedure;
procedure CheckMemData( Bytes : in integer;
RdyDelay : in integer := 0;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : out std_logic;
signal Clk : in std_logic) is
variable DataCnt_v : integer := 0;
begin
for dw in 0 to (Bytes+7)/8-1 loop
if RdyDelay > 0 then
Mem_DatRdy <= '0';
for i in 0 to RdyDelay loop
wait until rising_edge(Clk);
end loop;
end if;
Mem_DatRdy <= '1';
wait until rising_edge(Clk) and Mem_DatVld = '1';
for byte in 0 to 7 loop
if dw*8+byte >= Bytes then
-- nothing to compare
else
StdlvCompareInt (DataCnt_v, Mem_DatData(8*(byte+1)-1 downto 8*byte), "Wrong Data QW[" & to_string(dw) & "] Byte [" & to_string(byte) & "]", false);
DataCnt_v := (DataCnt_v + 1) mod 256;
end if;
end loop;
end loop;
wait until rising_edge(Clk);
StdlCompare(0, Mem_DatVld, "Mem_DatVld did not go low");
end procedure;
procedure CheckMemCmd( Address : in integer;
Bytes : in integer;
RdyDelay : in integer := 0;
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : out std_logic;
signal Clk : in std_logic) is
begin
if RdyDelay > 0 then
Mem_CmdRdy <= '0';
else
Mem_CmdRdy <= '1';
end if;
wait until rising_edge(Clk) and Mem_CmdVld = '1';
if RdyDelay > 0 then
for i in 0 to RdyDelay loop
wait until rising_edge(Clk);
end loop;
end if;
Mem_CmdRdy <= '1';
StdlCompare(1, Mem_CmdVld, "Mem_CmdVld did not stay high");
StdlvCompareInt(Address, Mem_CmdAddr, "Wrong Address", false);
StdlvCompareInt(Bytes, Mem_CmdSize, "Wrong Size", false);
wait until rising_edge(Clk);
wait for 1 ns;
Mem_CmdRdy <= '0';
StdlCompare(0, Mem_CmdVld, "Mem_CmdVld did not go low");
end procedure;
procedure InitCase( signal Clk : in std_logic;
signal Rst : out std_logic) is
begin
ProcDone_V := (others => '0');
TestCase_v := -1;
wait until rising_edge(Clk);
Rst <= '1';
wait until rising_edge(Clk);
Rst <= '0';
wait until rising_edge(Clk);
end procedure;
procedure InitSubCase(CaseNr : in integer) is
begin
ProcDone_V := (others => '0');
TestCase_v := CaseNr;
end procedure;
procedure WaitForCase( CaseNr : in integer;
signal Clk : in std_logic) is
begin
while CaseNr /= TestCase_v loop
wait until rising_edge(Clk);
end loop;
end procedure;
procedure WaitAllProc( signal Clk : in std_logic) is
begin
while signed(ProcDone_V) /= -1 loop
wait until rising_edge(Clk);
end loop;
end procedure;
end;