AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Initial implementation of the DMA engine

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This commit is contained in:
Oliver Bruendler
2018-07-16 11:10:10 +02:00
parent b6b6094f0f
commit 46ea654cbd
15 changed files with 1527 additions and 37 deletions
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219
hdl/psi_ms_daq_daq_dma.vhd
View File

@ -19,37 +19,38 @@ library work;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
-- $$ testcases=aligned,unaligned,odd_size,no_data_read,input_empty,timetout,empty_timeout,trigger,cmd_full,data_full $$
-- $$ processes=control,input,mem $$
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg,work.psi_tb_activity_pkg $$
entity psi_ms_daq_daq_dma is
generic (
Streams_g : positive range 1 to 32 := 4;
StreamWidth_g : t_ainteger := (8, 16, 32, 64)
Streams_g : positive range 1 to 32 := 4 -- $$ constant=4 $$
);
port (
-- Control signals
Clk : in std_logic;
Rst : in std_logic;
Clk : in std_logic; -- $$ type=clk; freq=200e6 $$
Rst : in std_logic; -- $$ type=rst; clk=Clk $$
-- DAQ Statemachione Connections
DaqSm_Cmd : in DaqSm2DaqDma_Cmd_t;
DaqSm_Cmd_Vld : in std_logic;
DaqSm_Resp : out DaqDma2DaqSm_Resp_t;
DaqSm_Resp_Vld : out std_logic;
DaqSm_Resp_Rdy : in std_logic;
DaqSm_Cmd : in DaqSm2DaqDma_Cmd_t; -- $$ proc=control $$
DaqSm_Cmd_Vld : in std_logic; -- $$ proc=control $$
DaqSm_Resp : out DaqDma2DaqSm_Resp_t; -- $$ proc=control $$
DaqSm_Resp_Vld : out std_logic; -- $$ proc=control $$
DaqSm_Resp_Rdy : in std_logic; -- $$ proc=control $$
-- Input handling connections
Inp_Vld : in std_logic_vector(Streams_g-1 downto 0);
Inp_Rdy : out std_logic_vector(Streams_g-1 downto 0);
Inp_Data : in Input2Daq_Data_a(Streams_g-1 downto 0);
Inp_Vld : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=input $$
Inp_Rdy : out std_logic_vector(Streams_g-1 downto 0); -- $$ proc=input $$
Inp_Data : in Input2Daq_Data_a(Streams_g-1 downto 0); -- $$ proc=input $$
-- Memory interface connections
Mem_CmdAddr : out std_logic_vector(31 downto 0);
Mem_CmdSize : out std_logic_vector(31 downto 0);
Mem_CmdVld : out std_logic;
Mem_CmdRdy : in std_logic;
Mem_DatData : out std_logic_vector(63 downto 0);
Mem_DatVld : out std_logic;
Mem_DatRdy : in std_logic
Mem_CmdAddr : out std_logic_vector(31 downto 0); -- $$ proc=mem $$
Mem_CmdSize : out std_logic_vector(31 downto 0); -- $$ proc=mem $$
Mem_CmdVld : out std_logic; -- $$ proc=mem $$
Mem_CmdRdy : in std_logic; -- $$ proc=mem $$
Mem_DatData : out std_logic_vector(63 downto 0); -- $$ proc=mem $$
Mem_DatVld : out std_logic; -- $$ proc=mem $$
Mem_DatRdy : in std_logic -- $$ proc=mem $$
);
end entity;
@ -59,7 +60,7 @@ end entity;
architecture rtl of psi_ms_daq_daq_dma is
-- Constants
signal BufferFifoDepth_g : integer := 32;
constant BufferFifoDepth_c : integer := 32;
-- Component Connection Signals
@ -69,13 +70,15 @@ architecture rtl of psi_ms_daq_daq_dma is
signal CmdFifo_Cmd : DaqSm2DaqDma_Cmd_t;
signal CmdFifo_Vld : std_logic;
signal RspFifo_Level_Dbg : std_logic_vector(log2ceil(Streams_g) downto 0);
signal RspFifo_InData : std_logic_vector(DaqSm2DaqDma_Resp_Size_c-1 downto 0);
signal RspFifo_OutData : std_logic_vector(DaqSm2DaqDma_Resp_Size_c-1 downto 0);
signal DatFifo_Level_Dbg : std_logic_vector(log2ceil(BufferFifoDepth_g) downto 0);
signal RspFifo_InData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
signal RspFifo_OutData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
signal DatFifo_Level_Dbg : std_logic_vector(log2ceil(BufferFifoDepth_c) downto 0);
signal DatFifo_AlmFull : std_logic;
signal Rem_RdBytes : std_logic_vector(2 downto 0);
signal Rem_Data : std_logic_vector(63 downto 0);
-- Types
--type State_t is (Idle_s, CheckPrio1_s, CheckPrio2_s, CheckPrio3_s, CheckResp_s, TlastCheck_s, ReadCtxStr_s, First_s, ReadCtxWin_s, CalcAccess0_s, CalcAccess1_s, ProcResp0_s, NextWin_s, WriteCtx_s);
type State_t is (Idle_s, RemRd1_s, RemRd2_s, Transfer_s, Done_s, Cmd_s);
-- Two process method
type two_process_r is record
@ -84,6 +87,25 @@ architecture rtl of psi_ms_daq_daq_dma is
RspFifo_Data : DaqDma2DaqSm_Resp_t;
Mem_Data : std_logic_vector(63 downto 0);
Mem_DataVld : std_logic;
RemWrAddr : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemRdAddr : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemWen : std_logic;
RemWrBytes : std_logic_vector(2 downto 0);
State : State_t;
HndlMaxSize : unsigned(15 downto 0);
HndlSize : unsigned(15 downto 0);
HndlStream : integer range 0 to MaxStreams_c-1;
HndlAddress : std_logic_vector(31 downto 0);
DataLast : std_logic_vector(63 downto 0);
DataCur : std_logic_vector(63 downto 0);
DataCurVld : std_logic;
HndlSft : unsigned(2 downto 0);
FirstDma : std_logic_vector(Streams_g-1 downto 0);
DataMux : std_logic_vector(63 downto 0);
DataMuxVld : std_logic;
Inp_Rdy : std_logic_vector(Streams_g-1 downto 0);
Mem_CmdVld : std_logic;
Trigger : std_logic;
end record;
signal r, r_next : two_process_r;
@ -93,19 +115,123 @@ begin
-- Combinatorial Process
--------------------------------------------
p_comb : process( r, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp_Rdy, Inp_Vld, Inp_Data, Mem_CmdRdy, Mem_DatRdy,
CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull)
CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull, Rem_RdBytes, Rem_Data)
variable v : two_process_r;
variable ThisByte_v : std_logic_vector(7 downto 0);
variable ByteIdx_v : integer range 0 to 7;
begin
-- *** Hold variables stable ***
v := r;
-- *** Default Values ***
v.CmdFifo_Rdy := '0';
v.Inp_Rdy := (others => '0');
v.Mem_DataVld := '0';
v.Mem_CmdVld := '0';
v.RspFifo_Vld := '0';
-- *** State Machine ***
case r.State is
when Idle_s =>
v.HndlMaxSize := unsigned(CmdFifo_Cmd.MaxSize);
v.HndlStream := CmdFifo_Cmd.Stream;
v.HndlAddress := CmdFifo_Cmd.Address;
v.Trigger := '0';
if CmdFifo_Vld = '1' then
v.CmdFifo_Rdy := '1';
v.State := RemRd1_s;
end if;
when RemRd1_s =>
v.State := RemRd2_s;
when RemRd2_s =>
-- TODO: Handle empty timeout sample
-- TODO: Very short TFs (no read from FIFO)
-- Prevent RAM data from before reset to have an influence
if r.FirstDma(r.HndlStream) = '1' then
v.HndlSft := (others => '0');
v.HndlSize := (others => '0');
else
v.HndlSft := unsigned(Rem_RdBytes);
v.DataLast := Rem_Data;
v.HndlSize := resize(unsigned(Rem_RdBytes), v.HndlMaxSize'length);
end if;
v.FirstDma(r.HndlStream) := '0';
v.State := Transfer_s;
when Transfer_s =>
-- TF done because of maximum size reached
if r.HndlSize >= r.HndlMaxSize then
v.State := Done_s;
elsif Inp_Data(r.HndlStream).Last = '1' then
v.State := Done_s;
v.Trigger := Inp_Data(r.HndlStream).IsTrig;
elsif DatFifo_AlmFull = '0' then
v.HndlSize := r.HndlSize + unsigned(Inp_Data(r.HndlStream).Bytes);
v.Inp_Rdy(r.HndlStream) := '1';
v.DataMuxVld := '1';
end if;
when Done_s =>
if r.HndlMaxSize < r.HndlSize then
v.RemWrBytes := std_logic_vector(resize(r.HndlSize - r.HndlMaxSize, v.RemWrBytes'length));
v.HndlSize := r.HndlMaxSize;
else
v.RemWrBytes := (others => '0');
end if;
v.State := Cmd_s;
v.Mem_CmdVld := '1';
when Cmd_s =>
if Mem_CmdRdy = '1' then
v.State := Idle_s;
v.Mem_CmdVld := '0';
v.RspFifo_Vld := '1';
v.RspFifo_Data.Size := std_logic_vector(r.HndlSize);
v.RspFifo_Data.Trigger := r.Trigger;
v.RspFifo_Data.Stream := r.HndlStream;
end if;
when others => null;
end case;
-- *** Data Multiplexer ***
v.DataMux := Inp_Data(r.HndlStream).Data;
-- *** Data Alignment ***
v.DataCurVld := '0';
if r.DataMuxVld = '1' then
v.DataCurVld := '1';
for i in 0 to 7 loop
ByteIdx_v := (i-to_integer(r.HndlSft)+8) mod 8;
v.DataCur(8*(i+1)-1 downto 8*i) := r.DataMux(8*(ByteIdx_v+1)-1 downto 8*ByteIdx_v);
end loop;
end if;
if r.DataCurVld = '1' then
for i in 0 to 7 loop
if i < r.HndlSft then
ThisByte_v := r.DataLast(8*(i+1) downto 8*i);
else
ThisByte_v := r.DataCur(8*(i+1) downto 8*i);
end if;
v.Mem_Data(8*(i+1) downto 8*i) := ThisByte_v;
end loop;
v.Mem_DataVld := '1';
v.DataLast := r.DataCur;
end if;
-- *** Assign to signal ***
r_next <= v;
end process;
-- *** Registered Outputs ***
Mem_CmdAddr <= r.HndlAddress;
Mem_CmdSize(r.HndlSize'range) <= std_logic_vector(r.HndlSize);
Mem_CmdSize(Mem_CmdSize'high downto r.HndlSize'high+1) <= (others => '0');
--------------------------------------------
-- Sequential Process
@ -118,6 +244,13 @@ begin
r.CmdFifo_Rdy <= '0';
r.RspFifo_Vld <= '0';
r.Mem_DataVld <= '0';
r.RemWen <= '0';
r.State <= Idle_s;
r.FirstDma <= (others => '1');
r.Inp_Rdy <= (others => '0');
r.DataMuxVld <= '0';
r.DataCurVld <= '0';
r.Mem_CmdVld <= '0';
end if;
end if;
end process;
@ -147,10 +280,10 @@ begin
-- *** Response FIFO ***
-- Ready not required for system reasons: There is never more commands open than streams.
RspFifo_InData <= DaqSm2DaqDma_Cmd_ToStdlv(r.RspFifo_Data);
RspFifo_InData <= DaqDma2DaqSm_Resp_ToStdlv(r.RspFifo_Data);
i_fiforsp : entity work.psi_common_sync_fifo
generic map (
Width_g => DaqSm2DaqDma_Resp_Size_c,
Width_g => DaqDma2DaqSm_Resp_Size_c,
Depth_g => Streams_g,
RamStyle_g => "distributed"
)
@ -159,12 +292,12 @@ begin
Rst => Rst,
InData => RspFifo_InData,
InVld => r.RspFifo_Vld,
OutData => OutData,
OutData => RspFifo_OutData,
OutVld => DaqSm_Resp_Vld,
OutRdy => DaqSm_Resp_Rdy,
OutLevel => RspFifo_Level_Dbg
);
DaqSm_Resp <= DaqSm2DaqDma_Cmd_FromStdlv(OutData);
DaqSm_Resp <= DaqDme2DaqSm_Resp_FromStdlv(RspFifo_OutData);
-- *** Buffer FIFO ***
-- This FIFO allows buffering data for the time the state machine requires to react on a "memory interface not ready for more data" situation.
@ -173,9 +306,9 @@ begin
i_fifodata : entity work.psi_common_sync_fifo
generic map (
Width_g => 64,
Depth_g => BufferFifoDepth_g,
Depth_g => BufferFifoDepth_c,
AlmFullOn_g => true,
AlmFullLevel_g => BufferFifoDepth_g/2,
AlmFullLevel_g => BufferFifoDepth_c/2,
RamStyle_g => "distributed"
)
port map (
@ -190,6 +323,26 @@ begin
AlmFull => DatFifo_AlmFull
);
-- *** Remaining Data RAM ***
i_remram : entity work.psi_common_sdp_ram_rbw
generic map (
Depth_g => Streams_g,
Width_g => 3+64,
IsAsync_g => false,
RamStyle_g => "distributed"
)
port map (
Clk => Clk,
RdClk => Rst,
WrAddr => r.RemWrAddr,
Wr => r.RemWen,
WrData(66 downto 64) => r.RemWrBytes,
WrData(63 downto 0) => r.DataLast,
RdAddr => r.RemRdAddr,
RdData(66 downto 64) => Rem_RdBytes,
RdData(63 downto 0) => Rem_Data
);
end;

8
hdl/psi_ms_daq_pkg.vhd
View File

@ -47,8 +47,8 @@ package psi_ms_daq_pkg is
Stream : integer range 0 to MaxStreams_c-1;
end record;
constant DaqDma2DaqSm_Resp_Size_c : integer := 15+1+MaxStreamsBits_c;
function DaqSm2DaqDma_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector;
function DaqSm2DaqDma_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t;
function DaqDma2DaqSm_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector;
function DaqDme2DaqSm_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t;
type ToCtxStr_t is record
Stream : integer range 0 to MaxStreams_c-1;
@ -113,7 +113,7 @@ package body psi_ms_daq_pkg is
end function;
-- *** DaqDma2DaqSm_Resp ***
function DaqSm2DaqDma_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector is
function DaqDma2DaqSm_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector is
variable stdlv : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
begin
stdlv(15 downto 0) := rec.Size;
@ -122,7 +122,7 @@ package body psi_ms_daq_pkg is
return stdlv;
end function;
function DaqSm2DaqDma_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t is
function DaqDme2DaqSm_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t is
variable rec : DaqDma2DaqSm_Resp_t;
begin
rec.Size := stdlv(15 downto 0);

13
sim/config.tcl
View File

@ -33,6 +33,7 @@ add_sources "../hdl" {
psi_ms_daq_pkg.vhd \
psi_ms_daq_input.vhd \
psi_ms_daq_daq_sm.vhd \
psi_ms_daq_daq_dma.vhd \
} -tag src
# testbenches
@ -56,6 +57,18 @@ add_sources "../tb" {
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_irq.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_timestamp.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_pkg.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_unaligned.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_trigger.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_timetout.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_odd_size.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_no_data_read.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_input_empty.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_empty_timeout.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_data_full.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_cmd_full.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd \
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd \
} -tag tb
#TB Runs

384
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd Normal file
View File

@ -0,0 +1,384 @@
------------------------------------------------------------
-- Testbench generated by TbGen.py
------------------------------------------------------------
-- see Library/Python/TbGenerator
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_case_aligned.all;
use work.psi_ms_daq_daq_dma_tb_case_unaligned.all;
use work.psi_ms_daq_daq_dma_tb_case_odd_size.all;
use work.psi_ms_daq_daq_dma_tb_case_no_data_read.all;
use work.psi_ms_daq_daq_dma_tb_case_input_empty.all;
use work.psi_ms_daq_daq_dma_tb_case_timetout.all;
use work.psi_ms_daq_daq_dma_tb_case_empty_timeout.all;
use work.psi_ms_daq_daq_dma_tb_case_trigger.all;
use work.psi_ms_daq_daq_dma_tb_case_cmd_full.all;
use work.psi_ms_daq_daq_dma_tb_case_data_full.all;
------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------
entity psi_ms_daq_daq_dma_tb is
end entity;
------------------------------------------------------------
-- Architecture
------------------------------------------------------------
architecture sim of psi_ms_daq_daq_dma_tb is
-- *** Fixed Generics ***
constant Streams_g : positive := 4;
-- *** Not Assigned Generics (default values) ***
-- *** Exported Generics ***
constant Generics_c : Generics_t := (
Dummy => true);
-- *** TB Control ***
signal TbRunning : boolean := True;
signal NextCase : integer := -1;
signal ProcessDone : std_logic_vector(0 to 2) := (others => '0');
constant AllProcessesDone_c : std_logic_vector(0 to 2) := (others => '1');
constant TbProcNr_control_c : integer := 0;
constant TbProcNr_input_c : integer := 1;
constant TbProcNr_mem_c : integer := 2;
-- *** DUT Signals ***
signal Clk : std_logic := '1';
signal Rst : std_logic := '1';
signal DaqSm_Cmd : DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : std_logic := '0';
signal DaqSm_Resp : DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : std_logic := '0';
signal DaqSm_Resp_Rdy : std_logic := '0';
signal Inp_Vld : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
signal Inp_Rdy : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
signal Inp_Data : Input2Daq_Data_a(Streams_g-1 downto 0);
signal Mem_CmdAddr : std_logic_vector(31 downto 0) := (others => '0');
signal Mem_CmdSize : std_logic_vector(31 downto 0) := (others => '0');
signal Mem_CmdVld : std_logic := '0';
signal Mem_CmdRdy : std_logic := '0';
signal Mem_DatData : std_logic_vector(63 downto 0) := (others => '0');
signal Mem_DatVld : std_logic := '0';
signal Mem_DatRdy : std_logic := '0';
begin
------------------------------------------------------------
-- DUT Instantiation
------------------------------------------------------------
i_dut : entity work.psi_ms_daq_daq_dma
generic map (
Streams_g => Streams_g
)
port map (
Clk => Clk,
Rst => Rst,
DaqSm_Cmd => DaqSm_Cmd,
DaqSm_Cmd_Vld => DaqSm_Cmd_Vld,
DaqSm_Resp => DaqSm_Resp,
DaqSm_Resp_Vld => DaqSm_Resp_Vld,
DaqSm_Resp_Rdy => DaqSm_Resp_Rdy,
Inp_Vld => Inp_Vld,
Inp_Rdy => Inp_Rdy,
Inp_Data => Inp_Data,
Mem_CmdAddr => Mem_CmdAddr,
Mem_CmdSize => Mem_CmdSize,
Mem_CmdVld => Mem_CmdVld,
Mem_CmdRdy => Mem_CmdRdy,
Mem_DatData => Mem_DatData,
Mem_DatVld => Mem_DatVld,
Mem_DatRdy => Mem_DatRdy
);
------------------------------------------------------------
-- Testbench Control !DO NOT EDIT!
------------------------------------------------------------
p_tb_control : process
begin
wait until Rst = '0';
-- aligned
NextCase <= 0;
wait until ProcessDone = AllProcessesDone_c;
-- unaligned
NextCase <= 1;
wait until ProcessDone = AllProcessesDone_c;
-- odd_size
NextCase <= 2;
wait until ProcessDone = AllProcessesDone_c;
-- no_data_read
NextCase <= 3;
wait until ProcessDone = AllProcessesDone_c;
-- input_empty
NextCase <= 4;
wait until ProcessDone = AllProcessesDone_c;
-- timetout
NextCase <= 5;
wait until ProcessDone = AllProcessesDone_c;
-- empty_timeout
NextCase <= 6;
wait until ProcessDone = AllProcessesDone_c;
-- trigger
NextCase <= 7;
wait until ProcessDone = AllProcessesDone_c;
-- cmd_full
NextCase <= 8;
wait until ProcessDone = AllProcessesDone_c;
-- data_full
NextCase <= 9;
wait until ProcessDone = AllProcessesDone_c;
TbRunning <= false;
wait;
end process;
------------------------------------------------------------
-- Clocks !DO NOT EDIT!
------------------------------------------------------------
p_clock_Clk : process
constant Frequency_c : real := real(200e6);
begin
while TbRunning loop
wait for 0.5*(1 sec)/Frequency_c;
Clk <= not Clk;
end loop;
wait;
end process;
------------------------------------------------------------
-- Resets
------------------------------------------------------------
p_rst_Rst : process
begin
wait for 1 us;
-- Wait for two clk edges to ensure reset is active for at least one edge
wait until rising_edge(Clk);
wait until rising_edge(Clk);
Rst <= '0';
wait;
end process;
------------------------------------------------------------
-- Processes !DO NOT EDIT!
------------------------------------------------------------
-- *** control ***
p_control : process
begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.control(DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
wait;
end process;
-- *** input ***
p_input : process
begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_input_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.input(Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_input_c) <= '1';
wait;
end process;
-- *** mem ***
p_mem : process
begin
-- aligned
wait until NextCase = 0;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_aligned.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- unaligned
wait until NextCase = 1;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_unaligned.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- odd_size
wait until NextCase = 2;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_odd_size.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- no_data_read
wait until NextCase = 3;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_no_data_read.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- input_empty
wait until NextCase = 4;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_input_empty.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- timetout
wait until NextCase = 5;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_timetout.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- empty_timeout
wait until NextCase = 6;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_empty_timeout.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- trigger
wait until NextCase = 7;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_trigger.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- cmd_full
wait until NextCase = 8;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_cmd_full.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
-- data_full
wait until NextCase = 9;
ProcessDone(TbProcNr_mem_c) <= '0';
work.psi_ms_daq_daq_dma_tb_case_data_full.mem(Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_mem_c) <= '1';
wait;
end process;
end;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_aligned is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_aligned is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ALIGNED Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case ALIGNED Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ALIGNED Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_cmd_full.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_cmd_full is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_cmd_full is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case CMD_FULL Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case CMD_FULL Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case CMD_FULL Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_data_full.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_data_full is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_data_full is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case DATA_FULL Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case DATA_FULL Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case DATA_FULL Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_empty_timeout.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_empty_timeout is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_input_empty.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_input_empty is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_input_empty is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

90
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_no_data_read is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_no_data_read is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case NO_DATA_READ Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case NO_DATA_READ Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case NO_DATA_READ Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_odd_size is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_odd_size is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ODD_SIZE Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case ODD_SIZE Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case ODD_SIZE Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_timetout is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_timetout is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TIMETOUT Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case TIMETOUT Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TIMETOUT Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

90
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_trigger.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_trigger is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_trigger is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TRIGGER Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case TRIGGER Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case TRIGGER Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

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tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_unaligned.vhd Normal file
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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_dma_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_case_unaligned is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t);
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t);
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_case_unaligned is
procedure control (
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
signal DaqSm_Cmd_Vld : inout std_logic;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
signal DaqSm_Resp_Vld : in std_logic;
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case UNALIGNED Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure input (
signal Inp_Vld : inout std_logic_vector;
signal Inp_Rdy : in std_logic_vector;
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case UNALIGNED Procedure INPUT: No Content added yet!" severity warning;
end procedure;
procedure mem (
signal Mem_CmdAddr : in std_logic_vector;
signal Mem_CmdSize : in std_logic_vector;
signal Mem_CmdVld : in std_logic;
signal Mem_CmdRdy : inout std_logic;
signal Mem_DatData : in std_logic_vector;
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case UNALIGNED Procedure MEM: No Content added yet!" severity warning;
end procedure;
end;

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------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_dma_tb_pkg is
-- *** Generics Record ***
type Generics_t is record
Dummy : boolean; -- required since empty records are not allowed
end record;
------------------------------------------------------------
-- Not exported Generics
------------------------------------------------------------
constant Streams_g : positive := 4;
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_dma_tb_pkg is
end;