AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Implemented Top-Level (not yet complete)

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This commit is contained in:
Oliver Bruendler
2018-08-31 08:30:19 +02:00
parent a773e82ee9
commit 2c987611ab
1 changed files with 247 additions and 0 deletions
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hdl/psi_ms_daq.vhd Normal file
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------------------------------------------------------------------------------
-- Description
------------------------------------------------------------------------------
-- This component calculates a binary division of two fixed point values.
------------------------------------------------------------------------------
-- Libraries
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_array_pkg.all;
use work.smem_master_types_pkg.all;
use work.psi_ms_daq_pkg.all;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
entity psi_ms_daq is
generic (
Streams_g : positive range 1 to 32 := 2;
StreamWidth_g : t_ainteger := (16, 16);
StreamPrio_g : t_ainteger := (1, 1);
StreamBuffer_g : t_ainteger := (1024, 1024);
StreamTimout_g : t_areal := (1.0e-3, 1.0e-3);
StreamClkFreq_g : t_areal := (100.0e6, 100.0e6);
StreamTsFifoDepth_g : t_ainteger := (16, 16);
StreamUseTs_g : t_aboolean := (true, true);
MaxWindows_g : positive range 1 to 32 := 16;
MinBurstSize_g : integer := 512;
MaxBurstSize_g : integer := 512
);
port (
-- Data Stream Input
Str_Clk : in std_logic_vector(Streams_g-1 downto 0);
Str_Data : in t_aslv64(Streams_g-1 downto 0);
Str_Ts : in t_aslv64(Streams_g-1 downto 0);
Str_Vld : in std_logic_vector(Streams_g-1 downto 0);
Str_Rdy : out std_logic_vector(Streams_g-1 downto 0);
Str_Trig : in std_logic_vector(Streams_g-1 downto 0);
-- Tosca Control Signals
Tosca_Clk : in std_logic; -- 200 MHz tosca clock
Tmem_Rst : in std_logic;
Smem_Rst : in std_logic;
-- TMEM Interface
AcqTmem : TBD
TmemAcq : TBD
-- SMEM Interface
AcqSmem : out ToSmemWr_t;
SmemAcq : in FromSmemWr_t;
-- Miscellaneous
Irq : out std_logic
);
end entity;
------------------------------------------------------------------------------
-- Architecture Declaration
------------------------------------------------------------------------------
architecture rtl of psi_ms_daq is
-- Control Signals
signal Rst : std_logic;
-- Input/Statemachine Signals
signal InpSm_HasTlast : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_TsVld : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_TsRdy : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_Level : t_aslv16/Streams_g-1 downto 0);
signal InpSm_TsData : t_aslv64(Streams_g-1 downto 0);
-- Statemachine/Dma
signal SmDma_Cmd : DaqSm2DaqDma_Cmd_t;
signal SmDma_CmdVld : std_logic;
signal DmaSm_Resp : DaqDma2DaqSm_Resp_t;
signal DmaSm_RespVld : std_logic;
signal DmaSm_RespRdy : std_logic;
-- Input/Dma
signal InpDma_Vld : std_logic_vector(Streams_g-1 downto 0);
signal InpDma_Rdy : std_logic_vector(Streams_g-1 downto 0);
signal InpDma_Data : Input2Daq_Data_a(Streams_g-1 downto 0);
-- Dma/Mem
signal DmaMem_CmdAddr : std_logic_vector(31 downto 0);
signal DmaMem_CmdSize : std_logic_vector(31 downto 0);
signal DmaMem_CmdVld : std_logic;
signal DmaMem_CmdRdy : std_logic;
signal DmaMem_DatData : std_logic_vector(63 downto 0);
signal DmaMem_DatVld : std_logic;
signal DmaMem_DatRdy : std_logic;
-- Mem/Statemachine
signal MemSm_Done : std_logic;
begin
--------------------------------------------
-- Reset
--------------------------------------------
p_rst : process(Tosca_Clk)
begin
if rising_edge(Tosca_Clk) then
Rst <= Tmem_Rst or Smem_Rst;
end if;
end process;
--------------------------------------------
-- Input Logic Instantiation
--------------------------------------------
g_input : for str in 0 to Streams_g-1 generate
i_input : entity work.psi_ms_daq_input
generic map (
StreamWidth_g => StreamWidth_g(str),
StreamBuffer_g => StreamBuffer_g(str),
StreamTimeout_g => StreamTimeout_g(str),
StreamClkFreq_g => StreamClkFreq_g(str),
StreamTsFifoDepth_g => StreamTsFifoDepth_g(str),
StreamUseTs_g => StreamUseTs_g(str)
)
port map (
Str_Clk => Str_Clk(str),
Str_Vld => Str_Vld(str),
Str_Rdy => Str_Rdy(str),
Str_Data => Str_Data(str),
Str_Trig => Str_Trig(str),
Str_Ts => Str_Ts(str),
Clk => Tosca_Clk,
Rst => Rst,
PostTrigSpls =>
Mode =>
Arm =>
IsArmed =>
Daq_Vld => InpDma_Vld(str),
Daq_Rdy => InpDma_Rdy(str),
Daq_Data => InpDma_Data(str),
Daq_Level => InpSm_Level(str),
Daq_HasLast => InpSm_HasTlast(str),
Ts_Vld => InpSm_TsVld(str),
Ts_Rdy => InpSm_TsRdy(str),
Ts_Data => InpSm_TsData(str)
);
end generate;
--------------------------------------------
-- Control State Machine
--------------------------------------------
i_statemachine : entity work.psi_ms_daq_daq_sm
generic map (
Simulation_g => false,
Streams_g => Streams_g,
StreamPrio_g => StreamPrio_g,
StreamWidth_g => StreamWidth_g,
Windows_g => MaxWindows_g,
MinBurstSize_g => MinBurstSize_g,
MaxBurstSize_g => MaxBurstSize_g
)
port map (
Clk => Tosca_Clk,
Rst => Rst,
GlbEna =>
StrEna =>
StrIrq =>
Inp_HasLast => InpSm_HasTlast,
Inp_Level => InpSm_Level,
Ts_Vld => InpSm_TsVld,
Ts_Rdy => InpSm_TsRdy,
Ts_Data => InpSm_TsData,
Dma_Cmd => SmDma_Cmd,
Dma_Cmd_Vld => SmDma_CmdVld,
Dma_Resp => DmaSm_Resp,
Dma_Resp_Vld => DmaSm_RespVld,
Dma_Resp_Rdy => DmaSm_RespRdy,
TfDone => MemSm_Done,
-- Context RAM connections
CtxStr_Cmd : out ToCtxStr_t; -- $$ proc=ctx $$
CtxStr_Resp : in FromCtx_t; -- $$ proc=ctx $$
CtxWin_Cmd : out ToCtxWin_t; -- $$ proc=ctx $$
CtxWin_Resp : in FromCtx_t -- $$ proc=ctx $$
);
--------------------------------------------
-- DMA Engine
--------------------------------------------
i_dma : entity work.psi_ms_daq_daq_dma
generic map (
Streams_g => Streams_g
)
port map (
Clk => Tosca_Clk,
Rst => Rst,
DaqSm_Cmd => SmDma_Cmd,
DaqSm_Cmd_Vld => SmDma_CmdVld,
DaqSm_Resp => DmaSm_Resp,
DaqSm_Resp_Vld => DmaSm_RespVld,
DaqSm_Resp_Rdy => DmaSm_RespRdy,
Inp_Vld => InpDma_Vld,
Inp_Rdy => InpDma_Rdy,
Inp_Data => InpDma_Data,
Mem_CmdAddr => DmaMem_CmdAddr,
Mem_CmdSize => DmaMem_CmdSize,
Mem_CmdVld => DmaMem_CmdVld,
Mem_CmdRdy => DmaMem_CmdRdy,
Mem_DatData => DmaMem_DatData,
Mem_DatVld => DmaMem_DatVld,
Mem_DatRdy => DmaMem_DatRdy
);
--------------------------------------------
-- SMEM Controller
--------------------------------------------
i_memif : entity work.smem_master_write
generic map (
MaxBurstSize_g => 512,
MemBlockSize_g => 4096,
DataBufferSize_g => 1024,
MaxOpenTransactions_g => Streams_g
)
port map (
Clk => Tosca_Clk,
Rst => Rst,
Cmd_Addr => DmaMem_CmdAddr,
Cmd_Size => DmaMem_CmdSize,
Cmd_Vld => DmaMem_CmdVld,
Cmd_Rdy => DmaMem_CmdRdy,
Dat_Data => DmaMem_DatData,
Dat_Vld => DmaMem_DatVld,
Dat_Rdy => DmaMem_DatRdy,
Done => MemSm_Done,
ToSmem => ToSmem,
FromSmem => FromSmem
);
end;