AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Implemented IRQ handling (not tested yet)

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This commit is contained in:
Oliver Bruendler
2018-07-11 07:52:27 +02:00
parent 7e6b610f92
commit cca1c36361
9 changed files with 159 additions and 44 deletions
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114
hdl/psi_ms_daq_daq_sm.vhd
View File

@ -43,6 +43,7 @@ entity psi_ms_daq_daq_sm is
Rst : in std_logic; -- $$ proc=control $$
GlbEna : in std_logic; -- $$ proc=control; lowactive=true $$
StrEna : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control; lowactive=true $$
StrIrq : out std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control,dma_resp,dma_cmd; $$
-- Input logic Connections
Inp_HasLast : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control $$
@ -58,6 +59,9 @@ entity psi_ms_daq_daq_sm is
Dma_Resp_Vld : in std_logic; -- $$ proc=dma_resp $$
Dma_Resp_Rdy : out std_logic; -- $$ proc=dma_resp $$
-- Memory Controller
TfDone : in std_logic; -- $$ proc=dma_resp $$
-- Context RAM connections
CtxStr_Cmd : out ToCtxStr_t; -- $$ proc=ctx $$
CtxStr_Resp : in FromCtx_t; -- $$ proc=ctx $$
@ -104,13 +108,19 @@ architecture rtl of psi_ms_daq_daq_sm is
end function;
-- Component Connection Signals
signal AvailPrio1 : std_logic_vector(count(StreamPrio_g, 1)-1 downto 0);
signal AvailPrio2 : std_logic_vector(count(StreamPrio_g, 2)-1 downto 0);
signal AvailPrio3 : std_logic_vector(count(StreamPrio_g, 3)-1 downto 0);
signal GrantPrio1 : std_logic_vector(AvailPrio1'range);
signal GrantPrio2 : std_logic_vector(AvailPrio2'range);
signal GrantPrio3 : std_logic_vector(AvailPrio3'range);
signal GrantVld : std_logic_vector(3 downto 1);
signal AvailPrio1 : std_logic_vector(count(StreamPrio_g, 1)-1 downto 0);
signal AvailPrio2 : std_logic_vector(count(StreamPrio_g, 2)-1 downto 0);
signal AvailPrio3 : std_logic_vector(count(StreamPrio_g, 3)-1 downto 0);
signal GrantPrio1 : std_logic_vector(AvailPrio1'range);
signal GrantPrio2 : std_logic_vector(AvailPrio2'range);
signal GrantPrio3 : std_logic_vector(AvailPrio3'range);
signal GrantVld : std_logic_vector(3 downto 1);
signal IrqFifoAlmFull : std_logic;
signal IrqFifoEmpty : std_logic;
signal IrqFifoGenIrq : std_logic;
signal IrqFifoStream : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
signal IrqFifoIn : std_logic_vector(log2ceil(Streams_g) downto 0);
signal IrqFifoOut : std_logic_vector(log2ceil(Streams_g) downto 0);
-- Types
type State_t is (Idle_s, CheckPrio1_s, CheckPrio2_s, CheckPrio3_s, CheckResp_s, TlastCheck_s, ReadCtxStr_s, First_s, ReadCtxWin_s, CalcAccess0_s, CalcAccess1_s, ProcResp0_s, NextWin_s, WriteCtx_s);
@ -151,6 +161,8 @@ architecture rtl of psi_ms_daq_daq_sm is
HndlWinBytes : std_logic_vector(32 downto 0);
HndlWinLast : std_logic_vector(31 downto 0);
HndlTs : std_logic_vector(63 downto 0);
TfDoneCnt : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
TfDoneReg : std_logic;
HndlWinDone : std_logic;
CtxStr_Cmd : ToCtxStr_t;
CtxWin_Cmd : ToCtxWin_t;
@ -159,6 +171,9 @@ architecture rtl of psi_ms_daq_daq_sm is
Dma_Resp_Rdy : std_logic;
Ts_Rdy : std_logic_vector(Streams_g-1 downto 0);
SimDelCnt : integer range 0 to 4;
IrqFifoWrite : std_logic;
IrqFifoRead : std_logic;
StrIrq : std_logic_vector(Streams_g-1 downto 0);
end record;
signal r, r_next : two_process_r;
@ -168,8 +183,8 @@ begin
--------------------------------------------
-- Combinatorial Process
--------------------------------------------
p_comb : process( r, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Data, Dma_Resp, Dma_Resp_Vld, CtxStr_Resp, CtxWin_Resp, GlbEna, StrEna,
GrantVld, GrantPrio1, GrantPrio2, GrantPrio3)
p_comb : process( r, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Data, Dma_Resp, Dma_Resp_Vld, CtxStr_Resp, CtxWin_Resp, GlbEna, StrEna, TfDone, IrqFifoGenIrq, IrqFifoStream,
GrantVld, GrantPrio1, GrantPrio2, GrantPrio3, IrqFifoAlmFull, IrqFifoEmpty)
variable v : two_process_r;
begin
-- *** Hold variables stable ***
@ -190,6 +205,9 @@ begin
v.CtxWin_Cmd.WdatHi := (others => '0');
v.CtxStr_Cmd.WdatLo := (others => '0');
v.CtxStr_Cmd.WdatHi := (others => '0');
v.IrqFifoWrite := '0';
v.IrqFifoRead := '0';
v.StrIrq := (others => '0');
-- *** Pure Pipelining (no functional registers) ***
@ -200,6 +218,7 @@ begin
v.HasLastReg := Inp_HasLast;
v.StrEnaReg := StrEna;
v.GlbEnaReg := GlbEna;
v.TfDoneReg := TfDone;
-- *** Check Availability of a full burst ***
for str in 0 to Streams_g-1 loop
@ -221,10 +240,12 @@ begin
when Idle_s =>
v.HndlCtxCnt := 0;
v.HndlWinDone := '0';
-- check if data to write is available
v.State := CheckPrio1_s;
v.GrantRdy(1) := '1';
v.HndlAfterCtxt := CalcAccess0_s;
-- check if data to write is available (only if IRQ FIFO has space for the response for sure)
if IrqFifoAlmFull = '0' then
v.State := CheckPrio1_s;
v.GrantRdy(1) := '1';
v.HndlAfterCtxt := CalcAccess0_s;
end if;
-- Delay arbitration in simulation to allow TB to react
if Simulation_g then
if r.SimDelCnt /= 4 then
@ -428,6 +449,7 @@ begin
-- Calculate next window to use
when NextWin_s =>
-- Switch to next window if required
v.IrqFifoWrite := '1';
if ((r.HndlPtr = r.HndlWinEnd) and (r.HndlRingbuf = '0')) or (Dma_Resp.Trigger = '1') then
v.HndlWinDone := '1';
v.NewBuffer(r.HndlStream) := '1';
@ -518,7 +540,22 @@ begin
v.NewBuffer(str) := '1';
end if;
end loop;
-- *** IRQ Handling ***
-- Feedback from memory controller
if r.TfDoneReg = '1' then
v.TfDoneCnt := std_logic_vector(unsigned(r.TfDoneCnt) + 1);
end if;
-- Process transfer completion
if (unsigned(r.TfDoneCnt) /= 0) and (IrqFifoEmpty = '0') then
v.IrqFifoRead := '1';
v.TfDoneCnt := std_logic_vector(unsigned(v.TfDoneCnt) - 1);
-- Generate IRQ if required
if IrqFifoGenIrq = '1' then
v.StrIrq(to_integer(unsigned(IrqFifoStream))) := '1';
end if;
end if;
-- *** Assign to signal ***
r_next <= v;
@ -532,6 +569,7 @@ begin
Dma_Cmd <= r.Dma_Cmd;
Dma_Resp_Rdy <= r.Dma_Resp_Rdy;
Ts_Rdy <= r.Ts_Rdy;
StrIrq <= r.StrIrq;
--------------------------------------------
-- Sequential Process
@ -560,6 +598,11 @@ begin
r.Ts_Rdy <= (others => '0');
r.GlbEnaReg <= '0';
r.FirstOngoing <= (others => '0');
r.TfDoneCnt <= (others => '0');
r.TfDoneReg <= '0';
r.IrqFifoWrite <= '0';
r.IrqFifoRead <= '0';
r.StrIrq <= (others => '0');
end if;
end if;
end process;
@ -610,19 +653,38 @@ begin
Grant => GrantPrio3,
Grant_Rdy => r.GrantRdy(3),
Grant_Vld => GrantVld(3)
);
--------------------------------------------
-- Assertions
--------------------------------------------
);
p_assert : process(Clk)
begin
if rising_edge(Clk) then
--assert StreamWidth_g = 8 or StreamWidth_g = 16 or StreamWidth_g = 32 or StreamWidth_g = 64 report "###ERROR###: psi_ms_daq_input: StreamWidth_g must be 8, 16, 32 or 64" severity error;
end if;
end process;
-- *** IRQ Information FIFO ***
-- input assembly
IrqFifoIn(IrqFifoIn'high-1 downto 0) <= std_logic_vector(to_unsigned(r.HndlStream, log2ceil(Streams_g)));
IrqFifoIn(IrqFifoIn'high) <= r.HndlWinDone;
-- Instantiation
i_irq_fifo : entity work.psi_common_sync_fifo
generic map (
Width_g => log2ceil(Streams_g)+1,
Depth_g => Streams_g*4,
AlmFullOn_g => true,
AlmFullLevel_g => Streams_g*3,
RamStyle_g => "distributed"
)
port map (
Clk => Clk,
Rst => Rst,
InData => IrqFifoIn,
InVld => r.IrqFifoWrite,
OutData => IrqFifoOut,
OutRdy => r.IrqFifoRead,
AlmFull => IrqFifoAlmFull,
Empty => IrqFifoEmpty
);
-- Output disassembly
IrqFifoStream <= IrqFifoOut(IrqFifoOut'high-1 downto 0);
IrqFifoGenIrq <= IrqFifoOut(IrqFifoOut'high);
end;

1
sim/config.tcl
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@ -25,6 +25,7 @@ add_sources $LibPath {
psi_common/hdl/psi_common_async_fifo.vhd \
psi_common/hdl/psi_common_arb_priority.vhd \
psi_common/hdl/psi_common_arb_round_robin.vhd \
psi_common/hdl/psi_common_sync_fifo.vhd \
} -tag lib
# project sources

40
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd
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@ -69,6 +69,7 @@ architecture sim of psi_ms_daq_daq_sm_tb is
signal Rst : std_logic := '0';
signal GlbEna : std_logic := '1';
signal StrEna : std_logic_vector(Streams_g-1 downto 0) := (others => '1');
signal StrIrq : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
signal Inp_HasLast : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
signal Inp_Level : t_aslv16(Streams_g-1 downto 0) := (others => (others => '0'));
signal Ts_Vld : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
@ -79,6 +80,7 @@ architecture sim of psi_ms_daq_daq_sm_tb is
signal Dma_Resp : DaqDma2DaqSm_Resp_t := ( Size => (others => '0'), Trigger => '0', Stream => 0);
signal Dma_Resp_Vld : std_logic := '0';
signal Dma_Resp_Rdy : std_logic := '0';
signal TfDone : std_logic := '0';
signal CtxStr_Cmd : ToCtxStr_t;
signal CtxStr_Resp : FromCtx_t := (others => (others => '0'));
signal CtxWin_Cmd : ToCtxWin_t;
@ -103,6 +105,7 @@ begin
Rst => Rst,
GlbEna => GlbEna,
StrEna => StrEna,
StrIrq => StrIrq,
Inp_HasLast => Inp_HasLast,
Inp_Level => Inp_Level,
Ts_Vld => Ts_Vld,
@ -113,6 +116,7 @@ begin
Dma_Resp => Dma_Resp,
Dma_Resp_Vld => Dma_Resp_Vld,
Dma_Resp_Rdy => Dma_Resp_Rdy,
TfDone => TfDone,
CtxStr_Cmd => CtxStr_Cmd,
CtxStr_Resp => CtxStr_Resp,
CtxWin_Cmd => CtxWin_Cmd,
@ -173,37 +177,37 @@ begin
-- single_simple
wait until NextCase = 0;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_simple.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_simple.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- priorities
wait until NextCase = 1;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_priorities.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_priorities.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- single_window
wait until NextCase = 2;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_window.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_window.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- multi_window
wait until NextCase = 3;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_multi_window.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_multi_window.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_enable.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_irq.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
wait;
@ -215,37 +219,37 @@ begin
-- single_simple
wait until NextCase = 0;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_simple.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_simple.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- priorities
wait until NextCase = 1;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_priorities.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_priorities.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- single_window
wait until NextCase = 2;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_window.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_window.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- multi_window
wait until NextCase = 3;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_multi_window.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_multi_window.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_enable.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_irq.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
wait;
@ -257,37 +261,37 @@ begin
-- single_simple
wait until NextCase = 0;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_simple.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_simple.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- priorities
wait until NextCase = 1;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_priorities.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_priorities.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- single_window
wait until NextCase = 2;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_window.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_window.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- multi_window
wait until NextCase = 3;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_multi_window.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_multi_window.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_enable.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_irq.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
wait;

8
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_enable.vhd
View File

@ -28,6 +28,7 @@ package psi_ms_daq_daq_sm_tb_case_enable is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -39,15 +40,18 @@ package psi_ms_daq_daq_sm_tb_case_enable is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
@ -69,6 +73,7 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -196,6 +201,7 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
@ -287,9 +293,11 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
begin
-- Disabled stream does not react (global)

8
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_irq.vhd
View File

@ -28,6 +28,7 @@ package psi_ms_daq_daq_sm_tb_case_irq is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -39,15 +40,18 @@ package psi_ms_daq_daq_sm_tb_case_irq is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
@ -69,6 +73,7 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -83,6 +88,7 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
@ -92,9 +98,11 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure DMA_RESP: No Content added yet!" severity warning;

8
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_multi_window.vhd
View File

@ -27,6 +27,7 @@ package psi_ms_daq_daq_sm_tb_case_multi_window is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -38,15 +39,18 @@ package psi_ms_daq_daq_sm_tb_case_multi_window is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
@ -68,6 +72,7 @@ package body psi_ms_daq_daq_sm_tb_case_multi_window is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -144,6 +149,7 @@ package body psi_ms_daq_daq_sm_tb_case_multi_window is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
@ -244,9 +250,11 @@ package body psi_ms_daq_daq_sm_tb_case_multi_window is
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
begin
-- Linear write with Overwrite

8
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_priorities.vhd
View File

@ -28,6 +28,7 @@ package psi_ms_daq_daq_sm_tb_case_priorities is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -39,15 +40,18 @@ package psi_ms_daq_daq_sm_tb_case_priorities is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
@ -71,6 +75,7 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -132,6 +137,7 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
@ -172,9 +178,11 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
variable Stream_v : integer;
begin

8
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_simple.vhd
View File

@ -27,6 +27,7 @@ package psi_ms_daq_daq_sm_tb_case_single_simple is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -38,15 +39,18 @@ package psi_ms_daq_daq_sm_tb_case_single_simple is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
@ -68,6 +72,7 @@ package body psi_ms_daq_daq_sm_tb_case_single_simple is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -168,6 +173,7 @@ package body psi_ms_daq_daq_sm_tb_case_single_simple is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
@ -270,9 +276,11 @@ package body psi_ms_daq_daq_sm_tb_case_single_simple is
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
variable StartTime_v : time;
begin

8
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_window.vhd
View File

@ -27,6 +27,7 @@ package psi_ms_daq_daq_sm_tb_case_single_window is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -38,15 +39,18 @@ package psi_ms_daq_daq_sm_tb_case_single_window is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
@ -68,6 +72,7 @@ package body psi_ms_daq_daq_sm_tb_case_single_window is
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -144,6 +149,7 @@ package body psi_ms_daq_daq_sm_tb_case_single_window is
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
@ -225,9 +231,11 @@ package body psi_ms_daq_daq_sm_tb_case_single_window is
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
begin
-- Linear write with Overwrite