AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

DEVEL: Implemented enable/disable tests

Browse Source
This commit is contained in:
Oliver Bruendler
2018-07-10 13:41:47 +02:00
parent cac231412b
commit 7e6b610f92
10 changed files with 792 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
hdl/psi_ms_daq_daq_sm.vhd
View File

@ -24,7 +24,7 @@ library work;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
-- $$ testcases=single_simple,priorities,single_window,multi_window$$
-- $$ testcases=single_simple,priorities,single_window,multi_window,enable,irq $$
-- $$ processes=control,dma_cmd,dma_resp,ctx $$
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg $$
entity psi_ms_daq_daq_sm is
@ -41,8 +41,8 @@ entity psi_ms_daq_daq_sm is
-- Control signals
Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=control,dma_cmd,dma_resp,ctx $$
Rst : in std_logic; -- $$ proc=control $$
GlbEna : in std_logic; -- $$ proc=control $$
StrEna : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control $$
GlbEna : in std_logic; -- $$ proc=control; lowactive=true $$
StrEna : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control; lowactive=true $$
-- Input logic Connections
Inp_HasLast : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control $$
@ -126,6 +126,7 @@ architecture rtl of psi_ms_daq_daq_sm is
WinProtected : std_logic_vector(Streams_g-1 downto 0); -- Set if the current window is not yet available
NewBuffer : std_logic_vector(Streams_g-1 downto 0);
FirstAfterEna : std_logic_vector(Streams_g-1 downto 0);
FirstOngoing : std_logic_vector(Streams_g-1 downto 0);
GrantRdy : std_logic_vector(3 downto 1);
GrantVldReg : std_logic_vector(3 downto 1);
State : State_t;
@ -203,7 +204,7 @@ begin
-- *** Check Availability of a full burst ***
for str in 0 to Streams_g-1 loop
if unsigned(Inp_Level(str)) >= MinBurstSize_g then
v.InpDataAvail(str) := '1';
v.InpDataAvail(str) := r.StrEnaReg(str) and r.GlbEnaReg;
else
v.InpDataAvail(str) := '0';
end if;
@ -337,9 +338,16 @@ begin
-- State handling
v.State := ReadCtxWin_s;
-- Ensure that command and response are both handled as first or not
if r.HndlAfterCtxt = ProcResp0_s then -- responses
-- nothing to do
else -- command
v.FirstAfterEna(r.HndlStream) := '0';
v.FirstOngoing(r.HndlStream) := r.FirstAfterEna(r.HndlStream);
end if;
-- Update values for first access
if r.FirstAfterEna(r.HndlStream) = '1' then
v.FirstAfterEna(r.HndlStream) := '0';
if v.FirstOngoing(r.HndlStream) = '1' then
v.HndlWinEnd := std_logic_vector(unsigned(r.HndlBufstart) + unsigned(r.HndlWinSize));
v.HndlPtr := r.HndlBufstart;
v.HndlWincur := (others => '0');
@ -409,7 +417,8 @@ begin
-- *** Handle response ***
-- Calculate next pointer
when ProcResp0_s =>
v.OpenCommand(r.HndlStream) := '0';
v.OpenCommand(r.HndlStream) := '0';
v.FirstOngoing(r.HndlStream) := '0';
v.HndlPtr := std_logic_vector(unsigned(r.HndlPtr) + unsigned(Dma_Resp.Size));
v.State := NextWin_s;
-- Update window information step 1
@ -419,7 +428,6 @@ begin
-- Calculate next window to use
when NextWin_s =>
-- Switch to next window if required
assert unsigned(r.HndlPtr) <= unsigned(r.HndlWinEnd) report "###ERROR###: psi_ms_daq_daq_sm internal error, Pointer is beyond window end" severity error;
if ((r.HndlPtr = r.HndlWinEnd) and (r.HndlRingbuf = '0')) or (Dma_Resp.Trigger = '1') then
v.HndlWinDone := '1';
v.NewBuffer(r.HndlStream) := '1';
@ -551,6 +559,7 @@ begin
r.Dma_Resp_Rdy <= '0';
r.Ts_Rdy <= (others => '0');
r.GlbEnaReg <= '0';
r.FirstOngoing <= (others => '0');
end if;
end if;
end process;

2
sim/config.tcl
View File

@ -50,6 +50,8 @@ add_sources "../tb" {
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_simple.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_priorities.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_multi_window.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_enable.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_irq.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd \
} -tag tb

73
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd
View File

@ -27,6 +27,8 @@ library work;
use work.psi_ms_daq_daq_sm_tb_case_priorities.all;
use work.psi_ms_daq_daq_sm_tb_case_single_window.all;
use work.psi_ms_daq_daq_sm_tb_case_multi_window.all;
use work.psi_ms_daq_daq_sm_tb_case_enable.all;
use work.psi_ms_daq_daq_sm_tb_case_irq.all;
------------------------------------------------------------
-- Entity Declaration
@ -42,7 +44,7 @@ architecture sim of psi_ms_daq_daq_sm_tb is
constant Streams_g : positive := 4;
constant StreamPrio_g : t_ainteger := (1, 2, 3, 1);
constant StreamWidth_g : t_ainteger := (8, 16, 32, 64);
constant Windows_g : positive := 4;
constant Windows_g : positive := 8;
constant MinBurstSize_g : positive := 512;
constant MaxBurstSize_g : positive := 512;
@ -65,6 +67,8 @@ architecture sim of psi_ms_daq_daq_sm_tb is
-- *** DUT Signals ***
signal Clk : std_logic := '1';
signal Rst : std_logic := '0';
signal GlbEna : std_logic := '1';
signal StrEna : std_logic_vector(Streams_g-1 downto 0) := (others => '1');
signal Inp_HasLast : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
signal Inp_Level : t_aslv16(Streams_g-1 downto 0) := (others => (others => '0'));
signal Ts_Vld : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
@ -97,8 +101,8 @@ begin
port map (
Clk => Clk,
Rst => Rst,
GlbEna => '1',
StrEna => (others => '1'),
GlbEna => GlbEna,
StrEna => StrEna,
Inp_HasLast => Inp_HasLast,
Inp_Level => Inp_Level,
Ts_Vld => Ts_Vld,
@ -132,7 +136,12 @@ begin
-- multi_window
NextCase <= 3;
wait until ProcessDone = AllProcessesDone_c;
-- enable
NextCase <= 4;
wait until ProcessDone = AllProcessesDone_c;
-- irq
NextCase <= 5;
wait until ProcessDone = AllProcessesDone_c;
TbRunning <= false;
wait;
end process;
@ -164,25 +173,37 @@ begin
-- single_simple
wait until NextCase = 0;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_simple.control(Clk, Rst, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_simple.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- priorities
wait until NextCase = 1;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_priorities.control(Clk, Rst, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_priorities.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- single_window
wait until NextCase = 2;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_single_window.control(Clk, Rst, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_single_window.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- multi_window
wait until NextCase = 3;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_multi_window.control(Clk, Rst, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
work.psi_ms_daq_daq_sm_tb_case_multi_window.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.control(Clk, Rst, GlbEna, StrEna, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
wait;
@ -215,6 +236,18 @@ begin
work.psi_ms_daq_daq_sm_tb_case_multi_window.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.dma_cmd(Clk, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
wait;
end process;
@ -245,6 +278,18 @@ begin
work.psi_ms_daq_daq_sm_tb_case_multi_window.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.dma_resp(Clk, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
wait;
end process;
@ -275,6 +320,18 @@ begin
work.psi_ms_daq_daq_sm_tb_case_multi_window.ctx(Clk, CtxStr_Cmd, CtxStr_Resp, CtxWin_Cmd, CtxWin_Resp, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_ctx_c) <= '1';
-- enable
wait until NextCase = 4;
ProcessDone(TbProcNr_ctx_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_enable.ctx(Clk, CtxStr_Cmd, CtxStr_Resp, CtxWin_Cmd, CtxWin_Resp, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_ctx_c) <= '1';
-- irq
wait until NextCase = 5;
ProcessDone(TbProcNr_ctx_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_irq.ctx(Clk, CtxStr_Cmd, CtxStr_Resp, CtxWin_Cmd, CtxWin_Resp, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_ctx_c) <= '1';
wait;
end process;

568
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_enable.vhd Normal file
View File

@ -0,0 +1,568 @@
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_sm_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_sm_tb_case_enable is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
signal Ts_Rdy : in std_logic_vector;
signal Ts_Data : inout t_aslv64;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_cmd (
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
constant Generics_c : Generics_t);
procedure ctx (
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : inout FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_sm_tb_case_enable is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
signal Ts_Rdy : in std_logic_vector;
signal Ts_Data : inout t_aslv64;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
print(">> -- enable --");
-- Disabled stream does not react (global)
print(">> Disabled stream does not react (global)");
InitTestCase(Clk, Rst);
GlbEna <= '0';
TestCase := 0;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
for i in 0 to 3 loop
Inp_Level(i) <= LvlThreshold_c;
end loop;
wait for 1 us;
for i in 0 to 3 loop
Inp_Level(i) <= (others => '0');
end loop;
GlbEna <= '1';
ControlWaitCompl(Clk);
-- Disabled stream does not react (per stream)
print(">> Disabled stream does not react (per stream)");
InitTestCase(Clk, Rst);
TestCase := 1;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
for i in 0 to 3 loop
StrEna(i) <= '0';
wait for 20 ns;
Inp_Level(i) <= LvlThreshold_c;
wait for 1 us;
Inp_Level(i) <= (others => '0');
StrEna(i) <= '1';
end loop;
ControlWaitCompl(Clk);
-- Disabled stream does not influence arbitration
print(">> Disabled stream does not react (per stream)");
InitTestCase(Clk, Rst);
TestCase := 2;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
StrEna(0) <= '0';
wait for 20 ns;
Inp_Level(0) <= LvlThreshold_c;
wait for 200 ns;
Inp_Level(1) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
Inp_Level(1) <= (others => '0');
StrEna(0) <= '1';
ControlWaitCompl(Clk);
-- Start with Sample 0, Window 0 after enable (global)
print("Start with Sample 0, Window 0 after enable (global)");
InitTestCase(Clk, Rst);
TestCase := 3;
for i in 0 to 2 loop
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
wait for 500 ns;
Inp_Level(1) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(1) <= (others => '0');
wait for 500 ns;
-- Shortly disable al lstreams after first access
if i = 1 then
GlbEna <= '0';
wait for 20 ns;
GlbEna <= '1';
wait for 20 ns;
end if;
end loop;
ControlWaitCompl(Clk);
-- Start with Sample 0, Window 0 after enable (per stream)
-- only reset stream 0
print("Start with Sample 0, Window 0 after enable (per stream)");
InitTestCase(Clk, Rst);
TestCase := 4;
for i in 0 to 2 loop
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
wait for 500 ns;
Inp_Level(1) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(1) <= (others => '0');
wait for 500 ns;
-- Shortly disable al lstreams after first access
if i = 1 then
StrEna(0) <= '0';
wait for 20 ns;
StrEna(0) <= '1';
wait for 20 ns;
end if;
end loop;
ControlWaitCompl(Clk);
-- 4k Boundary (is 4k boundary reset correctly for the first sample)
print("4k Boundary");
InitTestCase(Clk, Rst);
TestCase := 5;
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
StrEna(0) <= '0';
wait for 20 ns;
StrEna(0) <= '1';
wait for 20 ns;
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
ControlWaitCompl(Clk);
end procedure;
procedure dma_cmd (
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
variable StartTime_v : time;
begin
-- Disabled stream does not react (global)
WaitForCase(0, Clk);
StartTime_v := now;
while now < StartTime_v + 1 us loop
StdlCompare(0, Dma_Cmd_Vld, "Unexpected DMA command");
wait until rising_edge(Clk);
end loop;
ProcDone(2) := '1';
-- Disabled stream does not react (per stream)
WaitForCase(1, Clk);
for str in 0 to 3 loop
StartTime_v := now;
while now < StartTime_v + 1 us loop
StdlCompare(0, Dma_Cmd_Vld, "Unexpected DMA command");
wait until rising_edge(Clk);
end loop;
end loop;
ProcDone(2) := '1';
-- Disabled stream does not influence arbitration
WaitForCase(2, Clk);
-- Win0
ExpectDmaCmdAuto( Stream => 1, MaxSize => 4096, Msg => "Wr0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- Start with Sampe 0, Window 0 after enable (global)
WaitForCase(3, Clk);
-- First after reset
ExpectDmaCmd( Stream => 0, Address => 16#01200000#, MaxSize => 4096, Msg=>"0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmd( Stream => 1, Address => 16#01210000#, MaxSize => 4096, Msg=>"0.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- Normal
ExpectDmaCmd( Stream => 0, Address => 16#01208000#, MaxSize => 4096, Msg=>"1.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmd( Stream => 1, Address => 16#01218000#, MaxSize => 4096, Msg=>"1.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- First after disable
ExpectDmaCmd( Stream => 0, Address => 16#01200000#, MaxSize => 4096, Msg=>"2.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmd( Stream => 1, Address => 16#01210000#, MaxSize => 4096, Msg=>"2.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- Start with Sampe 0, Window 0 after enable (per stream)
WaitForCase(4, Clk);
-- First after reset
ExpectDmaCmd( Stream => 0, Address => 16#01200000#, MaxSize => 4096, Msg=>"0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmd( Stream => 1, Address => 16#01210000#, MaxSize => 4096, Msg=>"0.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- Normal
ExpectDmaCmd( Stream => 0, Address => 16#01208000#, MaxSize => 4096, Msg=>"1.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmd( Stream => 1, Address => 16#01218000#, MaxSize => 4096, Msg=>"1.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- First after disable for stream 0
ExpectDmaCmd( Stream => 0, Address => 16#01200000#, MaxSize => 4096, Msg=>"2.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- Stream 1 continues normally
ExpectDmaCmd( Stream => 1, Address => 16#01218000#, MaxSize => 4096, Msg=>"2.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- 4k Boundary
WaitForCase(5, Clk);
-- First after reset
ExpectDmaCmd( Stream => 0, Address => 16#01200800#, MaxSize => 2048, Msg=>"0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- Normal
ExpectDmaCmd( Stream => 0, Address => 16#01208000#, MaxSize => 4096, Msg=>"0.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- First after disable for stream 0
ExpectDmaCmd( Stream => 0, Address => 16#01200800#, MaxSize => 2048, Msg=>"1.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- Normal
ExpectDmaCmd( Stream => 0, Address => 16#01208000#, MaxSize => 4096, Msg=>"1.1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
end procedure;
procedure dma_resp (
signal Clk : in std_logic;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Disabled stream does not react (global)
WaitForCase(0, Clk);
ProcDone(1) := '1';
-- Disabled stream does not react (per stream)
WaitForCase(1, Clk);
ProcDone(1) := '1';
-- Disabled stream does not influence arbitration
WaitForCase(2, Clk);
ApplyDmaRespAuto( Stream => 1, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ProcDone(1) := '1';
-- Start with Sampe 0, Window 0 after enable (global)
WaitForCase(3, Clk);
for i in 0 to 2 loop
ApplyDmaResp( Stream => 0, Size => 4096, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaResp( Stream => 1, Size => 4096, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
ProcDone(1) := '1';
-- Start with Sampe 0, Window 0 after enable (per stream)
WaitForCase(4, Clk);
for i in 0 to 2 loop
ApplyDmaResp( Stream => 0, Size => 4096, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaResp( Stream => 1, Size => 4096, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
ProcDone(1) := '1';
-- 4k Boundary
WaitForCase(5, Clk);
for i in 0 to 1 loop
for k in 0 to 1 loop
ApplyDmaResp( Stream => 0, Size => 2048+k*2048, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
end loop;
ProcDone(1) := '1';
end procedure;
procedure ctx (
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : inout FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t) is
variable StartTime_v : time;
variable CurPtr_v : integer;
variable BufStart_v : integer;
variable NextPtr_v : integer;
variable WinNext_v : integer;
variable SplWinBefore_v : integer;
variable SplWinAfter_v : integer;
variable TfSize_v : integer;
begin
-- Disabled stream does not react (global)
WaitForCase(0, Clk);
StartTime_v := now;
while now < StartTime_v + 1 us loop
StdlCompare(0, CtxStr_Cmd.WenLo, "CtxStr_Cmd.WenLo high unexpectedly");
StdlCompare(0, CtxStr_Cmd.WenHi, "CtxStr_Cmd.WenHi high unexpectedly");
StdlCompare(0, CtxWin_Cmd.WenLo, "CtxWin_Cmd.WenLo high unexpectedly");
StdlCompare(0, CtxWin_Cmd.WenHi, "CtxWin_Cmd.WenHi high unexpectedly");
StdlCompare(0, CtxWin_Cmd.Rd, "CtxWin_Cmd.Rd high unexpectedly");
wait until rising_edge(Clk);
end loop;
ProcDone(0) := '1';
-- Disabled stream does not react (per stream)
WaitForCase(1, Clk);
for str in 0 to 3 loop
StartTime_v := now;
while now < StartTime_v + 1 us loop
StdlCompare(0, CtxStr_Cmd.WenLo, "CtxStr_Cmd.WenLo high unexpectedly");
StdlCompare(0, CtxStr_Cmd.WenHi, "CtxStr_Cmd.WenHi high unexpectedly");
StdlCompare(0, CtxWin_Cmd.WenLo, "CtxWin_Cmd.WenLo high unexpectedly");
StdlCompare(0, CtxWin_Cmd.WenHi, "CtxWin_Cmd.WenHi high unexpectedly");
StdlCompare(0, CtxWin_Cmd.Rd, "CtxWin_Cmd.Rd high unexpectedly");
wait until rising_edge(Clk);
end loop;
end loop;
ProcDone(0) := '1';
-- Disabled stream does not influence arbitration
WaitForCase(2, Clk);
ExpCtxFullBurstAuto( Stream => 1, Msg => "Wr0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- Start with Sampe 0, Window 0 after enable (global)
WaitForCase(3, Clk);
for i in 0 to 2 loop
for str in 0 to 1 loop
-- Read for calculation of access
BufStart_v := 16#01200000# + 16#00010000#*str;
CurPtr_v := BufStart_v + 16#8000#;
if i = 1 then
NextPtr_v := CurPtr_v + 4096;
WinNext_v := 2;
SplWinBefore_v := 4096/(StreamWidth_g(str)/8);
else
NextPtr_v := BufStart_v + 4096;
WinNext_v := 0;
SplWinBefore_v := 0;
end if;
SplWinAfter_v := SplWinBefore_v + 4096/(StreamWidth_g(str)/8);
ExpCtxRead( Stream => Str,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => CurPtr_v,
Wincnt => 4,
Wincur => 2,
WinSel => WinNext_v,
SamplesWin => SplWinBefore_v,
Msg => "a" & to_string(i) & "." & to_string(str),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Read for update
ExpCtxRead( Stream => Str,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => CurPtr_v,
Wincnt => 4,
Wincur => WinNext_v,
WinSel => WinNext_v,
SamplesWin => SplWinBefore_v,
Msg => "b" & to_string(i) & "." & to_string(str),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Write of update
ExpCtxWrite( Stream => Str,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => NextPtr_v,
Wincnt => 4,
Wincur => WinNext_v,
WinNext => WinNext_v,
SamplesWin => SplWinAfter_v,
WinLast => NextPtr_v-StreamWidth_g(str)/8,
Msg => "" & to_string(i) & "." & to_string(str),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxWin_Cmd => CtxWin_Cmd);
end loop;
end loop;
ProcDone(0) := '1';
-- Start with Sampe 0, Window 0 after enable (per stream)
WaitForCase(4, Clk);
for i in 0 to 2 loop
for str in 0 to 1 loop
-- Read for calculation of access
BufStart_v := 16#01200000# + 16#00010000#*str;
CurPtr_v := BufStart_v + 16#8000#;
if (i = 0) or (i = 2 and str = 0) then
NextPtr_v := BufStart_v + 4096;
WinNext_v := 0;
SplWinBefore_v := 0;
else
NextPtr_v := CurPtr_v + 4096;
WinNext_v := 2;
SplWinBefore_v := 4096/(StreamWidth_g(str)/8);
end if;
SplWinAfter_v := SplWinBefore_v + 4096/(StreamWidth_g(str)/8);
ExpCtxRead( Stream => Str,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => CurPtr_v,
Wincnt => 4,
Wincur => 2,
WinSel => WinNext_v,
SamplesWin => SplWinBefore_v,
Msg => "a" & to_string(i) & "." & to_string(str),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Read for update
ExpCtxRead( Stream => Str,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => CurPtr_v,
Wincnt => 4,
Wincur => WinNext_v,
WinSel => WinNext_v,
SamplesWin => SplWinBefore_v,
Msg => "b" & to_string(i) & "." & to_string(str),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Write of update
ExpCtxWrite( Stream => Str,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => NextPtr_v,
Wincnt => 4,
Wincur => WinNext_v,
WinNext => WinNext_v,
SamplesWin => SplWinAfter_v,
WinLast => NextPtr_v-StreamWidth_g(str)/8,
Msg => "" & to_string(i) & "." & to_string(str),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxWin_Cmd => CtxWin_Cmd);
end loop;
end loop;
ProcDone(0) := '1';
-- 4k Boundary
WaitForCase(5, Clk);
for i in 0 to 3 loop
-- Read for calculation of access
BufStart_v := 16#01200800#;
CurPtr_v := 16#01208000#;
-- If first after reset/enable
if (i = 0) or (i = 2) then
TfSize_v := 2048;
NextPtr_v := BufStart_v + TfSize_v;
WinNext_v := 0;
SplWinBefore_v := 0;
else
TfSize_v := 4096;
NextPtr_v := CurPtr_v + TfSize_v;
WinNext_v := 2;
SplWinBefore_v := 4096/(StreamWidth_g(0)/8);
end if;
SplWinAfter_v := SplWinBefore_v + TfSize_v/(StreamWidth_g(0)/8);
ExpCtxRead( Stream => 0,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => CurPtr_v,
Wincnt => 4,
Wincur => 2,
WinSel => WinNext_v,
SamplesWin => SplWinBefore_v,
Msg => "a" & to_string(i),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Read for update
ExpCtxRead( Stream => 0,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => CurPtr_v,
Wincnt => 4,
Wincur => WinNext_v,
WinSel => WinNext_v,
SamplesWin => SplWinBefore_v,
Msg => "b" & to_string(i),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Write of update
ExpCtxWrite( Stream => 0,
BufStart => BufStart_v,
WinSize => 16#00004000#,
Overwrite => '1',
Ptr => NextPtr_v,
Wincnt => 4,
Wincur => WinNext_v,
WinNext => WinNext_v,
SamplesWin => SplWinAfter_v,
WinLast => NextPtr_v-StreamWidth_g(0)/8,
Msg => "c" & to_string(i),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxWin_Cmd => CtxWin_Cmd);
end loop;
ProcDone(0) := '1';
end procedure;
end;

114
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_irq.vhd Normal file
View File

@ -0,0 +1,114 @@
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_sm_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_sm_tb_case_irq is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
signal Ts_Rdy : in std_logic_vector;
signal Ts_Data : inout t_aslv64;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_cmd (
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
constant Generics_c : Generics_t);
procedure ctx (
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : inout FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_sm_tb_case_irq is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
signal Ts_Rdy : in std_logic_vector;
signal Ts_Data : inout t_aslv64;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure CONTROL: No Content added yet!" severity warning;
end procedure;
procedure dma_cmd (
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure DMA_CMD: No Content added yet!" severity warning;
end procedure;
procedure dma_resp (
signal Clk : in std_logic;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure DMA_RESP: No Content added yet!" severity warning;
end procedure;
procedure ctx (
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : inout FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure CTX: No Content added yet!" severity warning;
end procedure;
end;

4
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_multi_window.vhd
View File

@ -25,6 +25,8 @@ package psi_ms_daq_daq_sm_tb_case_multi_window is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -64,6 +66,8 @@ package body psi_ms_daq_daq_sm_tb_case_multi_window is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;

4
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_priorities.vhd
View File

@ -26,6 +26,8 @@ package psi_ms_daq_daq_sm_tb_case_priorities is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -67,6 +69,8 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;

4
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_simple.vhd
View File

@ -25,6 +25,8 @@ package psi_ms_daq_daq_sm_tb_case_single_simple is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -64,6 +66,8 @@ package body psi_ms_daq_daq_sm_tb_case_single_simple is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;

4
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_window.vhd
View File

@ -25,6 +25,8 @@ package psi_ms_daq_daq_sm_tb_case_single_window is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
@ -64,6 +66,8 @@ package body psi_ms_daq_daq_sm_tb_case_single_window is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;

12
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_pkg.vhd
View File

@ -31,7 +31,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
constant StreamPrio_g : t_ainteger := (1, 2, 3, 1);
constant StreamWidth_g : t_ainteger := (8, 16, 32, 64);
constant MinBurstSize_g : positive := 512;
constant Windows_g : positive := 4;
constant Windows_g : positive := 8;
constant Streams_g : positive := 4;
------------------------------------------------------------
@ -72,6 +72,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
Overwrite : in std_logic := '0';
Wincnt : in integer := 2;
Wincur : in integer := 0;
WinSel : in integer := -1;
SamplesWin : in integer;
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -294,6 +295,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
Overwrite : in std_logic := '0';
Wincnt : in integer := 2;
Wincur : in integer := 0;
WinSel : in integer := -1;
SamplesWin : in integer;
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -301,7 +303,13 @@ package body psi_ms_daq_daq_sm_tb_pkg is
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "") is
variable WindowSel_v : integer;
begin
if WinSel = -1 then
WindowSel_v := Wincur;
else
WindowSel_v := WinSel;
end if;
for acc in 0 to 3 loop -- 3 read accesses are expected for stream context, 1 for window context
wait until rising_edge(Clk) and ((CtxStr_Cmd.Rd = '1') or (CtxWin_Cmd.Rd = '1'));
CtxStr_Resp.RdatLo <= (others => '0');
@ -323,7 +331,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
end case;
elsif CtxWin_Cmd.Rd = '1' then
IntCompare(Stream, CtxWin_Cmd.Stream, "ApplyContext.Win: Wrong stream number - " & Msg);
IntCompare(Wincur, CtxWin_Cmd.Window, "ApplyContext.Win: Wrong window number - " & Msg);
IntCompare(WindowSel_v, CtxWin_Cmd.Window, "ApplyContext.Win: Wrong window number - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenLo, "ApplyContext.Win: WenLo asserted - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenHi, "ApplyContext.Win: WenHi asserted - " & Msg);
case CtxWin_Cmd.Sel is