AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

DEVEL: Finished testbench for priority handling

Browse Source
This commit is contained in:
Oliver Bruendler
2018-07-06 11:39:12 +02:00
parent ff29458057
commit eed6158a1f
5 changed files with 455 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
hdl/psi_ms_daq_daq_sm.vhd
View File

@ -28,6 +28,7 @@ library work;
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg $$
entity psi_ms_daq_daq_sm is
generic (
Simulation_g : boolean := false; -- $$ constant=true $$
Streams_g : positive range 1 to 32 := 4; -- $$ constant=4 $$
StreamPrio_g : t_ainteger := (1, 2, 3, 1); -- $$ constant=(1, 2, 3, 1) $$
StreamWidth_g : t_ainteger := (8, 16, 32, 64); -- $$ constant=(8, 16, 32, 64) $$
@ -109,12 +110,13 @@ architecture rtl of psi_ms_daq_daq_sm is
signal GrantVld : std_logic_vector(3 downto 1);
-- Types
type State_t is (Idle_s, CheckPrio1_s, CheckPrio2_s, CheckPrio3_s, TlastCheck_s, ReadCtxStr_s, ReadCtxWin_s, CalcAccess0_s, CalcAccess1_s, ProcResp0_s, NextWin_s, WriteCtx_s);
type State_t is (Idle_s, CheckPrio1_s, CheckPrio2_s, CheckPrio3_s, CheckResp_s, TlastCheck_s, ReadCtxStr_s, ReadCtxWin_s, CalcAccess0_s, CalcAccess1_s, ProcResp0_s, NextWin_s, WriteCtx_s);
-- Two process method
type two_process_r is record
InpDataAvail : std_logic_vector(Streams_g-1 downto 0);
DataAvailMasked : std_logic_vector(Streams_g-1 downto 0);
DataAvailArbIn : std_logic_vector(Streams_g-1 downto 0);
DataPending : std_logic_vector(Streams_g-1 downto 0);
OpenCommand : std_logic_vector(Streams_g-1 downto 0);
WinProtected : std_logic_vector(Streams_g-1 downto 0); -- Set if the current window is not yet available
NewBuffer : std_logic_vector(Streams_g-1 downto 0);
@ -149,6 +151,7 @@ architecture rtl of psi_ms_daq_daq_sm is
Dma_Cmd_Vld : std_logic;
Dma_Resp_Rdy : std_logic;
Ts_Rdy : std_logic_vector(Streams_g-1 downto 0);
SimDelCnt : integer range 0 to 4;
end record;
signal r, r_next : two_process_r;
@ -197,7 +200,8 @@ begin
v.InpDataAvail(str) := '0';
end if;
end loop;
v.DataAvailMasked := r.InpDataAvail and (not r.OpenCommand) and (not r.WinProtected); -- Do not arbitrate new commands on streams that already have a command
v.DataAvailArbIn := r.InpDataAvail and (not r.OpenCommand) and (not r.WinProtected); -- Do not arbitrate new commands on streams that already have a command
v.DataPending := r.InpDataAvail and (not r.WinProtected); -- Do not prevent lower priority channels from access if the window of a higher priority stream is protected
-- *** Select level of currently handled FIFO ***
v.HndlLevel := Inp_Level(r.HndlStream);
@ -208,47 +212,62 @@ begin
when Idle_s =>
v.HndlCtxCnt := 0;
v.HndlWinDone := '0';
-- process response
if Dma_Resp_Vld = '1' then
v.State := ReadCtxStr_s;
v.HndlAfterCtxt := ProcResp0_s;
v.HndlStream := Dma_Resp.Stream;
-- check if data to write is available
else
v.State := CheckPrio1_s;
v.GrantRdy(1) := '1';
v.HndlAfterCtxt := CalcAccess0_s;
-- check if data to write is available
v.State := CheckPrio1_s;
v.GrantRdy(1) := '1';
v.HndlAfterCtxt := CalcAccess0_s;
-- Delay arbitration in simulation to allow TB to react
if Simulation_g then
if r.SimDelCnt /= 4 then
v.State := Idle_s;
v.GrantRdy(1) := '0';
v.SimDelCnt := r.SimDelCnt + 1;
else
v.SimDelCnt := 0;
end if;
end if;
-- *** Check for next stream to handle ***
when CheckPrio1_s =>
-- Handle command if prio 1 data is available
if r.GrantVldReg(1) = '1' then
v.State := ReadCtxStr_s;
v.HndlStream := GetStreamNrFromGrant(r.GrantPrio1Reg, 1);
-- If data is still pending, check for responses to schedule next transfer
elsif unsigned(GetBitsOfStreamPrio(r.DataPending, 1)) /= 0 then
v.State := CheckResp_s;
-- Otherwise check lower priority streams
else
v.State := CheckPrio2_s;
v.GrantRdy(2) := '1';
end if;
when CheckPrio2_s =>
-- Handle command if prio 2 data is available
if r.GrantVldReg(2) = '1' then
v.State := ReadCtxStr_s;
v.HndlStream := GetStreamNrFromGrant(r.GrantPrio2Reg, 2);
-- If data is still pending, check for responses to schedule next transfer
elsif unsigned(GetBitsOfStreamPrio(r.DataPending, 2)) /= 0 then
v.State := CheckResp_s;
-- Otherwise check lower priority streams
else
v.State := CheckPrio3_s;
v.GrantRdy(3) := '1';
end if;
when CheckPrio3_s =>
-- Handle command if prio 2 data is available
if r.GrantVldReg(3) = '1' then
v.State := ReadCtxStr_s;
v.HndlStream := GetStreamNrFromGrant(r.GrantPrio3Reg, 3);
-- Otherwise check for frame ends
else
v.State := TlastCheck_s;
end if;
when TlastCheck_s =>
v.State := Idle_s;
v.State := CheckResp_s;
v.WinProtected := (others => '0'); -- No bursts where available on any stream, so all of them were checked and we can retry whether SW emptied a window.
for idx in 0 to Streams_g-1 loop
if r.HasLastReg(idx) = '1' then
@ -257,6 +276,16 @@ begin
end if;
end loop;
when CheckResp_s =>
-- Handle response if one is pending (less important thandata transer, therefore at the end)
if Dma_Resp_Vld = '1' then
v.State := ReadCtxStr_s;
v.HndlAfterCtxt := ProcResp0_s;
v.HndlStream := Dma_Resp.Stream;
else
v.State := Idle_s;
end if;
-- *** Read Context Memory ***
-- Read information from stream memory
when ReadCtxStr_s =>
@ -468,8 +497,11 @@ begin
if rising_edge(Clk) then
r <= r_next;
if Rst = '1' then
if Simulation_g then
r.SimDelCnt <= 0;
end if;
r.InpDataAvail <= (others => '0');
r.DataAvailMasked <= (others => '0');
r.DataAvailArbIn <= (others => '0');
r.GrantRdy <= (others => '0');
r.HndlStream <= 0;
r.State <= Idle_s;
@ -491,7 +523,7 @@ begin
-- Component Instantiation
--------------------------------------------
-- *** Round Robin Arbiter - Prio 1 ***
AvailPrio1 <= GetBitsOfStreamPrio(r.DataAvailMasked, 1);
AvailPrio1 <= GetBitsOfStreamPrio(r.DataAvailArbIn, 1);
i_rrarb_1 : entity work.psi_common_arb_round_robin
generic map (
Size_g => count(StreamPrio_g, 1)
@ -506,7 +538,7 @@ begin
);
-- *** Round Robin Arbiter - Prio 2 ***
AvailPrio2 <= GetBitsOfStreamPrio(r.DataAvailMasked, 2);
AvailPrio2 <= GetBitsOfStreamPrio(r.DataAvailArbIn, 2);
i_rrarb_2 : entity work.psi_common_arb_round_robin
generic map (
Size_g => count(StreamPrio_g, 2)
@ -521,7 +553,7 @@ begin
);
-- *** Round Robin Arbiter - Prio 3 ***
AvailPrio3 <= GetBitsOfStreamPrio(r.DataAvailMasked, 3);
AvailPrio3 <= GetBitsOfStreamPrio(r.DataAvailArbIn, 3);
i_rrarb_3 : entity work.psi_common_arb_round_robin
generic map (
Size_g => count(StreamPrio_g, 3)

1
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd
View File

@ -88,6 +88,7 @@ begin
------------------------------------------------------------
i_dut : entity work.psi_ms_daq_daq_sm
generic map (
Simulation_g => true,
Streams_g => Streams_g,
StreamPrio_g => StreamPrio_g,
StreamWidth_g => StreamWidth_g,

195
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_priorities.vhd
View File

@ -16,6 +16,7 @@ library work;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_common_array_pkg.all;
------------------------------------------------------------
-- Package Header
@ -55,6 +56,8 @@ package psi_ms_daq_daq_sm_tb_case_priorities is
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t);
constant StreamOrder_c : t_ainteger := (3, 0, 1, 2);
end package;
------------------------------------------------------------
@ -73,7 +76,54 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case PRIORITIES Procedure CONTROL: No Content added yet!" severity warning;
print(">> -- priorities --");
-- Check correct order on parallel assertion
InitTestCase(Clk, Rst);
print(">> Check correct order on parallel assertion");
TestCase := 0;
for i in 0 to 3 loop
Inp_Level(i) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(i)'length));
end loop;
for i in 0 to 3 loop
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(Dma_Cmd.Stream) <= (others => '0');
end loop;
ControlWaitCompl(Clk);
-- Round Robin behavior
InitTestCase(Clk, Rst);
print(">> Round Robin behavior");
TestCase := 1;
Inp_Level(0) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(0)'length));
Inp_Level(3) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(3)'length));
Inp_Level(1) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(1)'length));
for i in 0 to 3 loop
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
end loop;
Inp_Level(0) <= (others => '0');
Inp_Level(3) <= (others => '0');
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(1) <= (others => '0');
ControlWaitCompl(Clk);
-- Reassertion of high-priority streams
InitTestCase(Clk, Rst);
print(">> Reassertion of high-priority streams");
TestCase := 2;
Inp_Level(0) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(0)'length));
Inp_Level(1) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(1)'length));
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= std_logic_vector(to_unsigned(Size4k_c/DataWidthBytes_c, Inp_Level(0)'length));
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(1) <= (others => '0');
ControlWaitCompl(Clk);
FinishTestCase;
end procedure;
procedure dma_cmd (
@ -81,8 +131,39 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
variable Stream_v : integer;
begin
assert false report "Case PRIORITIES Procedure DMA_CMD: No Content added yet!" severity warning;
-- Check correct order on parallel assertion
WaitForCase(0, Clk);
for i in 0 to 3 loop
ExpectDmaCmdAuto( Stream => StreamOrder_c(i), MaxSize => Size4k_c,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
end loop;
ProcDone(2) := '1';
-- Round Robin behavior
WaitForCase(1, Clk);
for i in 0 to 1 loop
for s in 0 to 1 loop
ExpectDmaCmdAuto( Stream => choose(s=0, 3, 0), MaxSize => Size4k_c, Msg => "i=" & to_string(i) & ", s=" & to_string(s),
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
end loop;
end loop;
ExpectDmaCmdAuto( Stream => 1, MaxSize => Size4k_c,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- Reassertion of high-priority streams
WaitForCase(2, Clk);
ExpectDmaCmdAuto( Stream => 0, MaxSize => Size4k_c, Msg => "HP0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 1, MaxSize => Size4k_c, Msg => "LP0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 0, MaxSize => Size4k_c, Msg => "HP1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 1, MaxSize => Size4k_c, Msg => "LP1",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
end procedure;
procedure dma_resp (
@ -91,8 +172,41 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
constant Generics_c : Generics_t) is
variable Stream_v : integer;
begin
assert false report "Case PRIORITIES Procedure DMA_RESP: No Content added yet!" severity warning;
-- Check correct order on parallel assertion
WaitForCase(0, Clk);
for i in 0 to 3 loop
ApplyDmaResp( Stream => StreamOrder_c(i), Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
ProcDone(1) := '1';
-- Round Robin behavior
WaitForCase(1, Clk);
for i in 0 to 1 loop
for s in 0 to 1 loop
ApplyDmaResp( Stream => choose(s=0, 3, 0), Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
end loop;
ApplyDmaResp( Stream => 1, Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ProcDone(1) := '1';
-- Reassertion of high-priority streams
WaitForCase(2, Clk);
ApplyDmaResp( Stream => 0, Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaResp( Stream => 1, Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaResp( Stream => 0, Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaResp( Stream => 1, Size => Size4k_c, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ProcDone(1) := '1';
end procedure;
procedure ctx (
@ -102,8 +216,81 @@ package body psi_ms_daq_daq_sm_tb_case_priorities is
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t) is
variable Ptr_v : integer;
variable Stream_v : integer;
variable PtrStr_v : t_ainteger(0 to 3);
variable SplsStr_v : t_ainteger(0 to 3) := (others => 0);
begin
assert false report "Case PRIORITIES Procedure CTX: No Content added yet!" severity warning;
-- Check two 4k Transfers in a row on stream 0
WaitForCase(0, Clk);
-- Requests are handled before responses
for i in 0 to 3 loop
ExpCtxReadAuto( Stream => StreamOrder_c(i),
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
end loop;
for i in 0 to 3 loop
ExpCtxUpdateAuto( Stream => StreamOrder_c(i), tfSize => Size4k_c,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
end loop;
ProcDone(0) := '1';
-- Round Robin behavior
WaitForCase(1, Clk);
PtrStr_v := (16#00000#, 16#10000#, 16#20000#, 16#30000#);
-- First high prio command
ExpCtxReadAuto( Stream => 3,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Second high prio stream can immediately send the next command
ExpCtxReadAuto( Stream => 0,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Wait for response and schnedule next high prio command
ExpCtxUpdateAuto( Stream => 3, tfSize => Size4k_c,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxReadAuto( Stream => 3,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Wait for response and schnedule next high prio command
ExpCtxUpdateAuto( Stream => 0, tfSize => Size4k_c,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxReadAuto( Stream => 0,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- No more high prio data, so low prio command follows
ExpCtxReadAuto( Stream => 1,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- pending responses
ExpCtxUpdateAuto( Stream => 3, tfSize => Size4k_c, Msg => "RobinLast3",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxUpdateAuto( Stream => 0, tfSize => Size4k_c, Msg => "RobinLast0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxUpdateAuto( Stream => 1, tfSize => Size4k_c, Msg => "RobinLast1",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- Reassertion of high-priority streams
WaitForCase(2, Clk);
-- Start high-prio transfer
ExpCtxReadAuto( Stream => 0, Msg => "Start HP0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Start low-prio transfer
ExpCtxReadAuto( Stream => 1, Msg => "Start LP0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- High-prio data available, so wait for high-prio response and restart transfer
ExpCtxUpdateAuto( Stream => 0, tfSize => Size4k_c, Msg => "Finish HP0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxReadAuto( Stream => 0, Msg => "Start HP1",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Low-prio data available, so wait for high-prio response and restart transfer
ExpCtxUpdateAuto( Stream => 1, tfSize => Size4k_c, Msg => "Finish LP0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxReadAuto( Stream => 1, Msg => "Start LP1",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Completion of last high prio transfer
ExpCtxUpdateAuto( Stream => 0, tfSize => Size4k_c, Msg => "Finish HP1",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- Completion of last low prio transfer
ExpCtxUpdateAuto( Stream => 1, tfSize => Size4k_c, Msg => "Finish LP1",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
end procedure;
end;

1
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_simple.vhd
View File

@ -74,6 +74,7 @@ package body psi_ms_daq_daq_sm_tb_case_single_simple is
constant Generics_c : Generics_t) is
variable StartTime_v : time;
begin
print(">> -- single_simple --");
InitTestCase(Clk, Rst);
-- Check Steady behavior

276
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_pkg.vhd
View File

@ -68,7 +68,8 @@ package psi_ms_daq_daq_sm_tb_pkg is
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t);
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "");
procedure ExpCtxWrite( Stream : in integer;
BufStart : in integer := 16#01230000#;
@ -84,7 +85,8 @@ package psi_ms_daq_daq_sm_tb_pkg is
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxWin_Cmd : in ToCtxWin_t);
signal CtxWin_Cmd : in ToCtxWin_t;
Msg : in string := "");
procedure ExpCtxUpdate( Stream : in integer;
TfSize : in integer; -- in bytes
@ -103,7 +105,8 @@ package psi_ms_daq_daq_sm_tb_pkg is
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t);
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "");
procedure ExpCtxFullBurst( Stream : in integer;
TfSize : in integer; -- in bytes
@ -122,14 +125,16 @@ package psi_ms_daq_daq_sm_tb_pkg is
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t);
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "");
procedure ExpectDmaCmd( Stream : in integer;
Address : in integer;
MaxSize : in integer;
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Vld : in std_logic);
signal Dma_Vld : in std_logic;
Msg : in string := "");
-- The DMA response is splilt into "Apply" and "Remove" because the context memory is read in between
procedure ApplyDmaResp( Stream : in integer;
@ -139,7 +144,51 @@ package psi_ms_daq_daq_sm_tb_pkg is
signal Clk : in std_logic;
signal Dma_Resp : out DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : out std_logic;
signal Dma_Resp_Rdy : in std_logic);
signal Dma_Resp_Rdy : in std_logic;
Msg : in string := "");
-- higher level functions
shared variable PtrStr_v : t_ainteger(0 to 3);
shared variable PtrDma_v : t_ainteger(0 to 3);
shared variable SplsStr_v : t_ainteger(0 to 3);
constant BufStart_c : t_ainteger(0 to 3) := (16#01230000#, 16#02230000#, 16#03230000#, 16#04230000#);
procedure ExpCtxReadAuto( Stream : in integer;
WinSize : in integer := 16#00100000#;
Ringbuf : in std_logic := '0';
Overwrite : in std_logic := '0';
Wincnt : in integer := 2;
Wincur : in integer := 0;
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "");
procedure ExpCtxUpdateAuto( Stream : in integer;
TfSize : in integer; -- in bytes
WinSize : in integer := 16#00100000#;
Ringbuf : in std_logic := '0';
Overwrite : in std_logic := '0';
Wincnt : in integer := 2;
Wincur : in integer := 0;
WriteTs : in boolean := false;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "");
procedure ExpectDmaCmdAuto( Stream : in integer;
MaxSize : in integer;
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Vld : in std_logic;
Msg : in string := "");
end package;
@ -154,6 +203,9 @@ package body psi_ms_daq_daq_sm_tb_pkg is
ProcDone := (others => '0');
TestCase := -1;
DmaCmdOpen := 0;
PtrStr_v := BufStart_c;
PtrDma_v := BufStart_c;
SplsStr_v := (others => 0);
wait until rising_edge(Clk);
Rst <= '1';
wait until rising_edge(Clk);
@ -198,16 +250,17 @@ package body psi_ms_daq_daq_sm_tb_pkg is
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t) is
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "") is
begin
for acc in 0 to 3 loop -- 3 read accesses are expected for stream context, 1 for window context
wait until rising_edge(Clk) and ((CtxStr_Cmd.Rd = '1') or (CtxWin_Cmd.Rd = '1'));
CtxStr_Resp.RdatLo <= (others => '0');
CtxStr_Resp.RdatHi <= (others => '0');
if CtxStr_Cmd.Rd = '1' then
IntCompare(Stream, CtxStr_Cmd.Stream, "ApplyContext.Str: Wrong stream number");
StdlCompare(0, CtxStr_Cmd.WenLo, "ApplyContext.Str: WenLo asserted");
StdlCompare(0, CtxStr_Cmd.WenHi, "ApplyContext.Str: WenHi asserted");
IntCompare(Stream, CtxStr_Cmd.Stream, "ApplyContext.Str: Wrong stream number - " & Msg);
StdlCompare(0, CtxStr_Cmd.WenLo, "ApplyContext.Str: WenLo asserted - " & Msg);
StdlCompare(0, CtxStr_Cmd.WenHi, "ApplyContext.Str: WenHi asserted - " & Msg);
case CtxStr_Cmd.Sel is
when CtxStr_Sel_ScfgBufstart_c => CtxStr_Resp.RdatLo(CtxStr_Sft_SCFG_RINGBUF_c) <= Ringbuf;
CtxStr_Resp.RdatLo(CtxStr_Sft_SCFG_OVERWRITE_c) <= Overwrite;
@ -217,16 +270,16 @@ package body psi_ms_daq_daq_sm_tb_pkg is
when CtxStr_Sel_WinsizePtr_c => CtxStr_Resp.RdatLo <= std_logic_vector(to_unsigned(WinSize, 32));
CtxStr_Resp.RdatHi <= std_logic_vector(to_unsigned(Ptr, 32));
when CtxStr_Sel_Winend_c => CtxStr_Resp.RdatLo <= std_logic_vector(to_unsigned(BufStart+WinSize*(Wincur+1), 32));
when others => report "###ERROR###: ApplyContext.Str: illegal CtxStr_Cmd.Sel" severity error;
when others => report "###ERROR###: ApplyContext.Str: illegal CtxStr_Cmd.Sel - " & Msg severity error;
end case;
elsif CtxWin_Cmd.Rd = '1' then
IntCompare(Stream, CtxWin_Cmd.Stream, "ApplyContext.Win: Wrong stream number");
IntCompare(Wincur, CtxWin_Cmd.Window, "ApplyContext.Win: Wrong window number");
StdlCompare(0, CtxWin_Cmd.WenLo, "ApplyContext.Win: WenLo asserted");
StdlCompare(0, CtxWin_Cmd.WenHi, "ApplyContext.Win: WenHi asserted");
IntCompare(Stream, CtxWin_Cmd.Stream, "ApplyContext.Win: Wrong stream number - " & Msg);
IntCompare(Wincur, CtxWin_Cmd.Window, "ApplyContext.Win: Wrong window number - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenLo, "ApplyContext.Win: WenLo asserted - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenHi, "ApplyContext.Win: WenHi asserted - " & Msg);
case CtxWin_Cmd.Sel is
when CtxWin_Sel_WincntWinlast_c => CtxWin_Resp.RdatLo <= std_logic_vector(to_unsigned(SamplesWin, 32));
when others => report "###ERROR###: ApplyContext.Win: illegal CtxStr_Cmd.Sel" severity error;
when others => report "###ERROR###: ApplyContext.Win: illegal CtxStr_Cmd.Sel - " & Msg severity error;
end case;
end if;
end loop;
@ -246,45 +299,46 @@ package body psi_ms_daq_daq_sm_tb_pkg is
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxWin_Cmd : in ToCtxWin_t) is
signal CtxWin_Cmd : in ToCtxWin_t;
Msg : in string := "") is
begin
wait until rising_edge(Clk) and CtxStr_Cmd.WenLo = '1';
-- Stream
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 0");
StdlvCompareStdlv(CtxStr_Sel_ScfgBufstart_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 0)");
StdlCompare(0, CtxStr_Cmd.WenHi, "ExpectContext.Str: WenHi asserted in first cycle (BufStart overwritten)");
StdlCompare(choose(Ringbuf='1',1,0), CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_RINGBUF_c), "ExpectContext.Str: Wrong RINGBUFFER");
StdlCompare(choose(Overwrite='1',1,0), CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_OVERWRITE_c), "ExpectContext.Str: Wrong OVERWRITE");
StdlvCompareInt(Wincnt, CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_WINCNT_c+7 downto CtxStr_Sft_SCFG_WINCNT_c), "ExpectContext.Str: Wrong WINCNT");
StdlvCompareInt(Wincur, CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_WINCUR_c+7 downto CtxStr_Sft_SCFG_WINCUR_c), "ExpectContext.Str: Wrong WINCUR");
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 0 - " & Msg);
StdlvCompareStdlv(CtxStr_Sel_ScfgBufstart_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 0) - " & Msg);
StdlCompare(0, CtxStr_Cmd.WenHi, "ExpectContext.Str: WenHi asserted in first cycle (BufStart overwritten) - " & Msg);
StdlCompare(choose(Ringbuf='1',1,0), CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_RINGBUF_c), "ExpectContext.Str: Wrong RINGBUFFER - " & Msg);
StdlCompare(choose(Overwrite='1',1,0), CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_OVERWRITE_c), "ExpectContext.Str: Wrong OVERWRITE - " & Msg);
StdlvCompareInt(Wincnt, CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_WINCNT_c+7 downto CtxStr_Sft_SCFG_WINCNT_c), "ExpectContext.Str: Wrong WINCNT - " & Msg);
StdlvCompareInt(Wincur, CtxStr_Cmd.WdatLo(CtxStr_Sft_SCFG_WINCUR_c+7 downto CtxStr_Sft_SCFG_WINCUR_c), "ExpectContext.Str: Wrong WINCUR - " & Msg);
-- Window
IntCompare(Stream, CtxWin_Cmd.Stream, "ExpectContext.Win: Wrong stream number 0");
StdlCompare(1, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo not asserted in first cycle");
StdlCompare(1, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi not asserted in first cycle");
StdlvCompareInt(SamplesWin, CtxWin_Cmd.WdatLo, "ExpectContext.Str: Wrong WINCNT");
StdlvCompareInt(WinLast, CtxWin_Cmd.WdatHi, "ExpectContext.Str: Wrong WINLAST");
IntCompare(Stream, CtxWin_Cmd.Stream, "ExpectContext.Win: Wrong stream number 0 - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo not asserted in first cycle - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi not asserted in first cycle - " & Msg);
StdlvCompareInt(SamplesWin, CtxWin_Cmd.WdatLo, "ExpectContext.Str: Wrong WINCNT - " & Msg);
StdlvCompareInt(WinLast, CtxWin_Cmd.WdatHi, "ExpectContext.Str: Wrong WINLAST - " & Msg);
wait until rising_edge(Clk) and CtxStr_Cmd.WenHi = '1';
-- Stream
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 1");
StdlvCompareStdlv(CtxStr_Sel_WinsizePtr_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 1)");
StdlCompare(0, CtxStr_Cmd.WenLo, "ExpectContext.Str: WenLo asserted in second cycle (WinSize overwritten)");
StdlvCompareInt(Ptr, CtxStr_Cmd.WdatHi, "ExpectContext.Str: Wrong WINCNT");
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 1 - " & Msg);
StdlvCompareStdlv(CtxStr_Sel_WinsizePtr_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 1) - " & Msg);
StdlCompare(0, CtxStr_Cmd.WenLo, "ExpectContext.Str: WenLo asserted in second cycle (WinSize overwritten) - " & Msg);
StdlvCompareInt(Ptr, CtxStr_Cmd.WdatHi, "ExpectContext.Str: Wrong WINCNT - " & Msg);
wait until rising_edge(Clk) and CtxStr_Cmd.WenLo = '1';
if WriteTs then
IntCompare(Stream, CtxWin_Cmd.Stream, "ExpectContext.Win: Wrong stream number 1");
StdlCompare(1, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo not asserted in second cycle");
StdlCompare(1, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi not asserted in second cycle");
StdlvCompareStdlv(Timstamp(31 downto 0), CtxWin_Cmd.WdatLo, "ExpectContext.Str: Wrong TS-LO");
StdlvCompareStdlv(Timstamp(63 downto 32), CtxWin_Cmd.WdatHi, "ExpectContext.Str: Wrong TS-HI");
IntCompare(Stream, CtxWin_Cmd.Stream, "ExpectContext.Win: Wrong stream number 1 - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo not asserted in second cycle - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi not asserted in second cycle - " & Msg);
StdlvCompareStdlv(Timstamp(31 downto 0), CtxWin_Cmd.WdatLo, "ExpectContext.Str: Wrong TS-LO - " & Msg);
StdlvCompareStdlv(Timstamp(63 downto 32), CtxWin_Cmd.WdatHi, "ExpectContext.Str: Wrong TS-HI - " & Msg);
else
StdlCompare(0, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo asserted in second cycle (without TS)");
StdlCompare(0, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi asserted in second cycle (without TS)");
StdlCompare(0, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo asserted in second cycle (without TS) - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi asserted in second cycle (without TS) - " & Msg);
end if;
-- Stream
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 2");
StdlvCompareStdlv(CtxStr_Sel_Winend_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 2)");
StdlCompare(0, CtxStr_Cmd.WenHi, "ExpectContext.Str: WenHi asserted in third cycle (Unused overwritten)");
StdlvCompareInt(BufStart+WinSize*(Wincur+1), CtxStr_Cmd.WdatLo, "ExpectContext.Str: Wrong WINEND");
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 2 - " & Msg);
StdlvCompareStdlv(CtxStr_Sel_Winend_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 2) - " & Msg);
StdlCompare(0, CtxStr_Cmd.WenHi, "ExpectContext.Str: WenHi asserted in third cycle (Unused overwritten) - " & Msg);
StdlvCompareInt(BufStart+WinSize*(Wincur+1), CtxStr_Cmd.WdatLo, "ExpectContext.Str: Wrong WINEND - " & Msg);
end procedure;
procedure ExpCtxUpdate( Stream : in integer;
@ -304,7 +358,8 @@ package body psi_ms_daq_daq_sm_tb_pkg is
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t) is
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "") is
variable PtrAfter_v : integer;
variable SampleswinAfter_v : integer;
variable WinLastAfter_v : integer;
@ -331,7 +386,8 @@ package body psi_ms_daq_daq_sm_tb_pkg is
CtxStr_Cmd => CtxStr_Cmd,
CtxStr_Resp => CtxStr_Resp,
CtxWin_Cmd => CtxWin_Cmd,
CtxWin_Resp => CtxWin_Resp);
CtxWin_Resp => CtxWin_Resp,
Msg => Msg);
-- Write
ExpCtxWrite(Stream => Stream,
BufStart => BufStart,
@ -347,7 +403,8 @@ package body psi_ms_daq_daq_sm_tb_pkg is
Timstamp => Timstamp,
Clk => Clk,
CtxStr_Cmd => CtxStr_Cmd,
CtxWin_Cmd => CtxWin_Cmd);
CtxWin_Cmd => CtxWin_Cmd,
Msg => Msg);
-- Output Values
PtrAfter := PtrAfter_v;
end procedure;
@ -369,7 +426,8 @@ package body psi_ms_daq_daq_sm_tb_pkg is
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t) is
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "") is
begin
-- context read
ExpCtxRead( Stream => Stream,
@ -385,7 +443,8 @@ package body psi_ms_daq_daq_sm_tb_pkg is
CtxStr_Cmd => CtxStr_Cmd,
CtxStr_Resp => CtxStr_Resp,
CtxWin_Cmd => CtxWin_Cmd,
CtxWin_Resp => CtxWin_Resp);
CtxWin_Resp => CtxWin_Resp,
Msg => Msg);
-- context update
ExpCtxUpdate( Stream => Stream,
TfSize => TfSize,
@ -404,7 +463,8 @@ package body psi_ms_daq_daq_sm_tb_pkg is
CtxStr_Cmd => CtxStr_Cmd,
CtxStr_Resp => CtxStr_Resp,
CtxWin_Cmd => CtxWin_Cmd,
CtxWin_Resp => CtxWin_Resp);
CtxWin_Resp => CtxWin_Resp,
Msg => Msg);
end procedure;
procedure ExpectDmaCmd( Stream : in integer;
@ -412,30 +472,35 @@ package body psi_ms_daq_daq_sm_tb_pkg is
MaxSize : in integer;
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Vld : in std_logic) is
signal Dma_Vld : in std_logic;
Msg : in string := "") is
begin
wait until rising_edge(Clk) and Dma_Vld = '1';
IntCompare(Stream, Dma_Cmd.Stream, "ExpectDmaCmd: Wrong stream number");
StdlvCompareInt (Address, Dma_Cmd.Address, "ExpectDmaCmd: Wrong address");
StdlvCompareInt (MaxSize, Dma_Cmd.MaxSize, "ExpectDmaCmd: Wrong MaxSize");
IntCompare(Stream, Dma_Cmd.Stream, "ExpectDmaCmd: Wrong stream number - " & Msg);
StdlvCompareInt (Address, Dma_Cmd.Address, "ExpectDmaCmd: Wrong address - " & Msg);
StdlvCompareInt (MaxSize, Dma_Cmd.MaxSize, "ExpectDmaCmd: Wrong MaxSize - " & Msg);
wait until rising_edge(Clk);
StdlCompare(0, Dma_Vld, "ExpectDmaCmd: Vld asserted for more than one cycle");
StdlCompare(0, Dma_Vld, "ExpectDmaCmd: Vld asserted for more than one cycle - " & Msg);
DmaCmdOpen := DmaCmdOpen + 1;
end procedure;
procedure ApplyDmaResp( Stream : in integer;
Size : in integer;
Trigger : in std_logic;
Delay : in time := 0 ns;
signal Clk : in std_logic;
signal Dma_Resp : out DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : out std_logic;
signal Dma_Resp_Rdy : in std_logic) is
procedure ApplyDmaResp( Stream : in integer;
Size : in integer;
Trigger : in std_logic;
Delay : in time := 0 ns;
signal Clk : in std_logic;
signal Dma_Resp : out DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : out std_logic;
signal Dma_Resp_Rdy : in std_logic;
Msg : in string := "") is
begin
while DmaCmdOpen = 0 loop
wait until rising_edge(Clk);
end loop;
end loop;
wait for Delay;
-- Update DMA pointer for next expectation (only with xxxAuto functions)
PtrDma_v(Stream) := PtrDma_v(Stream) + Size;
-- Send response
wait until rising_edge(Clk);
Dma_Resp_Vld <= '1';
Dma_Resp.Stream <= Stream;
@ -448,5 +513,88 @@ package body psi_ms_daq_daq_sm_tb_pkg is
Dma_Resp.Size <= (others => 'U');
DmaCmdOpen := DmaCmdOpen - 1;
end procedure;
procedure ExpCtxReadAuto( Stream : in integer;
WinSize : in integer := 16#00100000#;
Ringbuf : in std_logic := '0';
Overwrite : in std_logic := '0';
Wincnt : in integer := 2;
Wincur : in integer := 0;
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "") is
begin
ExpCtxRead( Stream => Stream,
BufStart => BufStart_c(Stream),
WinSize => WinSize,
Ptr => PtrStr_v(Stream),
Ringbuf => Ringbuf,
Overwrite => Overwrite,
Wincnt => Wincnt,
Wincur => Wincur,
SamplesWin => SplsStr_v(Stream),
Clk => Clk,
CtxStr_Cmd => CtxStr_Cmd,
CtxStr_Resp => CtxStr_Resp,
CtxWin_Cmd => CtxWin_Cmd,
CtxWin_Resp => CtxWin_Resp,
Msg => Msg);
end procedure;
procedure ExpCtxUpdateAuto( Stream : in integer;
TfSize : in integer; -- in bytes
WinSize : in integer := 16#00100000#;
Ringbuf : in std_logic := '0';
Overwrite : in std_logic := '0';
Wincnt : in integer := 2;
Wincur : in integer := 0;
WriteTs : in boolean := false;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : out FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : out FromCtx_t;
Msg : in string := "") is
begin
ExpCtxUpdate( Stream => Stream,
TfSize => TfSize,
BufStart => BufStart_c(Stream),
WinSize => WinSize,
PtrBefore => PtrStr_v(Stream),
Ringbuf => Ringbuf,
Overwrite => Overwrite,
Wincnt => Wincnt,
Wincur => Wincur,
SamplesWinBefore => SplsStr_v(Stream),
WriteTs => WriteTs,
Timstamp => Timstamp,
PtrAfter => PtrStr_v(Stream),
Clk => Clk,
CtxStr_Cmd => CtxStr_Cmd,
CtxStr_Resp => CtxStr_Resp,
CtxWin_Cmd => CtxWin_Cmd,
CtxWin_Resp => CtxWin_Resp,
Msg => Msg);
end procedure;
procedure ExpectDmaCmdAuto( Stream : in integer;
MaxSize : in integer;
signal Clk : in std_logic;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Vld : in std_logic;
Msg : in string := "") is
begin
ExpectDmaCmd( Stream => Stream,
Address => PtrDma_v(Stream),
MaxSize => MaxSize,
Clk => Clk,
Dma_Cmd => Dma_Cmd,
Dma_Vld => Dma_Vld,
Msg => Msg);
end procedure;
end;