AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Work on handling of unaligned transfers

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This commit is contained in:
Oliver Bruendler
2018-08-06 10:44:08 +02:00
parent f6ec0a087a
commit e0205add63
5 changed files with 123 additions and 53 deletions
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80
hdl/psi_ms_daq_daq_dma.vhd
View File

@ -87,13 +87,16 @@ architecture rtl of psi_ms_daq_daq_dma is
RspFifo_Data : DaqDma2DaqSm_Resp_t;
Mem_Data : std_logic_vector(63 downto 0);
Mem_DataVld : std_logic;
RemWrAddr : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemRdAddr : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemWen : std_logic;
StreamStdlv : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemAddr : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemWen : std_logic_vector(0 to 3);
RemWrBytes : std_logic_vector(2 downto 0);
RemSft : integer range 0 to 7;
RemData : std_logic_vector(63 downto 0);
State : State_t;
HndlMaxSize : unsigned(15 downto 0);
HndlSize : unsigned(15 downto 0);
HndlBytes : unsigned(15 downto 0);
HndlStream : integer range 0 to MaxStreams_c-1;
HndlAddress : std_logic_vector(31 downto 0);
DataLast : std_logic_vector(63 downto 0);
@ -106,7 +109,6 @@ architecture rtl of psi_ms_daq_daq_dma is
DataMuxVld : std_logic;
Mem_CmdVld : std_logic;
Trigger : std_logic;
DataRaw : std_logic_vector(63 downto 0);
end record;
signal r, r_next : two_process_r;
@ -119,7 +121,6 @@ begin
CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull, Rem_RdBytes, Rem_Data)
variable v : two_process_r;
variable ThisByte_v : std_logic_vector(7 downto 0);
variable ByteIdx_v : integer range 0 to 7;
variable MuxInVld_v : std_logic;
begin
-- *** Hold variables stable ***
@ -131,7 +132,7 @@ begin
v.Mem_DataVld := '0';
v.RspFifo_Vld := '0';
MuxInVld_v := '0';
v.RemWen := '0';
v.RemWen(0) := '0';
v.UpdateLast := '0';
-- *** State Machine ***
@ -140,11 +141,15 @@ begin
when Idle_s =>
v.HndlMaxSize := unsigned(CmdFifo_Cmd.MaxSize);
v.HndlStream := CmdFifo_Cmd.Stream;
v.StreamStdlv := std_logic_vector(to_unsigned(CmdFifo_Cmd.Stream, v.StreamStdlv'length));
v.HndlAddress := CmdFifo_Cmd.Address;
v.Trigger := '0';
if CmdFifo_Vld = '1' then
v.CmdFifo_Rdy := '1';
v.State := RemRd1_s;
-- For back to back commands on the same stream, wait until remaining bytes are written (will never occur in real-life but in TBs)
if (std_logic_vector(to_unsigned(CmdFifo_Cmd.Stream, v.StreamStdlv'length)) /= r.RemAddr) or (unsigned(r.RemWen) = 0) then
v.CmdFifo_Rdy := '1';
v.State := RemRd1_s;
end if;
end if;
when RemRd1_s =>
@ -159,10 +164,12 @@ begin
if r.FirstDma(r.HndlStream) = '1' then
v.HndlSft := (others => '0');
v.HndlSize := (others => '0');
v.HndlBytes := (others => '0');
else
v.HndlSft := to_unsigned(0, 3) - unsigned(Rem_RdBytes);
v.HndlSft := unsigned(Rem_RdBytes);
v.DataLast := Rem_Data;
v.HndlSize := resize(unsigned(Rem_RdBytes), v.HndlMaxSize'length);
v.HndlSize := (others => '0');
v.HndlBytes := resize(unsigned(Rem_RdBytes), v.HndlBytes'length);
end if;
v.FirstDma(r.HndlStream) := '0';
v.State := Start_s;
@ -175,36 +182,43 @@ begin
-- TF done because of maximum size reached
if r.HndlSize >= r.HndlMaxSize then
v.State := Done_s;
elsif Inp_Data(r.HndlStream).Last = '1' then
v.State := Done_s;
v.Trigger := Inp_Data(r.HndlStream).IsTrig;
elsif DatFifo_AlmFull = '0' then
v.HndlSize := r.HndlSize + unsigned(Inp_Data(r.HndlStream).Bytes);
v.HndlSize := r.HndlSize + 8;
v.HndlBytes := r.HndlBytes + unsigned(Inp_Data(r.HndlStream).Bytes);
-- Combinatorial handling because of fall-through interface at input
Inp_Rdy(r.HndlStream) <= '1';
MuxInVld_v := '1';
-- Handling of last frame
if Inp_Data(r.HndlStream).Last = '1' then
v.State := Done_s;
v.Trigger := Inp_Data(r.HndlStream).IsTrig;
end if;
end if;
when Done_s =>
if r.HndlMaxSize < r.HndlSize then
v.RemWrBytes := std_logic_vector(resize(r.HndlSize - r.HndlMaxSize, v.RemWrBytes'length));
v.RemWrBytes := std_logic_vector(resize(r.HndlBytes - r.HndlMaxSize, v.RemWrBytes'length));
v.HndlSize := r.HndlMaxSize;
v.RemSft := to_integer(resize(r.HndlMaxSize, 3));
else
v.RemWrBytes := (others => '0');
v.RemSft := 0;
end if;
v.State := Cmd_s;
v.Mem_CmdVld := '1';
v.RemWen(0) := '1';
v.RemAddr := r.StreamStdlv;
when Cmd_s =>
if Mem_CmdRdy = '1' then
v.State := Idle_s;
v.RemWen := '1';
v.State := Idle_s;
v.Mem_CmdVld := '0';
v.RspFifo_Vld := '1';
v.RspFifo_Data.Size := std_logic_vector(r.HndlSize);
v.RspFifo_Data.Trigger := r.Trigger;
v.RspFifo_Data.Stream := r.HndlStream;
end if;
-- do shift
when others => null;
end case;
@ -216,22 +230,21 @@ begin
v.DataMux := Inp_Data(r.HndlStream).Data;
end if;
v.DataMuxVld := MuxInVld_v;
if r.DataMuxVld = '1' then
v.DataRaw := r.DataMux;
end if;
v.RemWen(1) := r.RemWen(0);
-- *** Data Alignment ***
v.DataCurVld := r.DataMuxVld;
if r.DataMuxVld = '1' or r.State = Start_s then
for i in 0 to 7 loop
ByteIdx_v := (i+to_integer(r.HndlSft)) mod 8;
v.DataCur(8*(i+1)-1 downto 8*i) := r.DataMux(8*(ByteIdx_v+1)-1 downto 8*ByteIdx_v);
end loop;
v.RemWen(2) := r.RemWen(1);
if r.State = Start_s then
v.DataCur := r.DataMux;
elsif r.DataMuxVld = '1' then
v.DataCur(63 downto 8*to_integer(r.HndlSft)) := r.DataMux(63-8*to_integer(r.HndlSft) downto 0);
v.DataCur(8*to_integer(r.HndlSft)-1 downto 0) := r.DataMux(63 downto 64-8*to_integer(r.HndlSft));
end if;
v.Mem_DataVld := r.DataCurVld;
if (r.DataCurVld = '1') or (r.UpdateLast = '1') then
for i in 0 to 7 loop
if i < 8-r.HndlSft then
if i < r.HndlSft then
ThisByte_v := r.DataLast(8*(i+1)-1 downto 8*i);
else
ThisByte_v := r.DataCur(8*(i+1)-1 downto 8*i);
@ -241,6 +254,11 @@ begin
v.DataLast := r.DataCur;
end if;
-- *** Alignment of remiaining data for next transfer ***
v.RemWen(3) := r.RemWen(2);
v.RemData(63-8*r.RemSft downto 0) := r.DataCur(63 downto 8*r.RemSft);
v.RemData(63 downto 64-8*r.RemSft) := r.DataCur(8*r.RemSft-1 downto 0);
-- *** Assign to signal ***
r_next <= v;
@ -264,7 +282,7 @@ begin
r.CmdFifo_Rdy <= '0';
r.RspFifo_Vld <= '0';
r.Mem_DataVld <= '0';
r.RemWen <= '0';
r.RemWen <= (others => '0');
r.State <= Idle_s;
r.FirstDma <= (others => '1');
r.DataMuxVld <= '0';
@ -353,11 +371,11 @@ begin
port map (
Clk => Clk,
RdClk => Rst,
WrAddr => r.RemWrAddr,
Wr => r.RemWen,
WrAddr => r.RemAddr,
Wr => r.RemWen(3),
WrData(66 downto 64) => r.RemWrBytes,
WrData(63 downto 0) => r.DataRaw,
RdAddr => r.RemRdAddr,
WrData(63 downto 0) => r.RemData,
RdAddr => r.StreamStdlv,
RdData(66 downto 64) => Rem_RdBytes,
RdData(63 downto 0) => Rem_Data
);

1
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd
View File

@ -174,7 +174,6 @@ begin
-- Wait for two clk edges to ensure reset is active for at least one edge
wait until rising_edge(Clk);
wait until rising_edge(Clk);
Rst <= '0';
wait;
end process;

9
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd
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@ -79,22 +79,25 @@ package body psi_ms_daq_daq_dma_tb_case_aligned is
print(">> Ready always high");
InitSubCase(0);
ApplyCmd(2, 16#01230000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01230000#, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- Data Ready toggling
print(">> Data Ready toggling");
InitSubCase(1);
ApplyCmd(2, 16#01231000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01231000#, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- Cmd Ready toggling
print(">> Cmd Ready toggling");
InitSubCase(2);
ApplyCmd(2, 16#01232000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01232000#, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- Empty Timeout Frame
print(">> TODO: Empty Timeout Frame");
end procedure;
procedure input (

76
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_unaligned.vhd
View File

@ -80,38 +80,57 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
InitCase(Clk, Rst);
InitSubCase(0);
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01230000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01231000#, 29, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01231000#, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01232000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- QWord Split
wait for 10 us;
print(">> QWord Split");
InitCase(Clk, Rst);
InitSubCase(1);
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01230000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01231000#, 29, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01231000#, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01232000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- QWord Split, Rdy Toggling
wait for 10 us;
print(">> QWord Split, Rdy Toggling");
InitCase(Clk, Rst);
InitSubCase(2);
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01230000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01231000#, 29, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01231000#, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 29, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16#01232000#, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- mixed streams
wait for 10 us;
print(">> mixed streams");
InitCase(Clk, Rst);
InitSubCase(3);
ApplyCmd(2, 16#02000000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
ApplyCmd(1, 16#01000000#, 23, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(1, 23, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#02000001#, 33, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
ApplyCmd(1, 16#01000001#, 21, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 33, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(1, 21, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(1, 16#01000002#, 11, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
ApplyCmd(2, 16#02000002#, 11, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(1, 11, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
CheckResp(2, 11, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- End Aligned
@ -143,7 +162,17 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
-- QWord Split, Rdy Toggling
WaitForCase(2, Clk);
ApplyData(2, 30+29+30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ProcDone_V(0) := '1';
ProcDone_V(0) := '1';
-- mixed streams
WaitForCase(3, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ApplyData(1, 24, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 32);
ApplyData(1, 20, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 24);
ApplyData(1, 12, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 20+24);
ApplyData(2, 12, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 32+32);
ProcDone_V(0) := '1';
end procedure;
procedure mem_cmd (
@ -173,6 +202,16 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01231000#, 29, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
-- mixed streams
WaitForCase(3, Clk);
CheckMemCmd( 16#02000000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01000000#, 23, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#02000001#, 33, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01000001#, 21, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01000002#, 11, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#02000002#, 11, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
end procedure;
@ -185,9 +224,9 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
begin
-- End Unaligned
WaitForCase(0, Clk);
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
CheckMemData(29, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30);
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29);
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
CheckMemData(29, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29, "1.2");
ProcDone_V(2) := '1';
-- QWord Split
@ -202,7 +241,18 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
CheckMemData(30, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk);
CheckMemData(29, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30);
CheckMemData(30, 5, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29);
ProcDone_V(2) := '1';
-- mixed streams
WaitForCase(3, Clk);
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "2.0");
CheckMemData(23, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
CheckMemData(33, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "2.1");
CheckMemData(21, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 23, "1.1");
CheckMemData(11, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 23+21, "1.2");
CheckMemData(11, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+33, "2.2");
ProcDone_V(2) := '1';
end procedure;
end;

10
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_pkg.vhd
View File

@ -43,7 +43,6 @@ package psi_ms_daq_daq_dma_tb_pkg is
signal Clk : in std_logic);
procedure CheckResp( Stream : in integer;
Address : in integer;
Size : in integer;
EndType : in EndType_s;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -66,7 +65,8 @@ package psi_ms_daq_daq_dma_tb_pkg is
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : out std_logic;
signal Clk : in std_logic;
Offset : in integer := 0);
Offset : in integer := 0;
Msg : in string := "");
procedure CheckMemCmd( Address : in integer;
Bytes : in integer;
@ -114,7 +114,6 @@ package body psi_ms_daq_daq_dma_tb_pkg is
end procedure;
procedure CheckResp( Stream : in integer;
Address : in integer;
Size : in integer;
EndType : in EndType_s;
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
@ -175,7 +174,8 @@ package body psi_ms_daq_daq_dma_tb_pkg is
signal Mem_DatVld : in std_logic;
signal Mem_DatRdy : out std_logic;
signal Clk : in std_logic;
Offset : in integer := 0) is
Offset : in integer := 0;
Msg : in string := "") is
variable DataCnt_v : integer := Offset;
begin
for dw in 0 to (Bytes+7)/8-1 loop
@ -192,7 +192,7 @@ package body psi_ms_daq_daq_dma_tb_pkg is
if dw*8+byte >= Bytes then
-- nothing to compare
else
StdlvCompareInt (DataCnt_v, Mem_DatData(8*(byte+1)-1 downto 8*byte), "Wrong Data QW[" & to_string(dw) & "] Byte [" & to_string(byte) & "]", false);
StdlvCompareInt (DataCnt_v, Mem_DatData(8*(byte+1)-1 downto 8*byte), "Wrong Data QW[" & to_string(dw) & "] Byte [" & to_string(byte) & "] - " & Msg, false);
DataCnt_v := (DataCnt_v + 1) mod 256;
end if;
end loop;