AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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CLEANUP: Removed RemRam address latch not required anymore (no pipeline delay between state machine and RAM write)

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This commit is contained in:
Oliver Bruendler
2018-08-29 13:43:01 +02:00
parent 6ef2687cf4
commit 8001511e7d
1 changed files with 1 additions and 3 deletions
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4
hdl/psi_ms_daq_daq_dma.vhd
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@ -87,7 +87,6 @@ architecture rtl of psi_ms_daq_daq_dma is
RspFifo_Data : DaqDma2DaqSm_Resp_t;
Mem_DataVld : std_logic;
StreamStdlv : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemAddr : std_logic_vector(log2ceil(Streams_g)-1 downto 0);
RemWen : std_logic;
RemWrBytes : std_logic_vector(2 downto 0);
RemData : std_logic_vector(63 downto 0);
@ -213,7 +212,6 @@ begin
v.Mem_CmdVld := '1';
end if;
v.RemWen := '1';
v.RemAddr := r.StreamStdlv;
when Cmd_s =>
if Mem_CmdRdy = '1' or r.Mem_CmdVld = '0' then
@ -336,7 +334,7 @@ begin
port map (
Clk => Clk,
RdClk => Rst,
WrAddr => r.RemAddr,
WrAddr => r.StreamStdlv,
Wr => r.RemWen,
WrData(66 downto 64) => r.RemWrBytes,
WrData(63 downto 0) => r.RemData,