DEVEL: Implemented TMEM Interface (not yet tested)
This commit is contained in:
Oliver Bruendler
@ -1,8 +1,3 @@
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------------------------------------------------------------------------------
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-- Description
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------------------------------------------------------------------------------
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-- This component calculates a binary division of two fixed point values.
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------------------------------------------------------------------------------
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-- Libraries
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------------------------------------------------------------------------------
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@ -49,8 +44,8 @@ entity psi_ms_daq is
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Smem_Rst : in std_logic;
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-- TMEM Interface
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AcqTmem : TBD
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TmemAcq : TBD
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TmemAcq : in TmemRqst_t;
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AcqTmem : out TmemResp_t;
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-- SMEM Interface
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AcqSmem : out ToSmemWr_t;
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@ -100,6 +95,23 @@ architecture rtl of psi_ms_daq is
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-- Mem/Statemachine
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signal MemSm_Done : std_logic;
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-- Configuration
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signal Cfg_StrEna : std_logic_vector(Streams_g-1 downto 0);
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signal Cfg_GlbEna : std_logic;
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signal Cfg_PostTrig : t_aslv32(Streams_g-1 downto 0);
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signal Cfg_Arm : std_logic_vector(Streams_g-1 downto 0);
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signal Cfg_RecMode : t_aslv2(Streams_g-1 downto 0);
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-- Status
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signal Stat_StrIrq : std_logic_vector(Streams_g-1 downto 0);
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signal Stat_IsArmed : std_logic_vector(Streams_g-1 downto 0);
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-- Context Memory Connections
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signal CtxStr_Cmd : ToCtxStr_t;
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signal CtxStr_Resp : FromCtx_t;
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signal CtxWin_Cmd : ToCtxWin_t;
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signal CtxWin_Resp : FromCtx_t;
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begin
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--------------------------------------------
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@ -112,10 +124,43 @@ begin
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end if;
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end process;
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--------------------------------------------
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-- TMEM Interface
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--------------------------------------------
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i_reg : entity work.psi_ms_daq_reg_tmem
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generic map (
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Streams_g => Streams_g
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)
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port map (
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ToscaClk => Tosca_Clk,
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Rst => Rst,
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TmemRqst => TmemAcq,
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TmemResp => AcqTmem,
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CtxStr_Cmd => CtxStr_Cmd,
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CtxStr_Resp => CtxStr_Resp,
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CtxWin_Cmd => CtxWin_Cmd,
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CtxWin_Resp => CtxWin_Resp,
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StrIrq => Stat_StrIrq,
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StrEna => Cfg_StrEna,
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GlbEna => Cfg_GlbEna,
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IrqOut => Irq,
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InLevel => InpSm_Level,
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PostTrig => Cfg_PostTrig,
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Arm => Cfg_Arm,
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IsArmed => Stat_IsArmed,
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RecMode => Cfg_RecMode
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);
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--------------------------------------------
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-- Input Logic Instantiation
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--------------------------------------------
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g_input : for str in 0 to Streams_g-1 generate
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signal InRst : std_logic;
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begin
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-- Reset if stream is disabled
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InRst <= Rst or not Cfg_StrEna(str) or not Cfg_GlbEna;
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-- Instantiation
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i_input : entity work.psi_ms_daq_input
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generic map (
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StreamWidth_g => StreamWidth_g(str),
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@ -133,11 +178,11 @@ begin
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Str_Trig => Str_Trig(str),
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Str_Ts => Str_Ts(str),
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Clk => Tosca_Clk,
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Rst => Rst,
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PostTrigSpls =>
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Mode =>
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Arm =>
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IsArmed =>
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Rst => InRst,
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PostTrigSpls => Cfg_PostTrig(str),
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Mode => Cfg_RecMode(str),
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Arm => Cfg_Arm(str),
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IsArmed => Stat_IsArmed(str),
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Daq_Vld => InpDma_Vld(str),
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Daq_Rdy => InpDma_Rdy(str),
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Daq_Data => InpDma_Data(str),
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@ -165,9 +210,9 @@ begin
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port map (
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Clk => Tosca_Clk,
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Rst => Rst,
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GlbEna =>
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StrEna =>
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StrIrq =>
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GlbEna => Cfg_GlbEna,
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StrEna => Cfg_StrEna,
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StrIrq => Stat_StrIrq,
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Inp_HasLast => InpSm_HasTlast,
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Inp_Level => InpSm_Level,
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Ts_Vld => InpSm_TsVld,
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@ -181,10 +226,10 @@ begin
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TfDone => MemSm_Done,
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-- Context RAM connections
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CtxStr_Cmd : out ToCtxStr_t; -- $$ proc=ctx $$
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CtxStr_Resp : in FromCtx_t; -- $$ proc=ctx $$
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CtxWin_Cmd : out ToCtxWin_t; -- $$ proc=ctx $$
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CtxWin_Resp : in FromCtx_t -- $$ proc=ctx $$
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CtxStr_Cmd => CtxStr_Cmd,
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CtxStr_Resp => CtxStr_Resp,
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CtxWin_Cmd => CtxWin_Cmd,
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CtxWin_Resp => CtxWin_Resp
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);
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--------------------------------------------
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@ -79,12 +79,25 @@ package psi_ms_daq_pkg is
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end record;
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constant CtxWin_Sel_WincntWinlast_c : std_logic_vector(0 downto 0) := "0";
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constant CtxWin_Sel_WinTs_c : std_logic_vector(0 downto 0) := "1";
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type FromCtx_t is record
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RdatLo : std_logic_vector(31 downto 0);
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RdatHi : std_logic_vector(31 downto 0);
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end record;
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type TmemRqst_t is record
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ADD : std_logic_vector(23 downto 0);
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DATW : std_logic_vector(63 downto 0);
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ENA ; std_logic;
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WE : std_logic_vector(7 downto 0);
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CS : std_logic_vector(1 downto 0);
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end reord;
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type TmemResp_t is record
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DATR : std_logic_vector(63 downto 0);
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BUSY : std_logic;
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PIPE : std_logic_vector(1 downto 0);
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end record;
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end psi_ms_daq_pkg;
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337
hdl/psi_ms_daq_reg_tmem.vhd
Normal file
337
hdl/psi_ms_daq_reg_tmem.vhd
Normal file
@ -0,0 +1,337 @@
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------------------------------------------------------------------------------
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-- Libraries
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_fix_pkg.all;
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------------------------------------------------------------------------------
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-- Entity Declaration
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------------------------------------------------------------------------------
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entity psi_ms_daq_reg_tmem is
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generic (
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Streams_g : in integer range 1 to 32;
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MaxWindows_g : in integer range 1 to 32
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)
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port (
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-- control Ports
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ToscaClk : in std_logic;
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Rst : in std_logic;
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-- TMEM Interface
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TmemRqst : in TmemRqst_t;
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TmemResp : out TmemResp_t;
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-- Context Memory Interface
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CtxStr_Cmd : in ToCtxStr_t;
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CtxStr_Resp : out FromCtx_t;
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CtxWin_Cmd : in ToCtxWin_t;
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CtxWin_Resp : out FromCtx_t;
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-- Logic Interface
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StrIrq : in std_logic_vector(Streams_g-1 downto 0);
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StrEna : out std_logic_vector(Streams_g-1 downto 0);
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GlbEna : out std_logic;
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IrqOut : out std_logic;
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InLevel : in t_aslv16(Streams_g-1 downto 0);
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PostTrig : out t_aslv32(Streams_g-1 downto 0);
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Arm : out std_logic_vector(Streams_g-1 downto 0);
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IsArmed : in std_logic_vector(Streams_g-1 downto 0);
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RecMode : out t_aslv2(Streams_g-1 downto 0)
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);
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end entity;
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architecture rtl of psi_ms_daq_reg_tmem is
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-- Two process method
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type two_process_r is record
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Reg_Gcfg_Ena : std_logic;
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Reg_Gcfg_IrqEna : std_logic;
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Reg_IrqVec : std_logic_vector(Streams_g-1 downto 0);
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Reg_IrqEna : std_logic_vector(Streams_g-1 downto 0);
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Reg_StrEna : std_logic_vector(Streams_g-1 downto 0);
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Reg_MaxLvl : t_aslv16(Streams_g-1 downto 0);
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Reg_PostTrig : t_aslv32(Streams_g-1 downto 0);
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Reg_Mode_Recm : t_aslv2(Streams_g-1 downto 0);
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Reg_Mode_Arm : std_logic_vector(Streams_g-1 downto 0);
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Irq : std_logic;
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RegRdval : std_logic_vector(63 downto 0);
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RdVal : std_logic_vector(63 downto 0);
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AddrReg : std_logic_vector(23 downto 0);
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end record;
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signal r, r_next : two_process_r;
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constant DwWrite_c : std_logic_vector(3 downto 0) := "1111";
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subtype WeHigh_c is natural range 7 downto 4;
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subtype WeLow_c is natural range 3 downto 0;
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constant DepthCtxStr_c : integer := Streams_g*32/8;
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constant CtxStrAddrHigh_c : integer := log2ceil(Streams_g*32)-1;
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signal CtxStr_WeLo : std_logic;
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signal CtxStr_WeHi : std_logic;
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signal CtxStr_Rdval : std_logic_vector(63 downto 0);
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signal CtxStr_AddrB : std_logic_vector(log2ceil(DepthCtxStr_c-1 downto 0);
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signal AddrCtxStr : boolean;
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constant DepthCtxWin_c : integer := Streams_g*MaxWindows_g*16/8;
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constant CtxWinAddrHigh_c : integer := log2ceil(Streams_g*MaxWindows_g*16)-1;
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signal CtxWin_WeLo : std_logic;
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signal CtxWin_WeHi : std_logic;
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signal CtxWin_Rdval : std_logic_vector(63 downto 0);
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signal CtxWin_AddrB : std_logic_vector(log2ceil(DepthCtxWin_c-1 downto 0);
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signal AddrCtxWin : boolean;
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begin
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--------------------------------------------
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-- Combinatorial Process
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--------------------------------------------
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p_comb : process( r, TmemRqst, StrIrq, InLevel, IsArmed, CtxStr_Rdval, CtxWin_Rdval)
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variable v : two_process_r;
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variable Stream_v : integer range 0 to Streams_g-1;
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begin
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-- *** Hold variables stable ***
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v := r;
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-- *** Update Maximum Level
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for i in 0 to Streams_g-1 loop
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if unsigned(InLevel(i)) > unsigned(r.Reg_MaxLvl(i)) then
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v.Reg_MaxLvl(i) := InLevel(i);
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end if;
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end loop;
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-- *** General Register Accesses ***
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v.RegRdval := (others => '0');
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case TmemRqst.ADD is
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-- GCFG / GSTAT
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when X"000000" =>
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-- GCFG
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if Rqst.WE(0) = '1' then
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v.Reg_Gcfg_Ena := TmemRqst.DATW(0);
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end if;
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if Rqst.WE(1) = '1' then
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v.Reg_Gcfg_Ena := TmemRqst.DATW(8);
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end if;
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v.RegRdval(0) := r.Reg_Gcfg_Ena;
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v.RegRdval(8) := r.Reg_Gcfg_IrqEna;
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-- IRQVEC / IRQENA
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when X"000010" =>
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-- IRQVEC
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if Rqst.WE(WeLow_c) = DwWrite_c then
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v.Reg_IrqVec := r.IrqVec and (not TmemRqst.DATW(Streams_g-1 downto 0));
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end if;
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v.RegRdval(Streams_g-1 downto 0) := r.Reg_IrqVec;
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-- IRQENA
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if Rqst.WE(WeHigh_c) = DwWrite_c then
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v.Reg_IrqEna := TmemRqst.DATW(Streams_g+32-1 downto 32);
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end if;
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v.RegRdval(Streams_g+32-1 downto 32) := r.Reg_IrqEna;
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-- STRENA
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when X"000020" =>
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-- STRENA
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if Rqst.WE(WeLow_c) = DwWrite_c then
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v.Reg_StrEna := TmemRqst.DATW(Streams_g-1 downto 0);
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end if;
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v.RegRdval(Streams_g-1 downto 0) := r.Reg_StrEna;
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-- others clause
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when others => null;
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end case;
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-- *** Stream Register Accesses ***
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v.Reg_Mode_Arm <= (others => '0');
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if TmemRqst.ADD(23 downto 9) = X"000" & "001" then
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Stream_v := to_integer(unsigned(TmemRqst.ADD(8 downto 4)));
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-- MAXLVLn / POSTTRIGn
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if TmemRqst.ADD(3 downto 0) = X"0" then
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-- MAXLVLn
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if Rqst.WE(WeLow_c) = DwWrite_c then
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v.Reg_MaxLvl(Stream_v) := (others => '0');
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end if;
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v.RegRdval(15 downto 0) := r.Reg_MaxLvl(Stream_v);
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-- POSTTRIGn
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if Rqst.WE(WeHigh_c) = DwWrite_c then
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v.Reg_PostTrig(Stream_v) := TmemRqst.DATW(63 downto 32);
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end if;
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v.RegRdval(63 downto 32) := r.Reg_PostTrig(Stream_v);
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end if;
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-- MODEn
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if TmemRqst.ADD(3 downto 0) = X"8" then
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-- MODEn
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if Rqst.WE(0) = '1' then
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v.Reg_Mode_Recm(Stream_v) := TmemRqst.DATW(1 downto 0);
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end if;
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if Rqst.WE(1) = '1' then
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v.Reg_Mode_Arm(Stream_v) := TmemRqst.DATW(8);
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end if;
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v.RegRdval(1 downto 0) := r.Reg_Mode_Recm(Stream_v);
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v.RegRdval(8) := IsArmed(Stream_v);
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end if;
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end if;
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-- *** Read Data MUX ***
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v.AddrReg := TmemRqst.ADD;
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v.RdVal := (others => '0');
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if r.AddrReg(23 downto 12) = X"000" then
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v.RdVal := r.RegRdval;
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elsif r.AddrReg(23 downto 12) = X"001" then
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v.RdVal := CtxStr_Rdval;
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elsif r.AddrReg(23 downto 14) = X"00" & "01" then
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v.RdVal := CtxWin_Rdval;
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end case;
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-- *** IRQ Handling ***
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for i in 0 to Streams_g-1 loop
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if StrIrq(i) = '1' then
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v.Reg_IrqVec(i) := '1';
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end if;
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end if;
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if (r.Reg_IrqVec and r.Reg_IrqEna /= ZerosVector(Streams_g)) and (r.Reg_Gcfg_IrqEna = '1') then
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v.Irq := '1';
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else
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v.Irq := '0';
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end if;
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-- *** Assign to signal ***
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r_next <= v;
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end process;
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-- *** Registered Outputs ***
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TmemResp.PIPE <= "10";
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TmemResp.BUSY <= '0';
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TmemResp.DATR <= r.RdVal;
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IrqOut <= r.Irq;
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StrEna <= r.Reg_StrEna;
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GlbEna <= r.Reg_Gcfg_Ena;
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PostTrig <= r.Reg_PostTrig;
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Arm <= r.Reg_Mode_Arm;
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RecMode <= r.Reg_Mode_Recm;
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--------------------------------------------
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-- Sequential Process
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--------------------------------------------
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p_seq : process(ToscaClk)
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begin
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if rising_edge(ToscaClk) then
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r <= r_next;
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if Rst = '1' then
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r.Reg_Gcfg_Ena <= '0';
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r.Reg_Gcfg_IrqEna <= '0';
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r.Reg_IrqVec <= (others => '0');
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r.Reg_IrqEna <= (others => '0');
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r.Reg_StrEna <= (others => '0');
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r.Irq <= '0';
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r.Reg_MaxLvl <= (others => (others => '0'));
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r.Reg_PostTrig <= (others => (others => '0'));
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r.Reg_Mode_Recm <= (others => (others => '0'));
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r.Reg_Mode_Arm <= (others => '0');
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end if;
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end if;
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end process;
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--------------------------------------------
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-- Component Instantiations
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--------------------------------------------
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-- *** Stream Context Memory ***
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-- Signal Assembly
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AddrCtxStr <= TmemRqst.ADD(23 downto 12) = X"001";
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CtxStr_WeLo <= '1' when Rqst.WE(WeLow_c) = DwWrite_c and AddrCtxStr else '0';
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CtxStr_WeHi <= '1' when Rqst.WE(WeHigh_c) = DwWrite_c and AddrCtxStr else '0';
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CtxStr_AddrB <= std_logic_vector(to_unsigned(CtxStr_Cmd.Stream, log2ceil(Streams_g))) & CtxStr_Cmd.Sel;
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-- Low DWORD memory
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i_mem_ctx_lo : entity work.psi_common_tdp_ram_rbw
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generic map (
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Depth_g => DepthCtxStr_c,
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Width_g => 32
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)
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port map (
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ClkA => ToscaClk,
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AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 4),
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WrA => CtxStr_WeLo,
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DinA => TmemRqst.DATW(31 downto 0),
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DoutA => CtxStr_Rdval(31 downto 0),
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ClkB => ToscaClk,
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AddrB => CtxStr_AddrB,
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WrB => CtxStr_Cmd.WenLo,
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DinB => CtxStr_Cmd.WdatLo,
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DoutB => CtxStr_Resp.RdatLo
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||||
);
|
||||
|
||||
-- High DWORD memory
|
||||
i_mem_ctx_hi : entity work.psi_common_tdp_ram_rbw
|
||||
generic map (
|
||||
Depth_g => DepthCtxStr_c,
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 4),
|
||||
WrA => CtxStr_WeHi,
|
||||
DinA => TmemRqst.DATW(63 downto 32),
|
||||
DoutA => CtxStr_Rdval(63 downto 32),
|
||||
ClkB => ToscaClk,
|
||||
AddrB => CtxStr_AddrB,
|
||||
WrB => CtxStr_Cmd.WenHi,
|
||||
DinB => CtxStr_Cmd.WdatHi,
|
||||
DoutB => CtxStr_Resp.RdatHi
|
||||
);
|
||||
|
||||
-- *** Window Context Memory ***
|
||||
-- Signal Assembly
|
||||
AddrCtxWin <= TmemRqst.ADD(23 downto 14) = X"00" & "01";
|
||||
CtxWin_WeLo <= '1' when Rqst.WE(WeLow_c) = DwWrite_c and AddrCtxWin else '0';
|
||||
CtxWin_WeHi <= '1' when Rqst.WE(WeHigh_c) = DwWrite_c and AddrCtxWin else '0';
|
||||
CtxWin_AddrB <= std_logic_vector(to_unsigned(CtxWin_Cmd.Stream, log2ceil(Streams_g))) & CtxWin_Cmd.Sel;
|
||||
|
||||
-- Low DWORD memory
|
||||
i_mem_win_lo : entity work.psi_common_tdp_ram_rbw
|
||||
generic map (
|
||||
Depth_g => DepthCtxWin_c,
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 4),
|
||||
WrA => CtxWin_WeLo,
|
||||
DinA => TmemRqst.DATW(31 downto 0),
|
||||
DoutA => CtxWin_Rdval(31 downto 0),
|
||||
ClkB => ToscaClk,
|
||||
AddrB => CtxWin_AddrB,
|
||||
WrB => CtxWin_Cmd.WenLo,
|
||||
DinB => CtxWin_Cmd.WdatLo,
|
||||
DoutB => CtxWin_Resp.RdatLo
|
||||
);
|
||||
|
||||
-- High DWORD memory
|
||||
i_mem_win_hi : entity work.psi_common_tdp_ram_rbw
|
||||
generic map (
|
||||
Depth_g => DepthCtxWin_c,
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 4),
|
||||
WrA => CtxWin_WeHi,
|
||||
DinA => TmemRqst.DATW(63 downto 32),
|
||||
DoutA => CtxWin_Rdval(63 downto 32),
|
||||
ClkB => ToscaClk,
|
||||
AddrB => CtxWin_AddrB,
|
||||
WrB => CtxWin_Cmd.WenHi,
|
||||
DinB => CtxWin_Cmd.WdatHi,
|
||||
DoutB => CtxWin_Resp.RdatHi
|
||||
);
|
||||
|
||||
end architecture;
|
||||
Reference in New Issue
Block a user