AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: TB for empty timeout frame

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This commit is contained in:
Oliver Bruendler
2018-08-30 17:08:15 +02:00
parent 550d451684
commit 8eede7e216
3 changed files with 109 additions and 36 deletions
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69
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_empty_timeout.vhd
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@ -72,7 +72,34 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure CONTROL: No Content added yet!" severity warning;
InitCase(Clk, Rst);
print(">> -- Empty Timeout Frame --");
-- Without Leftover data
wait for 1 us;
print(">> Without Leftover data");
InitCase(Clk, Rst);
InitSubCase(0);
ApplyCmd(2, 16#01230000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01231000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 0, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01232000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- With Leftover data
wait for 1 us;
print(">> With Leftover data");
InitCase(Clk, Rst);
InitSubCase(1);
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01231000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 2, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
ApplyCmd(2, 16#01232000#, 32, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 32, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
end procedure;
procedure input (
@ -82,7 +109,19 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure INPUT: No Content added yet!" severity warning;
-- Without Leftover data
WaitForCase(0, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ApplyData(2, 0, Timeout_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 32);
ProcDone_V(0) := '1';
-- With Leftover data
WaitForCase(1, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ApplyData(2, 0, Timeout_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
ApplyData(2, 32, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 32);
ProcDone_V(0) := '1';
end procedure;
procedure mem_cmd (
@ -93,7 +132,18 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure MEM_CMD: No Content added yet!" severity warning;
-- Without Leftover data
WaitForCase(0, Clk);
CheckMemCmd( 16#01230000#, 32, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01232000#, 32, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
-- With Leftover data
WaitForCase(1, Clk);
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01231000#, 2, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01232000#, 32, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
end procedure;
procedure mem_dat (
@ -103,7 +153,18 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case EMPTY_TIMEOUT Procedure MEM_DAT: No Content added yet!" severity warning;
-- Without Leftover data
WaitForCase(0, Clk);
CheckMemData(32, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
CheckMemData(32, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 32, "1.2");
ProcDone_V(2) := '1';
-- With Leftover data
WaitForCase(1, Clk);
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
CheckMemData(2, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
CheckMemData(32, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 32, "1.2");
ProcDone_V(2) := '1';
end procedure;
end;

5
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_unaligned.vhd
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@ -74,10 +74,7 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
begin
InitCase(Clk, Rst);
print(">> -- Unaligned --");
print("TODO: Handle empty timeout sample");
print("TODO: Handle end of transfer because no more data");
-- End Unaligned
print(">> End Unaligned");
InitCase(Clk, Rst);

71
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_pkg.vhd
View File

@ -147,37 +147,52 @@ package body psi_ms_daq_daq_dma_tb_pkg is
begin
assert EndType = NoEnd_s or EndType = Trigger_s or EndType = Timeout_s
report "###ERROR###: APPLY_DATA: EndType not yet implemented" severity error;
Inp_Vld(Stream) <= '1';
for dw in 0 to (Bytes+7)/8-1 loop
for byte in 0 to 7 loop
if dw*8+byte >= Bytes then
Inp_Data(Stream).Data(8*(byte+1)-1 downto 8*byte) <= (others => '0');
else
Inp_Data(Stream).Data(8*(byte+1)-1 downto 8*byte) <= std_logic_vector(DataCnt_v);
DataCnt_v := DataCnt_v + 1;
end if;
end loop;
Inp_Data(Stream).Last <= '0';
Inp_Data(Stream).IsTo <= '0';
Inp_Data(Stream).IsTrig <= '0';
if dw = (Bytes+7)/8-1 then
if EndType = Trigger_s then
Inp_Data(Stream).Last <= '1';
Inp_Data(Stream).IsTrig <= '1';
elsif EndType = Timeout_s then
Inp_Data(Stream).Last <= '1';
Inp_Data(Stream).IsTo <= '1';
end if;
end if;
if Bytes-dw*8 > 8 then
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(8, 4));
-- Empty frame handling
if Bytes = 0 then
Inp_Data(Stream).Data <= X"AAAA_BBBB_CCCC_DDDD";
Inp_Data(Stream).Bytes <= "0000";
if EndType = Timeout_s then
Inp_Data(Stream).Last <= '1';
Inp_Data(Stream).IsTo <= '1';
else
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(Bytes-dw*8, 4));
report "###ERROR###: APPLY_DATA: empty frames only supported for timeout" severity error;
end if;
wait until rising_edge(Clk) and Inp_Rdy(Stream) = '1';
end loop;
Inp_Vld(Stream) <= '0';
Inp_Vld(Stream) <= '0';
-- Normal operation
else
Inp_Vld(Stream) <= '1';
for dw in 0 to (Bytes+7)/8-1 loop
for byte in 0 to 7 loop
if dw*8+byte >= Bytes then
Inp_Data(Stream).Data(8*(byte+1)-1 downto 8*byte) <= (others => '0');
else
Inp_Data(Stream).Data(8*(byte+1)-1 downto 8*byte) <= std_logic_vector(DataCnt_v);
DataCnt_v := DataCnt_v + 1;
end if;
end loop;
Inp_Data(Stream).Last <= '0';
Inp_Data(Stream).IsTo <= '0';
Inp_Data(Stream).IsTrig <= '0';
if dw = (Bytes+7)/8-1 then
if EndType = Trigger_s then
Inp_Data(Stream).Last <= '1';
Inp_Data(Stream).IsTrig <= '1';
elsif EndType = Timeout_s then
Inp_Data(Stream).Last <= '1';
Inp_Data(Stream).IsTo <= '1';
end if;
end if;
if Bytes-dw*8 > 8 then
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(8, 4));
else
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(Bytes-dw*8, 4));
end if;
wait until rising_edge(Clk) and Inp_Rdy(Stream) = '1';
end loop;
Inp_Vld(Stream) <= '0';
end if;
end procedure;
procedure CheckMemData( Bytes : in integer;