AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Implemented test for the case of empty input FIFO

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This commit is contained in:
Oliver Bruendler
2018-08-30 16:52:15 +02:00
parent 8001511e7d
commit 550d451684
1 changed files with 73 additions and 4 deletions
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77
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_input_empty.vhd
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@ -56,6 +56,8 @@ package psi_ms_daq_daq_dma_tb_case_input_empty is
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t);
shared variable SubCase : integer := 0;
end package;
------------------------------------------------------------
@ -72,7 +74,36 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
signal DaqSm_Resp_Rdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure CONTROL: No Content added yet!" severity warning;
InitCase(Clk, Rst);
print(">> -- Input Empty --");
-- Transfer aborted by input FIFO empty
wait for 1 us;
print(">> Transfer aborted by input FIFO empty");
InitCase(Clk, Rst);
InitSubCase(0);
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 16, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
SubCase := 1;
ApplyCmd(2, 16#01231000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
-- With leftover data
wait for 1 us;
print(">> With leftover data");
InitCase(Clk, Rst);
InitSubCase(1);
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
SubCase := 1;
ApplyCmd(2, 16#01231000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 18, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
SubCase := 2;
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
WaitAllProc(Clk);
end procedure;
procedure input (
@ -82,7 +113,23 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
signal Inp_Data : inout Input2Daq_Data_a;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure INPUT: No Content added yet!" severity warning;
-- Transfer aborted by input FIFO empty
WaitForCase(0, Clk);
ApplyData(2, 16, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
while SubCase < 1 loop
wait until rising_edge(Clk);
end loop;
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 16);
ProcDone_V(0) := '1';
-- With leftover data
WaitForCase(1, Clk);
ApplyData(2, 48, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
while SubCase < 2 loop
wait until rising_edge(Clk);
end loop;
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 48);
ProcDone_V(0) := '1';
end procedure;
procedure mem_cmd (
@ -93,7 +140,18 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
signal Mem_CmdRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure MEM_CMD: No Content added yet!" severity warning;
-- Transfer aborted by input FIFO empty
WaitForCase(0, Clk);
CheckMemCmd( 16#01230000#, 16, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01231000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
-- With leftover data
WaitForCase(1, Clk);
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01231000#, 18, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
ProcDone_V(1) := '1';
end procedure;
procedure mem_dat (
@ -103,7 +161,18 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
signal Mem_DatRdy : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case INPUT_EMPTY Procedure MEM_DAT: No Content added yet!" severity warning;
-- Transfer aborted by input FIFO empty
WaitForCase(0, Clk);
CheckMemData(16, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 16, "1.1");
ProcDone_V(2) := '1';
-- Transfer aborted by input FIFO empty
WaitForCase(1, Clk);
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
CheckMemData(18, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+18, "1.2");
ProcDone_V(2) := '1';
end procedure;
end;