BUGFIX: Fixed handling of TLAST remaining in DMA engine buffer
This commit is contained in:
Oliver Bruendler
@ -77,6 +77,7 @@ architecture rtl of psi_ms_daq is
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signal DmaSm_Resp : DaqDma2DaqSm_Resp_t;
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signal DmaSm_RespVld : std_logic;
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signal DmaSm_RespRdy : std_logic;
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signal DmaSm_HasLast : std_logic_vector(Streams_g-1 downto 0);
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-- Input/Dma
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signal InpDma_Vld : std_logic_vector(Streams_g-1 downto 0);
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@ -112,6 +113,9 @@ architecture rtl of psi_ms_daq is
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signal CtxWin_Cmd : ToCtxWin_t;
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signal CtxWin_Resp : FromCtx_t;
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-- Others
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signal Sm_HasLast : std_logic_vector(Streams_g-1 downto 0);
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begin
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--------------------------------------------
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@ -199,7 +203,11 @@ begin
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--------------------------------------------
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-- Control State Machine
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--------------------------------------------
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--------------------------------------------
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-- Detect end-of frame in input buffer or DMA buffer
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Sm_HasLast <= InpSm_HasTlast or DmaSm_HasLast;
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-- Instantiation
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i_statemachine : entity work.psi_ms_daq_daq_sm
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generic map (
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Streams_g => Streams_g,
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@ -215,7 +223,7 @@ begin
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GlbEna => Cfg_GlbEna,
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StrEna => Cfg_StrEna,
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StrIrq => Stat_StrIrq,
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Inp_HasLast => InpSm_HasTlast,
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Inp_HasLast => Sm_HasLast,
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Inp_Level => InpSm_Level,
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Ts_Vld => InpSm_TsVld,
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Ts_Rdy => InpSm_TsRdy,
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@ -249,6 +257,7 @@ begin
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DaqSm_Resp => DmaSm_Resp,
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DaqSm_Resp_Vld => DmaSm_RespVld,
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DaqSm_Resp_Rdy => DmaSm_RespRdy,
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DaqSm_HasLast => DmaSm_HasLast,
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Inp_Vld => InpDma_Vld,
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Inp_Rdy => InpDma_Rdy,
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Inp_Data => InpDma_Data,
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@ -19,7 +19,7 @@ library work;
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------------------------------------------------------------------------------
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-- Entity Declaration
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------------------------------------------------------------------------------
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-- $$ testcases=aligned,unaligned,odd_size,no_data_read,input_empty,timetout,empty_timeout,trigger,cmd_full,data_full $$
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-- $$ testcases=aligned,unaligned,no_data_read,input_empty,empty_timeout,cmd_full,data_full,errors $$
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-- $$ processes=control,input,mem_cmd,mem_dat $$
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-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg,work.psi_tb_activity_pkg $$
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entity psi_ms_daq_daq_dma is
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@ -37,6 +37,7 @@ entity psi_ms_daq_daq_dma is
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DaqSm_Resp : out DaqDma2DaqSm_Resp_t; -- $$ proc=control $$
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DaqSm_Resp_Vld : out std_logic; -- $$ proc=control $$
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DaqSm_Resp_Rdy : in std_logic; -- $$ proc=control $$
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DaqSm_HasLast : out std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control $$
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-- Input handling connections
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Inp_Vld : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=input $$
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@ -76,6 +77,8 @@ architecture rtl of psi_ms_daq_daq_dma is
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signal DatFifo_AlmFull : std_logic;
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signal Rem_RdBytes : std_logic_vector(2 downto 0);
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signal Rem_Data : std_logic_vector(63 downto 0);
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signal Rem_Trigger : std_logic;
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signal Rem_Last : std_logic;
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-- Types
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type State_t is (Idle_s, RemRd1_s, RemRd2_s, Transfer_s, Done_s, Cmd_s);
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@ -90,6 +93,10 @@ architecture rtl of psi_ms_daq_daq_dma is
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RemWen : std_logic;
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RemWrBytes : std_logic_vector(2 downto 0);
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RemData : std_logic_vector(63 downto 0);
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RemTrigger : std_logic;
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RemLast : std_logic;
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RemWrTrigger : std_logic;
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RemWrLast : std_logic;
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State : State_t;
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HndlMaxSize : unsigned(15 downto 0);
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RdBytes : unsigned(15 downto 0);
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@ -101,9 +108,11 @@ architecture rtl of psi_ms_daq_daq_dma is
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FirstDma : std_logic_vector(Streams_g-1 downto 0);
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Mem_CmdVld : std_logic;
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Trigger : std_logic;
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Last : std_logic;
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DataSft : std_logic_vector(127 downto 0);
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NextDone : std_logic;
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DataWritten : std_logic;
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HasLast : std_logic_vector(Streams_g-1 downto 0);
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end record;
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signal r, r_next : two_process_r;
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@ -113,7 +122,7 @@ begin
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-- Combinatorial Process
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--------------------------------------------
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p_comb : process( r, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp_Rdy, Inp_Vld, Inp_Data, Mem_CmdRdy, Mem_DatRdy,
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CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull, Rem_RdBytes, Rem_Data)
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CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull, Rem_RdBytes, Rem_Data, Rem_Trigger, Rem_Last)
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variable v : two_process_r;
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variable ThisByte_v : std_logic_vector(7 downto 0);
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variable RemSft_v : integer range 0 to 7;
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@ -138,6 +147,7 @@ begin
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v.StreamStdlv := std_logic_vector(to_unsigned(CmdFifo_Cmd.Stream, v.StreamStdlv'length));
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v.HndlAddress := CmdFifo_Cmd.Address;
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v.Trigger := '0';
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v.Last := '0';
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if CmdFifo_Vld = '1' then
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v.CmdFifo_Rdy := '1';
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v.State := RemRd1_s;
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@ -153,10 +163,14 @@ begin
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v.HndlSft := (others => '0');
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v.RdBytes := (others => '0');
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v.DataSft := (others => '0');
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v.RemTrigger := '0';
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v.RemLast := '0';
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else
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v.HndlSft := unsigned(Rem_RdBytes);
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v.DataSft(127 downto 64) := Rem_Data;
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v.RdBytes := resize(unsigned(Rem_RdBytes), v.RdBytes'length);
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v.RemTrigger := Rem_Trigger;
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v.RemLast := Rem_Last;
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end if;
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v.FirstDma(r.HndlStream) := '0';
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v.State := Transfer_s;
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@ -168,23 +182,26 @@ begin
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if r.WrBytes >= r.HndlMaxSize then
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v.State := Done_s;
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elsif DatFifo_AlmFull = '0' then
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if r.NextDone = '0' and Inp_Vld(r.HndlStream) = '1' then
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if r.NextDone = '0' and Inp_Vld(r.HndlStream) = '1' and r.RemLast = '0' then
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v.RdBytes := r.RdBytes + unsigned(Inp_Data(r.HndlStream).Bytes);
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end if;
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v.WrBytes := r.WrBytes + 8;
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-- Combinatorial handling because of fall-through interface at input
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if r.RdBytes < r.HndlMaxSize and r.NextDone = '0' then
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if r.RdBytes < r.HndlMaxSize and r.NextDone = '0' and r.RemLast = '0' then
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Inp_Rdy(r.HndlStream) <= '1';
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end if;
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-- Handling of last frame
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if Inp_Data(r.HndlStream).Last = '1' then
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if (Inp_Data(r.HndlStream).Last = '1') or (r.RemLast = '1') then
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-- Do one more word if not all data can be transferred in the current beat (NextDone = 1)
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if r.HndlSft + unsigned(Inp_Data(r.HndlStream).Bytes) <= 8 then
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if (r.HndlSft + unsigned(Inp_Data(r.HndlStream).Bytes) <= 8) or (r.RemLast = '1') then
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v.State := Done_s;
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else
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v.NextDone := '1';
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end if;
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v.Trigger := Inp_Data(r.HndlStream).IsTrig;
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if (Inp_Data(r.HndlStream).IsTrig = '1') or (r.RemTrigger = '1') then
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v.Trigger :='1';
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end if;
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v.Last := '1';
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end if;
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if r.NextDone = '1' or Inp_Vld(r.HndlStream) = '0' then
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v.State := Done_s;
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@ -200,11 +217,17 @@ begin
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when Done_s =>
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RemSft_v := to_integer(resize(r.HndlMaxSize, 3));
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v.RemWrTrigger := '0';
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v.RemWrLast := '0';
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if r.HndlMaxSize < r.RdBytes then
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v.RemWrBytes := std_logic_vector(resize(r.RdBytes - r.HndlMaxSize, v.RemWrBytes'length));
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v.RdBytes := r.HndlMaxSize;
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v.RdBytes := r.HndlMaxSize;
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v.RemWrTrigger := r.Trigger;
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v.RemWrLast := r.Last;
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v.HasLast(r.HndlStream) := r.Last;
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else
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v.RemWrBytes := (others => '0');
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v.HasLast(r.HndlStream) := '0';
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end if;
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v.RemData := v.DataSft(8*RemSft_v+63 downto 8*RemSft_v);
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v.State := Cmd_s;
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@ -219,7 +242,12 @@ begin
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v.Mem_CmdVld := '0';
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v.RspFifo_Vld := '1';
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v.RspFifo_Data.Size := std_logic_vector(r.RdBytes);
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v.RspFifo_Data.Trigger := r.Trigger;
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-- Only mark as trigger if all samples are completely written to memory (no remaining samples in REM RAM)
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if (unsigned(r.RemWrBytes) = 0) and (r.Trigger = '1') then
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v.RspFifo_Data.Trigger := '1';
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else
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v.RspFifo_Data.Trigger := '0';
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end if;
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v.RspFifo_Data.Stream := r.HndlStream;
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end if;
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when others => null;
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@ -235,6 +263,8 @@ begin
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Mem_CmdSize(r.RdBytes'range) <= std_logic_vector(r.RdBytes);
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Mem_CmdSize(Mem_CmdSize'high downto r.RdBytes'high+1) <= (others => '0');
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Mem_CmdVld <= r.Mem_CmdVld;
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DaqSm_HasLast <= r.HasLast;
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--------------------------------------------
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-- Sequential Process
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@ -251,6 +281,7 @@ begin
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r.State <= Idle_s;
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r.FirstDma <= (others => '1');
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r.Mem_CmdVld <= '0';
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r.HasLast <= (others => '0');
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end if;
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end if;
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end process;
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@ -327,7 +358,7 @@ begin
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i_remram : entity work.psi_common_sdp_ram_rbw
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generic map (
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Depth_g => Streams_g,
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Width_g => 3+64,
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Width_g => 1+1+3+64,
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IsAsync_g => false,
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RamStyle_g => "distributed"
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)
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@ -336,9 +367,13 @@ begin
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RdClk => Rst,
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WrAddr => r.StreamStdlv,
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Wr => r.RemWen,
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WrData(68) => r.RemWrLast,
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WrData(67) => r.RemWrTrigger,
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WrData(66 downto 64) => r.RemWrBytes,
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WrData(63 downto 0) => r.RemData,
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RdAddr => r.StreamStdlv,
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RdDAta(68) => Rem_Last,
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RdData(67) => Rem_Trigger,
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RdData(66 downto 64) => Rem_RdBytes,
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RdData(63 downto 0) => Rem_Data
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);
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@ -70,6 +70,7 @@ add_sources "../tb" {
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_data_full.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_cmd_full.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_errors.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd \
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psi_ms_daq/psi_ms_daq_tb_pkg.vhd \
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psi_ms_daq/psi_ms_daq_tb_str0_pkg.vhd \
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@ -32,6 +32,7 @@ library work;
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use work.psi_ms_daq_daq_dma_tb_case_empty_timeout.all;
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use work.psi_ms_daq_daq_dma_tb_case_cmd_full.all;
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use work.psi_ms_daq_daq_dma_tb_case_data_full.all;
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use work.psi_ms_daq_daq_dma_tb_case_errors.all;
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------------------------------------------------------------
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-- Entity Declaration
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@ -70,6 +71,7 @@ architecture sim of psi_ms_daq_daq_dma_tb is
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signal DaqSm_Resp : DaqDma2DaqSm_Resp_t;
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signal DaqSm_Resp_Vld : std_logic := '0';
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signal DaqSm_Resp_Rdy : std_logic := '0';
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signal DaqSm_HasLast : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
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signal Inp_Vld : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
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signal Inp_Rdy : std_logic_vector(Streams_g-1 downto 0) := (others => '0');
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signal Inp_Data : Input2Daq_Data_a(Streams_g-1 downto 0);
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@ -97,6 +99,7 @@ begin
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DaqSm_Resp => DaqSm_Resp,
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DaqSm_Resp_Vld => DaqSm_Resp_Vld,
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DaqSm_Resp_Rdy => DaqSm_Resp_Rdy,
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DaqSm_HasLast => DaqSm_HasLast,
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Inp_Vld => Inp_Vld,
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Inp_Rdy => Inp_Rdy,
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Inp_Data => Inp_Data,
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@ -135,6 +138,9 @@ begin
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-- data_full
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NextCase <= 6;
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wait until ProcessDone = AllProcessesDone_c;
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-- errors
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NextCase <= 7;
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wait until ProcessDone = AllProcessesDone_c;
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TbRunning <= false;
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wait;
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end process;
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@ -175,45 +181,51 @@ begin
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-- aligned
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wait until NextCase = 0;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_aligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_aligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- unaligned
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wait until NextCase = 1;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_unaligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_unaligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- no_data_read
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wait until NextCase = 2;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_no_data_read.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_no_data_read.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- input_empty
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wait until NextCase = 3;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_input_empty.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_input_empty.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- empty_timeout
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wait until NextCase = 4;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_empty_timeout.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_empty_timeout.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- cmd_full
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wait until NextCase = 5;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_cmd_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_cmd_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- data_full
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wait until NextCase = 6;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_data_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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work.psi_ms_daq_daq_dma_tb_case_data_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- errors
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wait until NextCase = 7;
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ProcessDone(TbProcNr_control_c) <= '0';
|
||||
work.psi_ms_daq_daq_dma_tb_case_errors.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, DaqSm_HasLast, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_control_c) <= '1';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
@ -262,6 +274,12 @@ begin
|
||||
work.psi_ms_daq_daq_dma_tb_case_data_full.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_input_c) <= '1';
|
||||
-- errors
|
||||
wait until NextCase = 7;
|
||||
ProcessDone(TbProcNr_input_c) <= '0';
|
||||
work.psi_ms_daq_daq_dma_tb_case_errors.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_input_c) <= '1';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
@ -310,6 +328,12 @@ begin
|
||||
work.psi_ms_daq_daq_dma_tb_case_data_full.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
|
||||
-- errors
|
||||
wait until NextCase = 7;
|
||||
ProcessDone(TbProcNr_mem_cmd_c) <= '0';
|
||||
work.psi_ms_daq_daq_dma_tb_case_errors.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_mem_cmd_c) <= '1';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
@ -358,6 +382,12 @@ begin
|
||||
work.psi_ms_daq_daq_dma_tb_case_data_full.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_mem_dat_c) <= '1';
|
||||
-- errors
|
||||
wait until NextCase = 7;
|
||||
ProcessDone(TbProcNr_mem_dat_c) <= '0';
|
||||
work.psi_ms_daq_daq_dma_tb_case_errors.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_mem_dat_c) <= '1';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_aligned is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -70,6 +71,7 @@ package body psi_ms_daq_daq_dma_tb_case_aligned is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_cmd_full is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -70,6 +71,7 @@ package body psi_ms_daq_daq_dma_tb_case_cmd_full is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_data_full is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -74,6 +75,7 @@ package body psi_ms_daq_daq_dma_tb_case_data_full is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_empty_timeout is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -70,6 +71,7 @@ package body psi_ms_daq_daq_dma_tb_case_empty_timeout is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
184
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_errors.vhd
Normal file
184
tb/psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_errors.vhd
Normal file
@ -0,0 +1,184 @@
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_logic_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_ms_daq_daq_dma_tb_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.psi_tb_activity_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
||||
package psi_ms_daq_daq_dma_tb_case_errors is
|
||||
|
||||
procedure control (
|
||||
signal Clk : in std_logic;
|
||||
signal Rst : inout std_logic;
|
||||
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
|
||||
signal DaqSm_Cmd_Vld : inout std_logic;
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
signal Clk : in std_logic;
|
||||
signal Inp_Vld : inout std_logic_vector;
|
||||
signal Inp_Rdy : in std_logic_vector;
|
||||
signal Inp_Data : inout Input2Daq_Data_a;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure mem_cmd (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_CmdAddr : in std_logic_vector;
|
||||
signal Mem_CmdSize : in std_logic_vector;
|
||||
signal Mem_CmdVld : in std_logic;
|
||||
signal Mem_CmdRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure mem_dat (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_DatData : in std_logic_vector;
|
||||
signal Mem_DatVld : in std_logic;
|
||||
signal Mem_DatRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_daq_dma_tb_case_errors is
|
||||
procedure control (
|
||||
signal Clk : in std_logic;
|
||||
signal Rst : inout std_logic;
|
||||
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
|
||||
signal DaqSm_Cmd_Vld : inout std_logic;
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
print(">> -- Error cases from top-tb and HW --");
|
||||
|
||||
-- Trigger in remaining data
|
||||
wait for 1 us;
|
||||
print(">> Trigger in remaining data");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(0);
|
||||
ApplyCmd(2, 16#01230000#, 26, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
StdlCompare(0, DaqSm_HasLast(2), "HasLast high unexpectedly");
|
||||
CheckResp(2, 26, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
StdlCompare(1, DaqSm_HasLast(2), "HasLast low after incomplete frame");
|
||||
ApplyCmd(2, 16#01231000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
StdlCompare(1, DaqSm_HasLast(2), "HasLast low after completion command");
|
||||
CheckResp(2, 2, Trigger_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
StdlCompare(0, DaqSm_HasLast(2), "HasLast high after completion response");
|
||||
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- Timeout in remaining data
|
||||
wait for 1 us;
|
||||
print(">> Timeout in remaining data");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(1);
|
||||
ApplyCmd(2, 16#01230000#, 26, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
StdlCompare(0, DaqSm_HasLast(2), "HasLast high unexpectedly");
|
||||
CheckResp(2, 26, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
StdlCompare(1, DaqSm_HasLast(2), "HasLast low after incomplete frame");
|
||||
ApplyCmd(2, 16#01231000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
StdlCompare(1, DaqSm_HasLast(2), "HasLast low after completion command");
|
||||
CheckResp(2, 2, Timeout_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
StdlCompare(0, DaqSm_HasLast(2), "HasLast high after completion response");
|
||||
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
end procedure;
|
||||
|
||||
procedure input (
|
||||
signal Clk : in std_logic;
|
||||
signal Inp_Vld : inout std_logic_vector;
|
||||
signal Inp_Rdy : in std_logic_vector;
|
||||
signal Inp_Data : inout Input2Daq_Data_a;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
-- Trigger in remaining data
|
||||
WaitForCase(0, Clk);
|
||||
ApplyData(2, 28, Trigger_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
|
||||
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 128);
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
-- Timeout in remaining data
|
||||
WaitForCase(1, Clk);
|
||||
ApplyData(2, 28, Timeout_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
|
||||
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 128);
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
end procedure;
|
||||
|
||||
procedure mem_cmd (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_CmdAddr : in std_logic_vector;
|
||||
signal Mem_CmdSize : in std_logic_vector;
|
||||
signal Mem_CmdVld : in std_logic;
|
||||
signal Mem_CmdRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
-- Trigger in remaining data
|
||||
WaitForCase(0, Clk);
|
||||
CheckMemCmd( 16#01230000#, 26, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01231000#, 2, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
|
||||
-- Timeout in remaining data
|
||||
WaitForCase(1, Clk);
|
||||
CheckMemCmd( 16#01230000#, 26, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01231000#, 2, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
|
||||
end procedure;
|
||||
|
||||
procedure mem_dat (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_DatData : in std_logic_vector;
|
||||
signal Mem_DatVld : in std_logic;
|
||||
signal Mem_DatRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
-- Trigger in remaining data
|
||||
WaitForCase(0, Clk);
|
||||
CheckMemData(26, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
|
||||
CheckMemData(2, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 26, "1.1");
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 128, "1.2");
|
||||
ProcDone_V(2) := '1';
|
||||
|
||||
-- Timeout in remaining data
|
||||
WaitForCase(1, Clk);
|
||||
CheckMemData(26, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
|
||||
CheckMemData(2, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 26, "1.1");
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 128, "1.2");
|
||||
ProcDone_V(2) := '1';
|
||||
|
||||
end procedure;
|
||||
|
||||
end;
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_input_empty is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -72,6 +73,7 @@ package body psi_ms_daq_daq_dma_tb_case_input_empty is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_no_data_read is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -72,6 +73,7 @@ package body psi_ms_daq_daq_dma_tb_case_no_data_read is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
@ -32,6 +32,7 @@ package psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
procedure input (
|
||||
@ -70,6 +71,7 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
signal DaqSm_HasLast : in std_logic_vector;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
InitCase(Clk, Rst);
|
||||
|
||||
Reference in New Issue
Block a user