CLEANUP: Split top-level TB into multiple files
This commit is contained in:
Oliver Bruendler
@ -71,6 +71,8 @@ add_sources "../tb" {
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_cmd_full.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd \
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psi_ms_daq/psi_ms_daq_tb_pkg.vhd \
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psi_ms_daq/psi_ms_daq_tb_str0_pkg.vhd \
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psi_ms_daq/psi_ms_daq_tb.vhd \
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} -tag tb
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@ -19,6 +19,8 @@ library work;
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use work.psi_tb_txt_util.all;
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use work.psi_tb_compare_pkg.all;
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use work.smem_master_types_pkg.all;
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use work.psi_ms_daq_tb_pkg.all;
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use work.psi_ms_daq_tb_str0_pkg.all;
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------------------------------------------------------------
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@ -38,7 +40,7 @@ architecture sim of psi_ms_daq_tb is
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-- Constants
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constant StrCount_c : integer := 4;
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constant ClkFreq_c : t_areal := (0=>250.0e6, 1=>125.0e6, 2=>80.0e6, 3=>200.0e6);
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constant MemSize_c : integer := 16#10000#;
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-- Port signals
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signal Str_Clk : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
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@ -59,191 +61,6 @@ architecture sim of psi_ms_daq_tb is
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signal AcqSmem : ToSmemWr_t;
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signal Irq : std_logic := '0';
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-- Memory
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signal Memory : t_aslv8(0 to MemSize_c-1);
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alias Memory0 : t_aslv8(0 to 16#0FFF#) is Memory(16#1000# to 16#1FFF#);
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function IntAnd( int : in integer;
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op : in integer) return integer is
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variable intu, opu : unsigned(31 downto 0);
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begin
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intu := to_unsigned(int, 32);
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opu := to_unsigned(op, 32);
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return to_integer(intu and opu);
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end function;
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-- *** TMEM Procedures ***
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procedure TmemWrite32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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begin
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wait until rising_edge(clk);
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rqst.ADD <= std_logic_vector(to_unsigned(address, 24)) and X"FFFFF8";
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rqst.ENA <= '1';
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rqst.DATW <= (others => '0');
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rqst.WE <= (others => '0');
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if address mod 8 = 0 then
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rqst.DATW(31 downto 0) <= std_logic_vector(to_unsigned(value, 32));
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rqst.WE(3 downto 0) <= (others => '1');
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else
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rqst.DATW(63 downto 32) <= std_logic_vector(to_unsigned(value, 32));
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rqst.WE(7 downto 4) <= (others => '1');
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end if;
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wait until rising_edge(clk);
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rqst.ENA <= '0';
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rqst.WE <= (others => '0');
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end procedure;
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procedure TmemRead32( address : in integer;
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value : out integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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begin
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wait until rising_edge(clk);
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rqst.ADD <= std_logic_vector(to_unsigned(address, 24)) and X"FFFFF8";
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rqst.ENA <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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if address mod 8 = 0 then
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value := to_integer(unsigned(rsp.DATR(31 downto 0)));
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else
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value := to_integer(unsigned(rsp.DATR(63 downto 32)));
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end if;
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rqst.ENA <= '0';
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end procedure;
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procedure TmemExpect32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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variable readVal : integer;
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begin
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TmemRead32(address, readVal, clk, rqst, rsp);
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IntCompare(value, readVal, "Unexpected value at address 0x" & to_hstring(to_unsigned(address, 32)));
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end procedure;
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procedure TmemWriteAndRead32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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begin
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TmemWrite32(address, value, clk, rqst, rsp);
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TmemExpect32(address, value, clk, rqst, rsp);
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end procedure;
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-- *** IRQ Handling ***
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shared variable Str0NextWin : integer := 0;
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shared variable Str0WinCheck : integer := 0;
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shared variable Str0LastTs : integer;
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procedure Str0Handler( signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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variable v : integer;
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variable curwin : integer;
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variable wincnt : integer;
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variable winstart, winend : integer;
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variable winlast : integer;
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variable addr : integer;
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variable tslo : integer;
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begin
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print("------------ Stream 0 Handler ------------");
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TmemRead32(16#0200#, v, clk, rqst, rsp);
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print("MAXLVL: " & to_string(v));
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TmemRead32(16#1000#, v, clk, rqst, rsp);
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curwin := v/(2**24);
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print("CURWIN: " & to_string(curwin));
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print("");
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while Str0NextWin /= curwin loop
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print("*** Window " & to_string(Str0NextWin) & " / Number: " & to_string(Str0WinCheck) & " ***");
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TmemRead32(16#4000#+Str0NextWin*16#10#, wincnt, clk, rqst, rsp);
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print("WINCNT: " & to_string(wincnt));
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TmemWrite32(16#4000#+Str0NextWin*16#10#, 0, clk, rqst, rsp); -- reset window counter
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TmemRead32(16#4004#+Str0NextWin*16#10#, winlast, clk, rqst, rsp);
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print("WINLAST: " & to_string(winlast));
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TmemRead32(16#4008#+Str0NextWin*16#10#, tslo, clk, rqst, rsp);
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print("WINTSLO: " & to_string(tslo));
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TmemRead32(16#400C#+Str0NextWin*16#10#, v, clk, rqst, rsp);
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print("WINTSHI: " & to_string(v));
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winstart := 16#1000# + Str0NextWin*100;
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winend := winstart + 99;
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case Str0WinCheck is
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when 0 =>
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-- Windows full because dat received for quite some time
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IntCompare(100, wincnt, "WINCNT wrong");
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-- Check Values
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addr := winlast + 1;
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for i in 256+30+3-99 to 256+30+3 loop
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StdlvCompareInt (i mod 256, Memory(addr), "Wrong value", false);
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if addr = winend then
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addr := winstart;
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else
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addr := addr + 1;
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end if;
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end loop;
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when 1 =>
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-- Trigger following each other with 30 samples difference
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IntCompare(30, wincnt, "WINCNT wrong");
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IntCompare(30*2, tslo-Str0LastTs, "TS difference wrong");
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-- Check Values
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addr := winstart;
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for i in 34 to 63 loop
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StdlvCompareInt (i, Memory(addr), "Wrong value", false);
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addr := addr + 1; -- does never wrap
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end loop;
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when 2 =>
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-- Trigger following each other with 30 samples difference
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IntCompare(30, wincnt, "WINCNT wrong");
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print(to_string(tslo) & " " & to_string(Str0LastTs));
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IntCompare(30*2, tslo-Str0LastTs, "TS difference wrong");
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-- Check Values
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addr := winstart;
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for i in 64 to 93 loop
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StdlvCompareInt (i, Memory(addr), "Wrong value", false);
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addr := addr + 1; -- does never wrap
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end loop;
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when 3 =>
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-- Full buffer recorded after emptying first buffer
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IntCompare(100, wincnt, "WINCNT wrong");
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IntCompare((256-2*30)*2, tslo-Str0LastTs, "TS difference wrong");
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-- Disable stream IRQ
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TmemRead32(16#0014#, v, clk, rqst, rsp);
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v := IntAnd(v, 16#0FE#);
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TmemWrite32(16#0014#, v, clk, rqst, rsp);
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TmemRead32(16#0020#, v, clk, rqst, rsp);
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v := IntAnd(v, 16#0FE#);
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TmemWrite32(16#0020#, v, clk, rqst, rsp);
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-- Check Values
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addr := winlast + 1;
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for i in 256+30+3-99 to 256+30+3 loop
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StdlvCompareInt (i mod 256, Memory(addr), "Wrong value", false);
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if addr = winend then
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addr := winstart;
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else
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addr := addr + 1;
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end if;
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end loop;
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when others => null;
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end case;
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print("");
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Str0LastTs := tslo;
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Str0NextWin := (Str0NextWin + 1) mod 3;
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Str0WinCheck := Str0WinCheck + 1;
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end loop;
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end procedure;
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procedure IrqHandler( signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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@ -265,11 +82,7 @@ architecture sim of psi_ms_daq_tb is
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end if;
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end loop;
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wait until rising_edge(clk);
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end procedure;
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end procedure;
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begin
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@ -449,22 +262,7 @@ begin
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begin
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wait until rising_edge(Str_Clk(0));
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while TbRunning loop
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Str_Vld(0) <= '1';
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if (now > 15 us) and (to_integer(unsigned(Str0_Data)) = 0) then
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IrqOn := true;
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end if;
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case to_integer(unsigned(Str0_Data)) is
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when 30 | 60 | 90 =>
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if IrqOn then
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Str_Trig(0) <= '1';
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end if;
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when others => null;
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end case;
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wait until rising_edge(Str_Clk(0));
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Str_Vld(0) <= '0';
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Str_Trig(0) <= '0';
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Str0_Data <= std_logic_vector(unsigned(Str0_Data)+1);
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wait until rising_edge(Str_Clk(0));
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Str0Sample(Str_Clk(0), Str_Vld(0), Str_Trig(0), Str0_Data);
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end loop;
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end process;
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150
tb/psi_ms_daq/psi_ms_daq_tb_pkg.vhd
Normal file
150
tb/psi_ms_daq/psi_ms_daq_tb_pkg.vhd
Normal file
@ -0,0 +1,150 @@
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------------------------------------------------------------
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-- Libraries
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_common_array_pkg.all;
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use work.psi_ms_daq_pkg.all;
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library work;
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use work.psi_tb_txt_util.all;
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use work.psi_tb_compare_pkg.all;
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------------------------------------------------------------
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-- Package Header
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------------------------------------------------------------
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package psi_ms_daq_tb_pkg is
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--------------------------------------------------------
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-- Global Stuff
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--------------------------------------------------------
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constant MemSize_c : integer := 16#10000#;
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signal Memory : t_aslv8(0 to MemSize_c-1);
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--------------------------------------------------------
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-- Helper Procedures
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--------------------------------------------------------
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function IntAnd( int : in integer;
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op : in integer) return integer;
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--------------------------------------------------------
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-- TMEM Procedures
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--------------------------------------------------------
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procedure TmemWrite32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t);
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procedure TmemRead32( address : in integer;
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value : out integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t);
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procedure TmemExpect32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t);
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procedure TmemWriteAndRead32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t);
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end package;
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------------------------------------------------------------
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-- Package Body
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------------------------------------------------------------
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package body psi_ms_daq_tb_pkg is
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--------------------------------------------------------
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-- Helper Procedures
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--------------------------------------------------------
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function IntAnd( int : in integer;
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op : in integer) return integer is
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variable intu, opu : unsigned(31 downto 0);
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begin
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intu := to_unsigned(int, 32);
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opu := to_unsigned(op, 32);
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return to_integer(intu and opu);
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end function;
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--------------------------------------------------------
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-- TMEM Procedures
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--------------------------------------------------------
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procedure TmemWrite32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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begin
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wait until rising_edge(clk);
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rqst.ADD <= std_logic_vector(to_unsigned(address, 24)) and X"FFFFF8";
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rqst.ENA <= '1';
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rqst.DATW <= (others => '0');
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rqst.WE <= (others => '0');
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if address mod 8 = 0 then
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rqst.DATW(31 downto 0) <= std_logic_vector(to_unsigned(value, 32));
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rqst.WE(3 downto 0) <= (others => '1');
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else
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rqst.DATW(63 downto 32) <= std_logic_vector(to_unsigned(value, 32));
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rqst.WE(7 downto 4) <= (others => '1');
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end if;
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wait until rising_edge(clk);
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rqst.ENA <= '0';
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rqst.WE <= (others => '0');
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end procedure;
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procedure TmemRead32( address : in integer;
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value : out integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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begin
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wait until rising_edge(clk);
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rqst.ADD <= std_logic_vector(to_unsigned(address, 24)) and X"FFFFF8";
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rqst.ENA <= '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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if address mod 8 = 0 then
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value := to_integer(unsigned(rsp.DATR(31 downto 0)));
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else
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value := to_integer(unsigned(rsp.DATR(63 downto 32)));
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end if;
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rqst.ENA <= '0';
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end procedure;
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procedure TmemExpect32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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variable readVal : integer;
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begin
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TmemRead32(address, readVal, clk, rqst, rsp);
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IntCompare(value, readVal, "Unexpected value at address 0x" & to_hstring(to_unsigned(address, 32)));
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end procedure;
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procedure TmemWriteAndRead32( address : in integer;
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value : in integer;
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signal clk : in std_logic;
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signal rqst : out TmemRqst_t;
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signal rsp : in TmemResp_t) is
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begin
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TmemWrite32(address, value, clk, rqst, rsp);
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TmemExpect32(address, value, clk, rqst, rsp);
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end procedure;
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end;
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197
tb/psi_ms_daq/psi_ms_daq_tb_str0_pkg.vhd
Normal file
197
tb/psi_ms_daq/psi_ms_daq_tb_str0_pkg.vhd
Normal file
@ -0,0 +1,197 @@
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------------------------------------------------------------
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-- Description
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------------------------------------------------------------
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-- Stream 0 works in ringbuffer mode (without overwrite). It
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-- produces 8-bit data (modulo counter). IRQs are located at samples
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-- containing data 30, 60 and 90. IRQs are suppressed until 15 us after
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-- simulation to see if IRQ enable works correctly.
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-- The IRQ handler also sets the window sample counter to zero to ensure
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-- more data can be recorded after the IRQ.
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------------------------------------------------------------
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-- Libraries
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||||
------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_common_array_pkg.all;
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use work.psi_ms_daq_pkg.all;
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||||
|
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library work;
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use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.psi_ms_daq_tb_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
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package psi_ms_daq_tb_str0_pkg is
|
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|
||||
-- Memory
|
||||
alias Memory0 : t_aslv8(0 to 16#0FFF#) is Memory(16#1000# to 16#1FFF#);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Persistent State
|
||||
--------------------------------------------------------
|
||||
shared variable Str0NextWin : integer := 0;
|
||||
shared variable Str0WinCheck : integer := 0;
|
||||
shared variable Str0LastTs : integer;
|
||||
shared variable Str0IrqOn : boolean := false;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str0Sample( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(7 downto 0));
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str0Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_tb_str0_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str0Sample( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(7 downto 0)) is
|
||||
begin
|
||||
vld <= '1';
|
||||
if (now > 15 us) and (to_integer(unsigned(data)) = 0) then
|
||||
Str0IrqOn := true;
|
||||
end if;
|
||||
case to_integer(unsigned(data)) is
|
||||
when 30 | 60 | 90 =>
|
||||
if Str0IrqOn then
|
||||
trig <= '1';
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
wait until rising_edge(clk);
|
||||
vld <= '0';
|
||||
trig <= '0';
|
||||
data <= std_logic_vector(unsigned(data)+1);
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str0Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
variable curwin : integer;
|
||||
variable wincnt : integer;
|
||||
variable winstart, winend : integer;
|
||||
variable winlast : integer;
|
||||
variable addr : integer;
|
||||
variable tslo : integer;
|
||||
begin
|
||||
print("------------ Stream 0 Handler ------------");
|
||||
TmemRead32(16#0200#, v, clk, rqst, rsp);
|
||||
print("MAXLVL: " & to_string(v));
|
||||
TmemRead32(16#1000#, v, clk, rqst, rsp);
|
||||
curwin := v/(2**24);
|
||||
print("CURWIN: " & to_string(curwin));
|
||||
print("");
|
||||
while Str0NextWin /= curwin loop
|
||||
print("*** Window " & to_string(Str0NextWin) & " / Number: " & to_string(Str0WinCheck) & " ***");
|
||||
TmemRead32(16#4000#+Str0NextWin*16#10#, wincnt, clk, rqst, rsp);
|
||||
print("WINCNT: " & to_string(wincnt));
|
||||
TmemWrite32(16#4000#+Str0NextWin*16#10#, 0, clk, rqst, rsp); -- reset window counter
|
||||
TmemRead32(16#4004#+Str0NextWin*16#10#, winlast, clk, rqst, rsp);
|
||||
print("WINLAST: " & to_string(winlast));
|
||||
TmemRead32(16#4008#+Str0NextWin*16#10#, tslo, clk, rqst, rsp);
|
||||
print("WINTSLO: " & to_string(tslo));
|
||||
TmemRead32(16#400C#+Str0NextWin*16#10#, v, clk, rqst, rsp);
|
||||
print("WINTSHI: " & to_string(v));
|
||||
winstart := 16#1000# + Str0NextWin*100;
|
||||
winend := winstart + 99;
|
||||
case Str0WinCheck is
|
||||
when 0 =>
|
||||
-- Windows full because dat received for quite some time
|
||||
IntCompare(100, wincnt, "WINCNT wrong");
|
||||
-- Check Values
|
||||
addr := winlast + 1;
|
||||
for i in 256+30+3-99 to 256+30+3 loop
|
||||
StdlvCompareInt (i mod 256, Memory(addr), "Wrong value", false);
|
||||
if addr = winend then
|
||||
addr := winstart;
|
||||
else
|
||||
addr := addr + 1;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
when 1 =>
|
||||
-- Trigger following each other with 30 samples difference
|
||||
IntCompare(30, wincnt, "WINCNT wrong");
|
||||
IntCompare(30*2, tslo-Str0LastTs, "TS difference wrong");
|
||||
-- Check Values
|
||||
addr := winstart;
|
||||
for i in 34 to 63 loop
|
||||
StdlvCompareInt (i, Memory(addr), "Wrong value", false);
|
||||
addr := addr + 1; -- does never wrap
|
||||
end loop;
|
||||
|
||||
when 2 =>
|
||||
-- Trigger following each other with 30 samples difference
|
||||
IntCompare(30, wincnt, "WINCNT wrong");
|
||||
print(to_string(tslo) & " " & to_string(Str0LastTs));
|
||||
IntCompare(30*2, tslo-Str0LastTs, "TS difference wrong");
|
||||
-- Check Values
|
||||
addr := winstart;
|
||||
for i in 64 to 93 loop
|
||||
StdlvCompareInt (i, Memory(addr), "Wrong value", false);
|
||||
addr := addr + 1; -- does never wrap
|
||||
end loop;
|
||||
when 3 =>
|
||||
-- Full buffer recorded after emptying first buffer
|
||||
IntCompare(100, wincnt, "WINCNT wrong");
|
||||
IntCompare((256-2*30)*2, tslo-Str0LastTs, "TS difference wrong");
|
||||
-- Disable stream IRQ
|
||||
TmemRead32(16#0014#, v, clk, rqst, rsp);
|
||||
v := IntAnd(v, 16#0FE#);
|
||||
TmemWrite32(16#0014#, v, clk, rqst, rsp);
|
||||
TmemRead32(16#0020#, v, clk, rqst, rsp);
|
||||
v := IntAnd(v, 16#0FE#);
|
||||
TmemWrite32(16#0020#, v, clk, rqst, rsp);
|
||||
-- Check Values
|
||||
addr := winlast + 1;
|
||||
for i in 256+30+3-99 to 256+30+3 loop
|
||||
StdlvCompareInt (i mod 256, Memory(addr), "Wrong value", false);
|
||||
if addr = winend then
|
||||
addr := winstart;
|
||||
else
|
||||
addr := addr + 1;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
print("");
|
||||
Str0LastTs := tslo;
|
||||
Str0NextWin := (Str0NextWin + 1) mod 3;
|
||||
Str0WinCheck := Str0WinCheck + 1;
|
||||
end loop;
|
||||
|
||||
|
||||
end procedure;
|
||||
|
||||
end;
|
||||
Reference in New Issue
Block a user