Refactoring and compliant with 3.0.0 release psi_common
This commit is contained in:
@ -33,8 +33,8 @@ Alternatively the repository [psi\_fpga\_all](https://github.com/paulscherrerins
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* TCL
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* [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) (2.1.0 or higher, for development only)
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* VHDL
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* [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (2.5.0 or higher)
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* [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (2.2.2 or higher, for development only)
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* [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (3.0.0 or higher)
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* [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (3.0.0 or higher, for development only)
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* [**psi\_multi\_stream\_daq**](https://github.com/paulscherrerinstitute/psi_multi_stream_daq)
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<!-- END OF PARSED SECTION -->
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@ -8,448 +8,439 @@
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-- Libraries
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_common_array_pkg.all;
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use work.psi_ms_daq_pkg.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_common_array_pkg.all;
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use work.psi_ms_daq_pkg.all;
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------------------------------------------------------------------------------
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-- Entity Declaration
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------------------------------------------------------------------------------
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entity psi_ms_daq_axi is
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generic (
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-- Streams
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Streams_g : positive range 1 to 32 := 2;
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StreamWidth_g : t_ainteger := (16, 16);
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StreamPrio_g : t_ainteger := (1, 1);
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StreamBuffer_g : t_ainteger := (1024, 1024);
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StreamTimeout_g : t_areal := (1.0e-3, 1.0e-3);
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StreamClkFreq_g : t_areal := (100.0e6, 100.0e6);
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StreamTsFifoDepth_g : t_ainteger := (16, 16);
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StreamUseTs_g : t_abool := (true, true);
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-- Recording
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MaxWindows_g : positive range 1 to 32 := 16;
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MinBurstSize_g : integer range 1 to 512 := 512;
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MaxBurstSize_g : integer range 1 to 512 := 512;
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-- Axi
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AxiDataWidth_g : natural range 64 to 1024 := 64;
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AxiMaxBurstBeats_g : integer range 1 to 256 := 256;
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AxiMaxOpenTrasactions_g : natural range 1 to 8 := 8;
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AxiFifoDepth_g : natural := 1024;
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-- Axi Slave
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AxiSlaveIdWidth_g : integer := 0
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);
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port (
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-- Data Stream Input
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Str_Clk : in std_logic_vector(Streams_g-1 downto 0);
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Str_Data : in t_aslv64(Streams_g-1 downto 0);
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Str_Ts : in t_aslv64(Streams_g-1 downto 0);
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Str_Vld : in std_logic_vector(Streams_g-1 downto 0);
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Str_Rdy : out std_logic_vector(Streams_g-1 downto 0);
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Str_Trig : in std_logic_vector(Streams_g-1 downto 0);
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-- Miscellaneous
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Irq : out std_logic;
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-- AXI Slave Interface for Register Access
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S_Axi_Aclk : in std_logic;
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S_Axi_Aresetn : in std_logic;
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S_Axi_ArId : in std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
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S_Axi_ArAddr : in std_logic_vector(15 downto 0);
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S_Axi_Arlen : in std_logic_vector(7 downto 0);
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S_Axi_ArSize : in std_logic_vector(2 downto 0);
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S_Axi_ArBurst : in std_logic_vector(1 downto 0);
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S_Axi_ArLock : in std_logic;
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S_Axi_ArCache : in std_logic_vector(3 downto 0);
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S_Axi_ArProt : in std_logic_vector(2 downto 0);
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S_Axi_ArValid : in std_logic;
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S_Axi_ArReady : out std_logic;
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S_Axi_RId : out std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
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S_Axi_RData : out std_logic_vector(31 downto 0);
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S_Axi_RResp : out std_logic_vector(1 downto 0);
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S_Axi_RLast : out std_logic;
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S_Axi_RValid : out std_logic;
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S_Axi_RReady : in std_logic;
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S_Axi_AwId : in std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
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S_Axi_AwAddr : in std_logic_vector(15 downto 0);
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S_Axi_AwLen : in std_logic_vector(7 downto 0);
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S_Axi_AwSize : in std_logic_vector(2 downto 0);
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S_Axi_AwBurst : in std_logic_vector(1 downto 0);
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S_Axi_AwLock : in std_logic;
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S_Axi_AwCache : in std_logic_vector(3 downto 0);
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S_Axi_AwProt : in std_logic_vector(2 downto 0);
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S_Axi_AwValid : in std_logic;
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S_Axi_AwReady : out std_logic;
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S_Axi_WData : in std_logic_vector(31 downto 0);
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S_Axi_WStrb : in std_logic_vector(3 downto 0);
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S_Axi_WLast : in std_logic;
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S_Axi_WValid : in std_logic;
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S_Axi_WReady : out std_logic;
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S_Axi_BId : out std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
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S_Axi_BResp : out std_logic_vector(1 downto 0);
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S_Axi_BValid : out std_logic;
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S_Axi_BReady : in std_logic;
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-- AXI Master Interface for Memory Access
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M_Axi_Aclk : in std_logic;
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M_Axi_Aresetn : in std_logic;
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M_Axi_AwAddr : out std_logic_vector(31 downto 0);
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M_Axi_AwLen : out std_logic_vector(7 downto 0);
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M_Axi_AwSize : out std_logic_vector(2 downto 0);
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M_Axi_AwBurst : out std_logic_vector(1 downto 0);
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M_Axi_AwLock : out std_logic;
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M_Axi_AwCache : out std_logic_vector(3 downto 0);
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M_Axi_AwProt : out std_logic_vector(2 downto 0);
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M_Axi_AwValid : out std_logic;
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M_Axi_AwReady : in std_logic := '0';
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M_Axi_WData : out std_logic_vector(AxiDataWidth_g-1 downto 0);
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M_Axi_WStrb : out std_logic_vector(AxiDataWidth_g/8-1 downto 0);
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M_Axi_WLast : out std_logic;
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M_Axi_WValid : out std_logic;
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M_Axi_WReady : in std_logic := '0';
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M_Axi_BResp : in std_logic_vector(1 downto 0) := (others => '0');
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M_Axi_BValid : in std_logic := '0';
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M_Axi_BReady : out std_logic;
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M_Axi_ArAddr : out std_logic_vector(31 downto 0);
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M_Axi_ArLen : out std_logic_vector(7 downto 0);
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M_Axi_ArSize : out std_logic_vector(2 downto 0);
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M_Axi_ArBurst : out std_logic_vector(1 downto 0);
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M_Axi_ArLock : out std_logic;
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M_Axi_ArCache : out std_logic_vector(3 downto 0);
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M_Axi_ArProt : out std_logic_vector(2 downto 0);
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M_Axi_ArValid : out std_logic;
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M_Axi_ArReady : in std_logic := '0';
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M_Axi_RData : in std_logic_vector(AxiDataWidth_g-1 downto 0) := (others => '0');
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M_Axi_RResp : in std_logic_vector(1 downto 0) := (others => '0');
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M_Axi_RLast : in std_logic := '0';
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M_Axi_RValid : in std_logic := '0';
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M_Axi_RReady : out std_logic
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);
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generic(
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-- Streams
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Streams_g : positive range 1 to 32 := 2;
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StreamWidth_g : t_ainteger := (16, 16);
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StreamPrio_g : t_ainteger := (1, 1);
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StreamBuffer_g : t_ainteger := (1024, 1024);
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StreamTimeout_g : t_areal := (1.0e-3, 1.0e-3);
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StreamClkFreq_g : t_areal := (100.0e6, 100.0e6);
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StreamTsFifoDepth_g : t_ainteger := (16, 16);
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StreamUseTs_g : t_abool := (true, true);
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-- Recording
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MaxWindows_g : positive range 1 to 32 := 16;
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MinBurstSize_g : integer range 1 to 512 := 512;
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MaxBurstSize_g : integer range 1 to 512 := 512;
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-- Axi
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AxiDataWidth_g : natural range 64 to 1024 := 64;
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AxiMaxBurstBeats_g : integer range 1 to 256 := 256;
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AxiMaxOpenTrasactions_g : natural range 1 to 8 := 8;
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AxiFifoDepth_g : natural := 1024;
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-- Axi Slave
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AxiSlaveIdWidth_g : integer := 0
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);
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port(
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-- Data Stream Input
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Str_Clk : in std_logic_vector(Streams_g - 1 downto 0);
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Str_Data : in t_aslv64(Streams_g - 1 downto 0);
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Str_Ts : in t_aslv64(Streams_g - 1 downto 0);
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Str_Vld : in std_logic_vector(Streams_g - 1 downto 0);
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Str_Rdy : out std_logic_vector(Streams_g - 1 downto 0);
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Str_Trig : in std_logic_vector(Streams_g - 1 downto 0);
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-- Miscellaneous
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Irq : out std_logic;
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-- AXI Slave Interface for Register Access
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S_Axi_Aclk : in std_logic;
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S_Axi_Aresetn : in std_logic;
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S_Axi_ArId : in std_logic_vector(AxiSlaveIdWidth_g - 1 downto 0);
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S_Axi_ArAddr : in std_logic_vector(15 downto 0);
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S_Axi_Arlen : in std_logic_vector(7 downto 0);
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S_Axi_ArSize : in std_logic_vector(2 downto 0);
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S_Axi_ArBurst : in std_logic_vector(1 downto 0);
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S_Axi_ArLock : in std_logic;
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S_Axi_ArCache : in std_logic_vector(3 downto 0);
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S_Axi_ArProt : in std_logic_vector(2 downto 0);
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S_Axi_ArValid : in std_logic;
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S_Axi_ArReady : out std_logic;
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S_Axi_RId : out std_logic_vector(AxiSlaveIdWidth_g - 1 downto 0);
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S_Axi_RData : out std_logic_vector(31 downto 0);
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S_Axi_RResp : out std_logic_vector(1 downto 0);
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S_Axi_RLast : out std_logic;
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S_Axi_RValid : out std_logic;
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S_Axi_RReady : in std_logic;
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S_Axi_AwId : in std_logic_vector(AxiSlaveIdWidth_g - 1 downto 0);
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S_Axi_AwAddr : in std_logic_vector(15 downto 0);
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S_Axi_AwLen : in std_logic_vector(7 downto 0);
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S_Axi_AwSize : in std_logic_vector(2 downto 0);
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S_Axi_AwBurst : in std_logic_vector(1 downto 0);
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S_Axi_AwLock : in std_logic;
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S_Axi_AwCache : in std_logic_vector(3 downto 0);
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S_Axi_AwProt : in std_logic_vector(2 downto 0);
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S_Axi_AwValid : in std_logic;
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S_Axi_AwReady : out std_logic;
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S_Axi_WData : in std_logic_vector(31 downto 0);
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S_Axi_WStrb : in std_logic_vector(3 downto 0);
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S_Axi_WLast : in std_logic;
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S_Axi_WValid : in std_logic;
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S_Axi_WReady : out std_logic;
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S_Axi_BId : out std_logic_vector(AxiSlaveIdWidth_g - 1 downto 0);
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S_Axi_BResp : out std_logic_vector(1 downto 0);
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S_Axi_BValid : out std_logic;
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S_Axi_BReady : in std_logic;
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-- AXI Master Interface for Memory Access
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M_Axi_Aclk : in std_logic;
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M_Axi_Aresetn : in std_logic;
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M_Axi_AwAddr : out std_logic_vector(31 downto 0);
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M_Axi_AwLen : out std_logic_vector(7 downto 0);
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M_Axi_AwSize : out std_logic_vector(2 downto 0);
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M_Axi_AwBurst : out std_logic_vector(1 downto 0);
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M_Axi_AwLock : out std_logic;
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M_Axi_AwCache : out std_logic_vector(3 downto 0);
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M_Axi_AwProt : out std_logic_vector(2 downto 0);
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M_Axi_AwValid : out std_logic;
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M_Axi_AwReady : in std_logic := '0';
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M_Axi_WData : out std_logic_vector(AxiDataWidth_g - 1 downto 0);
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M_Axi_WStrb : out std_logic_vector(AxiDataWidth_g / 8 - 1 downto 0);
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M_Axi_WLast : out std_logic;
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M_Axi_WValid : out std_logic;
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M_Axi_WReady : in std_logic := '0';
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M_Axi_BResp : in std_logic_vector(1 downto 0) := (others => '0');
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M_Axi_BValid : in std_logic := '0';
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M_Axi_BReady : out std_logic;
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M_Axi_ArAddr : out std_logic_vector(31 downto 0);
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M_Axi_ArLen : out std_logic_vector(7 downto 0);
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M_Axi_ArSize : out std_logic_vector(2 downto 0);
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M_Axi_ArBurst : out std_logic_vector(1 downto 0);
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M_Axi_ArLock : out std_logic;
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M_Axi_ArCache : out std_logic_vector(3 downto 0);
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M_Axi_ArProt : out std_logic_vector(2 downto 0);
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M_Axi_ArValid : out std_logic;
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M_Axi_ArReady : in std_logic := '0';
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M_Axi_RData : in std_logic_vector(AxiDataWidth_g - 1 downto 0) := (others => '0');
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M_Axi_RResp : in std_logic_vector(1 downto 0) := (others => '0');
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M_Axi_RLast : in std_logic := '0';
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M_Axi_RValid : in std_logic := '0';
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M_Axi_RReady : out std_logic
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);
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end entity;
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------------------------------------------------------------------------------
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-- Architecture Declaration
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------------------------------------------------------------------------------
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architecture rtl of psi_ms_daq_axi is
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-- Config Arrays with correct size
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constant StreamWidth_c : t_ainteger(0 to Streams_g-1) := StreamWidth_g(0 to Streams_g-1);
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constant StreamPrio_c : t_ainteger(0 to Streams_g-1) := StreamPrio_g(0 to Streams_g-1);
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constant StreamBuffer_c : t_ainteger(0 to Streams_g-1) := StreamBuffer_g(0 to Streams_g-1);
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constant StreamTimeout_c : t_areal(0 to Streams_g-1) := StreamTimeout_g(0 to Streams_g-1);
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constant StreamClkFreq_c : t_areal(0 to Streams_g-1) := StreamClkFreq_g(0 to Streams_g-1);
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constant StreamTsFifoDepth_c : t_ainteger(0 to Streams_g-1) := StreamTsFifoDepth_g(0 to Streams_g-1);
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constant StreamUseTs_c : t_abool(0 to Streams_g-1) := StreamUseTs_g(0 to Streams_g-1);
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-- Config Arrays with correct size
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constant StreamWidth_c : t_ainteger(0 to Streams_g - 1) := StreamWidth_g(0 to Streams_g - 1);
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constant StreamPrio_c : t_ainteger(0 to Streams_g - 1) := StreamPrio_g(0 to Streams_g - 1);
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constant StreamBuffer_c : t_ainteger(0 to Streams_g - 1) := StreamBuffer_g(0 to Streams_g - 1);
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constant StreamTimeout_c : t_areal(0 to Streams_g - 1) := StreamTimeout_g(0 to Streams_g - 1);
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constant StreamClkFreq_c : t_areal(0 to Streams_g - 1) := StreamClkFreq_g(0 to Streams_g - 1);
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constant StreamTsFifoDepth_c : t_ainteger(0 to Streams_g - 1) := StreamTsFifoDepth_g(0 to Streams_g - 1);
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constant StreamUseTs_c : t_abool(0 to Streams_g - 1) := StreamUseTs_g(0 to Streams_g - 1);
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-- Input/Statemachine Signals
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signal InpSm_HasTlast : std_logic_vector(Streams_g - 1 downto 0);
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signal InpSm_TsVld : std_logic_vector(Streams_g - 1 downto 0);
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signal InpSm_TsRdy : std_logic_vector(Streams_g - 1 downto 0);
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signal InpSm_Level : t_aslv16(Streams_g - 1 downto 0);
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signal InpSm_TsData : t_aslv64(Streams_g - 1 downto 0);
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-- Statemachine/Dma
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signal SmDma_Cmd : DaqSm2DaqDma_Cmd_t;
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signal SmDma_CmdVld : std_logic;
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signal DmaSm_Resp : DaqDma2DaqSm_Resp_t;
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signal DmaSm_RespVld : std_logic;
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signal DmaSm_RespRdy : std_logic;
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signal DmaSm_HasLast : std_logic_vector(Streams_g - 1 downto 0);
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-- Input/Dma
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signal InpDma_Vld : std_logic_vector(Streams_g - 1 downto 0);
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signal InpDma_Rdy : std_logic_vector(Streams_g - 1 downto 0);
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signal InpDma_Data : Input2Daq_Data_a(Streams_g - 1 downto 0);
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-- Dma/Mem
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signal DmaMem_CmdAddr : std_logic_vector(31 downto 0);
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signal DmaMem_CmdSize : std_logic_vector(31 downto 0);
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signal DmaMem_CmdVld : std_logic;
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signal DmaMem_CmdRdy : std_logic;
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signal DmaMem_DatData : std_logic_vector(63 downto 0);
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signal DmaMem_DatVld : std_logic;
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signal DmaMem_DatRdy : std_logic;
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-- Mem/Statemachine
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signal MemSm_Done : std_logic;
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-- Configuration
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signal Cfg_StrEna : std_logic_vector(Streams_g - 1 downto 0);
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signal Cfg_GlbEna : std_logic;
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signal Cfg_PostTrig : t_aslv32(Streams_g - 1 downto 0);
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signal Cfg_Arm : std_logic_vector(Streams_g - 1 downto 0);
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signal Cfg_RecMode : t_aslv2(Streams_g - 1 downto 0);
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-- Status
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signal Stat_StrIrq : std_logic_vector(Streams_g - 1 downto 0);
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signal Stat_StrLastWin : WinType_a(Streams_g - 1 downto 0);
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signal Stat_IsArmed : std_logic_vector(Streams_g - 1 downto 0);
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signal Stat_IsRecording : std_logic_vector(Streams_g - 1 downto 0);
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-- Context Memory Connections
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signal CtxStr_Cmd : ToCtxStr_t;
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signal CtxStr_Resp : FromCtx_t;
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signal CtxWin_Cmd : ToCtxWin_t;
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signal CtxWin_Resp : FromCtx_t;
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-- Others
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signal Sm_HasLast : std_logic_vector(Streams_g - 1 downto 0);
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signal M_Axi_Areset : std_logic; -- high active reset
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signal S_Axi_Areset : std_logic; -- high active reset
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||||
-- Input/Statemachine Signals
|
||||
signal InpSm_HasTlast : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpSm_TsVld : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpSm_TsRdy : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpSm_Level : t_aslv16(Streams_g-1 downto 0);
|
||||
signal InpSm_TsData : t_aslv64(Streams_g-1 downto 0);
|
||||
|
||||
-- Statemachine/Dma
|
||||
signal SmDma_Cmd : DaqSm2DaqDma_Cmd_t;
|
||||
signal SmDma_CmdVld : std_logic;
|
||||
signal DmaSm_Resp : DaqDma2DaqSm_Resp_t;
|
||||
signal DmaSm_RespVld : std_logic;
|
||||
signal DmaSm_RespRdy : std_logic;
|
||||
signal DmaSm_HasLast : std_logic_vector(Streams_g-1 downto 0);
|
||||
|
||||
-- Input/Dma
|
||||
signal InpDma_Vld : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpDma_Rdy : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpDma_Data : Input2Daq_Data_a(Streams_g-1 downto 0);
|
||||
|
||||
-- Dma/Mem
|
||||
signal DmaMem_CmdAddr : std_logic_vector(31 downto 0);
|
||||
signal DmaMem_CmdSize : std_logic_vector(31 downto 0);
|
||||
signal DmaMem_CmdVld : std_logic;
|
||||
signal DmaMem_CmdRdy : std_logic;
|
||||
signal DmaMem_DatData : std_logic_vector(63 downto 0);
|
||||
signal DmaMem_DatVld : std_logic;
|
||||
signal DmaMem_DatRdy : std_logic;
|
||||
|
||||
-- Mem/Statemachine
|
||||
signal MemSm_Done : std_logic;
|
||||
|
||||
-- Configuration
|
||||
signal Cfg_StrEna : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Cfg_GlbEna : std_logic;
|
||||
signal Cfg_PostTrig : t_aslv32(Streams_g-1 downto 0);
|
||||
signal Cfg_Arm : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Cfg_RecMode : t_aslv2(Streams_g-1 downto 0);
|
||||
|
||||
-- Status
|
||||
signal Stat_StrIrq : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Stat_StrLastWin : WinType_a(Streams_g-1 downto 0);
|
||||
signal Stat_IsArmed : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Stat_IsRecording : std_logic_vector(Streams_g-1 downto 0);
|
||||
|
||||
-- Context Memory Connections
|
||||
signal CtxStr_Cmd : ToCtxStr_t;
|
||||
signal CtxStr_Resp : FromCtx_t;
|
||||
signal CtxWin_Cmd : ToCtxWin_t;
|
||||
signal CtxWin_Resp : FromCtx_t;
|
||||
|
||||
-- Others
|
||||
signal Sm_HasLast : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal M_Axi_Areset : std_logic; -- high active reset
|
||||
signal S_Axi_Areset : std_logic; -- high active reset
|
||||
|
||||
begin
|
||||
|
||||
M_Axi_Areset <= not M_Axi_Aresetn;
|
||||
S_Axi_Areset <= not S_Axi_Aresetn;
|
||||
|
||||
--------------------------------------------
|
||||
-- Register Interface
|
||||
--------------------------------------------
|
||||
i_reg : entity work.psi_ms_daq_reg_axi
|
||||
generic map (
|
||||
Streams_g => Streams_g,
|
||||
MaxWindows_g => MaxWindows_g,
|
||||
AxiSlaveIdWidth_g => AxiSlaveIdWidth_g
|
||||
)
|
||||
port map (
|
||||
S_Axi_Aclk => S_Axi_Aclk,
|
||||
S_Axi_Aresetn => S_Axi_Aresetn,
|
||||
S_Axi_ArId => S_Axi_ArId,
|
||||
S_Axi_ArAddr => S_Axi_ArAddr,
|
||||
S_Axi_Arlen => S_Axi_Arlen,
|
||||
S_Axi_ArSize => S_Axi_ArSize,
|
||||
S_Axi_ArBurst => S_Axi_ArBurst,
|
||||
S_Axi_ArLock => S_Axi_ArLock,
|
||||
S_Axi_ArCache => S_Axi_ArCache,
|
||||
S_Axi_ArProt => S_Axi_ArProt,
|
||||
S_Axi_ArValid => S_Axi_ArValid,
|
||||
S_Axi_ArReady => S_Axi_ArReady,
|
||||
S_Axi_RId => S_Axi_RId,
|
||||
S_Axi_RData => S_Axi_RData,
|
||||
S_Axi_RResp => S_Axi_RResp,
|
||||
S_Axi_RLast => S_Axi_RLast,
|
||||
S_Axi_RValid => S_Axi_RValid,
|
||||
S_Axi_RReady => S_Axi_RReady,
|
||||
S_Axi_AwId => S_Axi_AwId,
|
||||
S_Axi_AwAddr => S_Axi_AwAddr,
|
||||
S_Axi_AwLen => S_Axi_AwLen,
|
||||
S_Axi_AwSize => S_Axi_AwSize,
|
||||
S_Axi_AwBurst => S_Axi_AwBurst,
|
||||
S_Axi_AwLock => S_Axi_AwLock,
|
||||
S_Axi_AwCache => S_Axi_AwCache,
|
||||
S_Axi_AwProt => S_Axi_AwProt,
|
||||
S_Axi_AwValid => S_Axi_AwValid,
|
||||
S_Axi_AwReady => S_Axi_AwReady,
|
||||
S_Axi_WData => S_Axi_WData,
|
||||
S_Axi_WStrb => S_Axi_WStrb,
|
||||
S_Axi_WLast => S_Axi_WLast,
|
||||
S_Axi_WValid => S_Axi_WValid,
|
||||
S_Axi_WReady => S_Axi_WReady,
|
||||
S_Axi_BId => S_Axi_BId,
|
||||
S_Axi_BResp => S_Axi_BResp,
|
||||
S_Axi_BValid => S_Axi_BValid,
|
||||
S_Axi_BReady => S_Axi_BReady,
|
||||
IrqOut => Irq,
|
||||
PostTrig => Cfg_PostTrig,
|
||||
Arm => Cfg_Arm,
|
||||
IsArmed => Stat_IsArmed,
|
||||
IsRecording => Stat_IsRecording,
|
||||
RecMode => Cfg_RecMode,
|
||||
ClkMem => M_Axi_Aclk,
|
||||
RstMem => M_Axi_Areset,
|
||||
CtxStr_Cmd => CtxStr_Cmd,
|
||||
CtxStr_Resp => CtxStr_Resp,
|
||||
CtxWin_Cmd => CtxWin_Cmd,
|
||||
CtxWin_Resp => CtxWin_Resp,
|
||||
InLevel => InpSm_Level,
|
||||
StrIrq => Stat_StrIrq,
|
||||
StrLastWin => Stat_StrLastWin,
|
||||
StrEna => Cfg_StrEna,
|
||||
GlbEna => Cfg_GlbEna
|
||||
);
|
||||
M_Axi_Areset <= not M_Axi_Aresetn;
|
||||
S_Axi_Areset <= not S_Axi_Aresetn;
|
||||
|
||||
--------------------------------------------
|
||||
-- Input Logic Instantiation
|
||||
--------------------------------------------
|
||||
g_input : for str in 0 to Streams_g-1 generate
|
||||
signal InRst : std_logic;
|
||||
signal StrInput : std_logic_vector(StreamWidth_c(str)-1 downto 0);
|
||||
begin
|
||||
-- Reset if stream is disabled
|
||||
InRst <= M_Axi_Areset or not Cfg_StrEna(str) or not Cfg_GlbEna;
|
||||
StrInput <= Str_Data(str)(StrInput'range);
|
||||
|
||||
-- Instantiation
|
||||
i_input : entity work.psi_ms_daq_input
|
||||
generic map (
|
||||
StreamWidth_g => StreamWidth_c(str),
|
||||
StreamBuffer_g => StreamBuffer_c(str),
|
||||
StreamTimeout_g => StreamTimeout_c(str),
|
||||
StreamClkFreq_g => StreamClkFreq_c(str),
|
||||
StreamTsFifoDepth_g => StreamTsFifoDepth_c(str),
|
||||
StreamUseTs_g => StreamUseTs_c(str)
|
||||
)
|
||||
port map (
|
||||
Str_Clk => Str_Clk(str),
|
||||
Str_Vld => Str_Vld(str),
|
||||
Str_Rdy => Str_Rdy(str),
|
||||
Str_Data => StrInput,
|
||||
Str_Trig => Str_Trig(str),
|
||||
Str_Ts => Str_Ts(str),
|
||||
ClkReg => S_Axi_Aclk,
|
||||
RstReg => S_Axi_Areset,
|
||||
PostTrigSpls => Cfg_PostTrig(str),
|
||||
Mode => Cfg_RecMode(str),
|
||||
Arm => Cfg_Arm(str),
|
||||
IsArmed => Stat_IsArmed(str),
|
||||
IsRecording => Stat_IsRecording(str),
|
||||
ClkMem => M_Axi_Aclk,
|
||||
RstMem => InRst,
|
||||
Daq_Vld => InpDma_Vld(str),
|
||||
Daq_Rdy => InpDma_Rdy(str),
|
||||
Daq_Data => InpDma_Data(str),
|
||||
Daq_Level => InpSm_Level(str),
|
||||
Daq_HasLast => InpSm_HasTlast(str),
|
||||
Ts_Vld => InpSm_TsVld(str),
|
||||
Ts_Rdy => InpSm_TsRdy(str),
|
||||
Ts_Data => InpSm_TsData(str)
|
||||
);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------
|
||||
-- Control State Machine
|
||||
--------------------------------------------
|
||||
-- Detect end-of frame in input buffer or DMA buffer
|
||||
Sm_HasLast <= InpSm_HasTlast or DmaSm_HasLast;
|
||||
|
||||
-- Instantiation
|
||||
i_statemachine : entity work.psi_ms_daq_daq_sm
|
||||
generic map (
|
||||
Streams_g => Streams_g,
|
||||
StreamPrio_g => StreamPrio_c,
|
||||
StreamWidth_g => StreamWidth_c,
|
||||
Windows_g => MaxWindows_g,
|
||||
MinBurstSize_g => MinBurstSize_g,
|
||||
MaxBurstSize_g => MaxBurstSize_g
|
||||
)
|
||||
port map (
|
||||
Clk => M_Axi_Aclk,
|
||||
Rst => M_Axi_Areset,
|
||||
GlbEna => Cfg_GlbEna,
|
||||
StrEna => Cfg_StrEna,
|
||||
StrIrq => Stat_StrIrq,
|
||||
StrLastWin => Stat_StrLastWin,
|
||||
Inp_HasLast => Sm_HasLast,
|
||||
Inp_Level => InpSm_Level,
|
||||
Ts_Vld => InpSm_TsVld,
|
||||
Ts_Rdy => InpSm_TsRdy,
|
||||
Ts_Data => InpSm_TsData,
|
||||
Dma_Cmd => SmDma_Cmd,
|
||||
Dma_Cmd_Vld => SmDma_CmdVld,
|
||||
Dma_Resp => DmaSm_Resp,
|
||||
Dma_Resp_Vld => DmaSm_RespVld,
|
||||
Dma_Resp_Rdy => DmaSm_RespRdy,
|
||||
TfDone => MemSm_Done,
|
||||
|
||||
-- Context RAM connections
|
||||
CtxStr_Cmd => CtxStr_Cmd,
|
||||
CtxStr_Resp => CtxStr_Resp,
|
||||
CtxWin_Cmd => CtxWin_Cmd,
|
||||
CtxWin_Resp => CtxWin_Resp
|
||||
);
|
||||
--------------------------------------------
|
||||
-- Register Interface
|
||||
--------------------------------------------
|
||||
i_reg : entity work.psi_ms_daq_reg_axi
|
||||
generic map(
|
||||
Streams_g => Streams_g,
|
||||
MaxWindows_g => MaxWindows_g,
|
||||
AxiSlaveIdWidth_g => AxiSlaveIdWidth_g
|
||||
)
|
||||
port map(
|
||||
S_Axi_Aclk => S_Axi_Aclk,
|
||||
S_Axi_Aresetn => S_Axi_Aresetn,
|
||||
S_Axi_ArId => S_Axi_ArId,
|
||||
S_Axi_ArAddr => S_Axi_ArAddr,
|
||||
S_Axi_Arlen => S_Axi_Arlen,
|
||||
S_Axi_ArSize => S_Axi_ArSize,
|
||||
S_Axi_ArBurst => S_Axi_ArBurst,
|
||||
S_Axi_ArLock => S_Axi_ArLock,
|
||||
S_Axi_ArCache => S_Axi_ArCache,
|
||||
S_Axi_ArProt => S_Axi_ArProt,
|
||||
S_Axi_ArValid => S_Axi_ArValid,
|
||||
S_Axi_ArReady => S_Axi_ArReady,
|
||||
S_Axi_RId => S_Axi_RId,
|
||||
S_Axi_RData => S_Axi_RData,
|
||||
S_Axi_RResp => S_Axi_RResp,
|
||||
S_Axi_RLast => S_Axi_RLast,
|
||||
S_Axi_RValid => S_Axi_RValid,
|
||||
S_Axi_RReady => S_Axi_RReady,
|
||||
S_Axi_AwId => S_Axi_AwId,
|
||||
S_Axi_AwAddr => S_Axi_AwAddr,
|
||||
S_Axi_AwLen => S_Axi_AwLen,
|
||||
S_Axi_AwSize => S_Axi_AwSize,
|
||||
S_Axi_AwBurst => S_Axi_AwBurst,
|
||||
S_Axi_AwLock => S_Axi_AwLock,
|
||||
S_Axi_AwCache => S_Axi_AwCache,
|
||||
S_Axi_AwProt => S_Axi_AwProt,
|
||||
S_Axi_AwValid => S_Axi_AwValid,
|
||||
S_Axi_AwReady => S_Axi_AwReady,
|
||||
S_Axi_WData => S_Axi_WData,
|
||||
S_Axi_WStrb => S_Axi_WStrb,
|
||||
S_Axi_WLast => S_Axi_WLast,
|
||||
S_Axi_WValid => S_Axi_WValid,
|
||||
S_Axi_WReady => S_Axi_WReady,
|
||||
S_Axi_BId => S_Axi_BId,
|
||||
S_Axi_BResp => S_Axi_BResp,
|
||||
S_Axi_BValid => S_Axi_BValid,
|
||||
S_Axi_BReady => S_Axi_BReady,
|
||||
IrqOut => Irq,
|
||||
PostTrig => Cfg_PostTrig,
|
||||
Arm => Cfg_Arm,
|
||||
IsArmed => Stat_IsArmed,
|
||||
IsRecording => Stat_IsRecording,
|
||||
RecMode => Cfg_RecMode,
|
||||
ClkMem => M_Axi_Aclk,
|
||||
RstMem => M_Axi_Areset,
|
||||
CtxStr_Cmd => CtxStr_Cmd,
|
||||
CtxStr_Resp => CtxStr_Resp,
|
||||
CtxWin_Cmd => CtxWin_Cmd,
|
||||
CtxWin_Resp => CtxWin_Resp,
|
||||
InLevel => InpSm_Level,
|
||||
StrIrq => Stat_StrIrq,
|
||||
StrLastWin => Stat_StrLastWin,
|
||||
StrEna => Cfg_StrEna,
|
||||
GlbEna => Cfg_GlbEna
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- DMA Engine
|
||||
--------------------------------------------
|
||||
i_dma : entity work.psi_ms_daq_daq_dma
|
||||
generic map (
|
||||
Streams_g => Streams_g
|
||||
)
|
||||
port map (
|
||||
Clk => M_Axi_Aclk,
|
||||
Rst => M_Axi_Areset,
|
||||
DaqSm_Cmd => SmDma_Cmd,
|
||||
DaqSm_Cmd_Vld => SmDma_CmdVld,
|
||||
DaqSm_Resp => DmaSm_Resp,
|
||||
DaqSm_Resp_Vld => DmaSm_RespVld,
|
||||
DaqSm_Resp_Rdy => DmaSm_RespRdy,
|
||||
DaqSm_HasLast => DmaSm_HasLast,
|
||||
Inp_Vld => InpDma_Vld,
|
||||
Inp_Rdy => InpDma_Rdy,
|
||||
Inp_Data => InpDma_Data,
|
||||
Mem_CmdAddr => DmaMem_CmdAddr,
|
||||
Mem_CmdSize => DmaMem_CmdSize,
|
||||
Mem_CmdVld => DmaMem_CmdVld,
|
||||
Mem_CmdRdy => DmaMem_CmdRdy,
|
||||
Mem_DatData => DmaMem_DatData,
|
||||
Mem_DatVld => DmaMem_DatVld,
|
||||
Mem_DatRdy => DmaMem_DatRdy
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- Memory Interface
|
||||
--------------------------------------------
|
||||
i_memif : entity work.psi_ms_daq_axi_if
|
||||
generic map (
|
||||
AxiDataWidth_g => AxiDataWidth_g,
|
||||
AxiMaxBeats_g => AxiMaxBurstBeats_g,
|
||||
AxiMaxOpenTrasactions_g => AxiMaxOpenTrasactions_g,
|
||||
MaxOpenCommands_g => max(2, Streams_g), -- ISE tools implement memory as FFs for one stream. Reason is unkown, so we always implement two streams for resource optimization reasons.
|
||||
DataFifoDepth_g => 1024,
|
||||
AxiFifoDepth_g => AxiFifoDepth_g,
|
||||
RamBehavior_g => "RBW" -- Okay for Xilinx chips
|
||||
)
|
||||
port map (
|
||||
Clk => M_Axi_Aclk,
|
||||
Rst_n => M_Axi_Aresetn,
|
||||
Cmd_Addr => DmaMem_CmdAddr,
|
||||
Cmd_Size => DmaMem_CmdSize,
|
||||
Cmd_Vld => DmaMem_CmdVld,
|
||||
Cmd_Rdy => DmaMem_CmdRdy,
|
||||
Dat_Data => DmaMem_DatData,
|
||||
Dat_Vld => DmaMem_DatVld,
|
||||
Dat_Rdy => DmaMem_DatRdy,
|
||||
Done => MemSm_Done,
|
||||
M_Axi_AwAddr => M_Axi_AwAddr,
|
||||
M_Axi_AwLen => M_Axi_AwLen,
|
||||
M_Axi_AwSize => M_Axi_AwSize,
|
||||
M_Axi_AwBurst => M_Axi_AwBurst,
|
||||
M_Axi_AwLock => M_Axi_AwLock,
|
||||
M_Axi_AwCache => M_Axi_AwCache,
|
||||
M_Axi_AwProt => M_Axi_AwProt,
|
||||
M_Axi_AwValid => M_Axi_AwValid,
|
||||
M_Axi_AwReady => M_Axi_AwReady,
|
||||
M_Axi_WData => M_Axi_WData,
|
||||
M_Axi_WStrb => M_Axi_WStrb,
|
||||
M_Axi_WLast => M_Axi_WLast,
|
||||
M_Axi_WValid => M_Axi_WValid,
|
||||
M_Axi_WReady => M_Axi_WReady,
|
||||
M_Axi_BResp => M_Axi_BResp,
|
||||
M_Axi_BValid => M_Axi_BValid,
|
||||
M_Axi_BReady => M_Axi_BReady,
|
||||
M_Axi_ArAddr => M_Axi_ArAddr,
|
||||
M_Axi_ArLen => M_Axi_ArLen,
|
||||
M_Axi_ArSize => M_Axi_ArSize,
|
||||
M_Axi_ArBurst => M_Axi_ArBurst,
|
||||
M_Axi_ArLock => M_Axi_ArLock,
|
||||
M_Axi_ArCache => M_Axi_ArCache,
|
||||
M_Axi_ArProt => M_Axi_ArProt,
|
||||
M_Axi_ArValid => M_Axi_ArValid,
|
||||
M_Axi_ArReady => M_Axi_ArReady,
|
||||
M_Axi_RData => M_Axi_RData,
|
||||
M_Axi_RResp => M_Axi_RResp,
|
||||
M_Axi_RLast => M_Axi_RLast,
|
||||
M_Axi_RValid => M_Axi_RValid,
|
||||
M_Axi_RReady => M_Axi_RReady
|
||||
);
|
||||
|
||||
end;
|
||||
--------------------------------------------
|
||||
-- Input Logic Instantiation
|
||||
--------------------------------------------
|
||||
g_input : for str in 0 to Streams_g - 1 generate
|
||||
signal InRst : std_logic;
|
||||
signal StrInput : std_logic_vector(StreamWidth_c(str) - 1 downto 0);
|
||||
begin
|
||||
-- Reset if stream is disabled
|
||||
InRst <= M_Axi_Areset or not Cfg_StrEna(str) or not Cfg_GlbEna;
|
||||
StrInput <= Str_Data(str)(StrInput'range);
|
||||
|
||||
-- Instantiation
|
||||
i_input : entity work.psi_ms_daq_input
|
||||
generic map(
|
||||
StreamWidth_g => StreamWidth_c(str),
|
||||
StreamBuffer_g => StreamBuffer_c(str),
|
||||
StreamTimeout_g => StreamTimeout_c(str),
|
||||
StreamClkFreq_g => StreamClkFreq_c(str),
|
||||
StreamTsFifoDepth_g => StreamTsFifoDepth_c(str),
|
||||
StreamUseTs_g => StreamUseTs_c(str)
|
||||
)
|
||||
port map(
|
||||
Str_Clk => Str_Clk(str),
|
||||
Str_Vld => Str_Vld(str),
|
||||
Str_Rdy => Str_Rdy(str),
|
||||
Str_Data => StrInput,
|
||||
Str_Trig => Str_Trig(str),
|
||||
Str_Ts => Str_Ts(str),
|
||||
ClkReg => S_Axi_Aclk,
|
||||
RstReg => S_Axi_Areset,
|
||||
PostTrigSpls => Cfg_PostTrig(str),
|
||||
Mode => Cfg_RecMode(str),
|
||||
Arm => Cfg_Arm(str),
|
||||
IsArmed => Stat_IsArmed(str),
|
||||
IsRecording => Stat_IsRecording(str),
|
||||
ClkMem => M_Axi_Aclk,
|
||||
RstMem => InRst,
|
||||
Daq_Vld => InpDma_Vld(str),
|
||||
Daq_Rdy => InpDma_Rdy(str),
|
||||
Daq_Data => InpDma_Data(str),
|
||||
Daq_Level => InpSm_Level(str),
|
||||
Daq_HasLast => InpSm_HasTlast(str),
|
||||
Ts_Vld => InpSm_TsVld(str),
|
||||
Ts_Rdy => InpSm_TsRdy(str),
|
||||
Ts_Data => InpSm_TsData(str)
|
||||
);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------
|
||||
-- Control State Machine
|
||||
--------------------------------------------
|
||||
-- Detect end-of frame in input buffer or DMA buffer
|
||||
Sm_HasLast <= InpSm_HasTlast or DmaSm_HasLast;
|
||||
|
||||
-- Instantiation
|
||||
i_statemachine : entity work.psi_ms_daq_daq_sm
|
||||
generic map(
|
||||
Streams_g => Streams_g,
|
||||
StreamPrio_g => StreamPrio_c,
|
||||
StreamWidth_g => StreamWidth_c,
|
||||
Windows_g => MaxWindows_g,
|
||||
MinBurstSize_g => MinBurstSize_g,
|
||||
MaxBurstSize_g => MaxBurstSize_g
|
||||
)
|
||||
port map(
|
||||
Clk => M_Axi_Aclk,
|
||||
Rst => M_Axi_Areset,
|
||||
GlbEna => Cfg_GlbEna,
|
||||
StrEna => Cfg_StrEna,
|
||||
StrIrq => Stat_StrIrq,
|
||||
StrLastWin => Stat_StrLastWin,
|
||||
Inp_HasLast => Sm_HasLast,
|
||||
Inp_Level => InpSm_Level,
|
||||
Ts_Vld => InpSm_TsVld,
|
||||
Ts_Rdy => InpSm_TsRdy,
|
||||
Ts_Data => InpSm_TsData,
|
||||
Dma_Cmd => SmDma_Cmd,
|
||||
Dma_Cmd_Vld => SmDma_CmdVld,
|
||||
Dma_Resp => DmaSm_Resp,
|
||||
Dma_Resp_Vld => DmaSm_RespVld,
|
||||
Dma_Resp_Rdy => DmaSm_RespRdy,
|
||||
TfDone => MemSm_Done,
|
||||
-- Context RAM connections
|
||||
CtxStr_Cmd => CtxStr_Cmd,
|
||||
CtxStr_Resp => CtxStr_Resp,
|
||||
CtxWin_Cmd => CtxWin_Cmd,
|
||||
CtxWin_Resp => CtxWin_Resp
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- DMA Engine
|
||||
--------------------------------------------
|
||||
i_dma : entity work.psi_ms_daq_daq_dma
|
||||
generic map(
|
||||
Streams_g => Streams_g
|
||||
)
|
||||
port map(
|
||||
Clk => M_Axi_Aclk,
|
||||
Rst => M_Axi_Areset,
|
||||
DaqSm_Cmd => SmDma_Cmd,
|
||||
DaqSm_Cmd_Vld => SmDma_CmdVld,
|
||||
DaqSm_Resp => DmaSm_Resp,
|
||||
DaqSm_Resp_Vld => DmaSm_RespVld,
|
||||
DaqSm_Resp_Rdy => DmaSm_RespRdy,
|
||||
DaqSm_HasLast => DmaSm_HasLast,
|
||||
Inp_Vld => InpDma_Vld,
|
||||
Inp_Rdy => InpDma_Rdy,
|
||||
Inp_Data => InpDma_Data,
|
||||
Mem_CmdAddr => DmaMem_CmdAddr,
|
||||
Mem_CmdSize => DmaMem_CmdSize,
|
||||
Mem_CmdVld => DmaMem_CmdVld,
|
||||
Mem_CmdRdy => DmaMem_CmdRdy,
|
||||
Mem_DatData => DmaMem_DatData,
|
||||
Mem_DatVld => DmaMem_DatVld,
|
||||
Mem_DatRdy => DmaMem_DatRdy
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- Memory Interface
|
||||
--------------------------------------------
|
||||
i_memif : entity work.psi_ms_daq_axi_if
|
||||
generic map(
|
||||
AxiDataWidth_g => AxiDataWidth_g,
|
||||
AxiMaxBeats_g => AxiMaxBurstBeats_g,
|
||||
AxiMaxOpenTrasactions_g => AxiMaxOpenTrasactions_g,
|
||||
MaxOpenCommands_g => max(2, Streams_g), -- ISE tools implement memory as FFs for one stream. Reason is unkown, so we always implement two streams for resource optimization reasons.
|
||||
DataFifoDepth_g => 1024,
|
||||
AxiFifoDepth_g => AxiFifoDepth_g,
|
||||
RamBehavior_g => "RBW" -- Okay for Xilinx chips
|
||||
)
|
||||
port map(
|
||||
Clk => M_Axi_Aclk,
|
||||
Rst_n => M_Axi_Aresetn,
|
||||
Cmd_Addr => DmaMem_CmdAddr,
|
||||
Cmd_Size => DmaMem_CmdSize,
|
||||
Cmd_Vld => DmaMem_CmdVld,
|
||||
Cmd_Rdy => DmaMem_CmdRdy,
|
||||
Dat_Data => DmaMem_DatData,
|
||||
Dat_Vld => DmaMem_DatVld,
|
||||
Dat_Rdy => DmaMem_DatRdy,
|
||||
Done => MemSm_Done,
|
||||
M_Axi_AwAddr => M_Axi_AwAddr,
|
||||
M_Axi_AwLen => M_Axi_AwLen,
|
||||
M_Axi_AwSize => M_Axi_AwSize,
|
||||
M_Axi_AwBurst => M_Axi_AwBurst,
|
||||
M_Axi_AwLock => M_Axi_AwLock,
|
||||
M_Axi_AwCache => M_Axi_AwCache,
|
||||
M_Axi_AwProt => M_Axi_AwProt,
|
||||
M_Axi_AwValid => M_Axi_AwValid,
|
||||
M_Axi_AwReady => M_Axi_AwReady,
|
||||
M_Axi_WData => M_Axi_WData,
|
||||
M_Axi_WStrb => M_Axi_WStrb,
|
||||
M_Axi_WLast => M_Axi_WLast,
|
||||
M_Axi_WValid => M_Axi_WValid,
|
||||
M_Axi_WReady => M_Axi_WReady,
|
||||
M_Axi_BResp => M_Axi_BResp,
|
||||
M_Axi_BValid => M_Axi_BValid,
|
||||
M_Axi_BReady => M_Axi_BReady,
|
||||
M_Axi_ArAddr => M_Axi_ArAddr,
|
||||
M_Axi_ArLen => M_Axi_ArLen,
|
||||
M_Axi_ArSize => M_Axi_ArSize,
|
||||
M_Axi_ArBurst => M_Axi_ArBurst,
|
||||
M_Axi_ArLock => M_Axi_ArLock,
|
||||
M_Axi_ArCache => M_Axi_ArCache,
|
||||
M_Axi_ArProt => M_Axi_ArProt,
|
||||
M_Axi_ArValid => M_Axi_ArValid,
|
||||
M_Axi_ArReady => M_Axi_ArReady,
|
||||
M_Axi_RData => M_Axi_RData,
|
||||
M_Axi_RResp => M_Axi_RResp,
|
||||
M_Axi_RLast => M_Axi_RLast,
|
||||
M_Axi_RValid => M_Axi_RValid,
|
||||
M_Axi_RReady => M_Axi_RReady
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
@ -8,217 +8,204 @@
|
||||
-- Libraries
|
||||
------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_math_pkg.all;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
------------------------------------------------------------------------------
|
||||
entity psi_ms_daq_axi_if is
|
||||
generic (
|
||||
AxiDataWidth_g : natural range 64 to 1024 := 64;
|
||||
AxiMaxBeats_g : natural range 1 to 256 := 256;
|
||||
AxiMaxOpenTrasactions_g : natural range 1 to 8 := 8;
|
||||
MaxOpenCommands_g : positive := 16;
|
||||
DataFifoDepth_g : natural := 1024;
|
||||
AxiFifoDepth_g : natural := 1024;
|
||||
RamBehavior_g : string := "RBW"
|
||||
);
|
||||
port (
|
||||
-- Control Signals
|
||||
Clk : in std_logic;
|
||||
Rst_n : in std_logic;
|
||||
|
||||
-- Write Command
|
||||
Cmd_Addr : in std_logic_vector(31 downto 0);
|
||||
Cmd_Size : in std_logic_vector(31 downto 0);
|
||||
Cmd_Vld : in std_logic;
|
||||
Cmd_Rdy : out std_logic;
|
||||
|
||||
-- Write Data
|
||||
Dat_Data : in std_logic_vector(63 downto 0);
|
||||
Dat_Vld : in std_logic;
|
||||
Dat_Rdy : out std_logic;
|
||||
|
||||
-- Response
|
||||
Done : out std_logic;
|
||||
|
||||
-- AXI Address Write Channel
|
||||
M_Axi_AwAddr : out std_logic_vector(31 downto 0);
|
||||
M_Axi_AwLen : out std_logic_vector(7 downto 0);
|
||||
M_Axi_AwSize : out std_logic_vector(2 downto 0);
|
||||
M_Axi_AwBurst : out std_logic_vector(1 downto 0);
|
||||
M_Axi_AwLock : out std_logic;
|
||||
M_Axi_AwCache : out std_logic_vector(3 downto 0);
|
||||
M_Axi_AwProt : out std_logic_vector(2 downto 0);
|
||||
M_Axi_AwValid : out std_logic;
|
||||
M_Axi_AwReady : in std_logic := '0';
|
||||
|
||||
-- AXI Write Data Channel
|
||||
M_Axi_WData : out std_logic_vector(AxiDataWidth_g-1 downto 0);
|
||||
M_Axi_WStrb : out std_logic_vector(AxiDataWidth_g/8-1 downto 0);
|
||||
M_Axi_WLast : out std_logic;
|
||||
M_Axi_WValid : out std_logic;
|
||||
M_Axi_WReady : in std_logic := '0';
|
||||
|
||||
-- AXI Write Response Channel
|
||||
M_Axi_BResp : in std_logic_vector(1 downto 0) := (others => '0');
|
||||
M_Axi_BValid : in std_logic := '0';
|
||||
M_Axi_BReady : out std_logic;
|
||||
|
||||
-- AXI Read Address Channel
|
||||
M_Axi_ArAddr : out std_logic_vector(31 downto 0);
|
||||
M_Axi_ArLen : out std_logic_vector(7 downto 0);
|
||||
M_Axi_ArSize : out std_logic_vector(2 downto 0);
|
||||
M_Axi_ArBurst : out std_logic_vector(1 downto 0);
|
||||
M_Axi_ArLock : out std_logic;
|
||||
M_Axi_ArCache : out std_logic_vector(3 downto 0);
|
||||
M_Axi_ArProt : out std_logic_vector(2 downto 0);
|
||||
M_Axi_ArValid : out std_logic;
|
||||
M_Axi_ArReady : in std_logic := '0';
|
||||
|
||||
-- AXI Read Data Channel
|
||||
M_Axi_RData : in std_logic_vector(AxiDataWidth_g-1 downto 0) := (others => '0');
|
||||
M_Axi_RResp : in std_logic_vector(1 downto 0) := (others => '0');
|
||||
M_Axi_RLast : in std_logic := '0';
|
||||
M_Axi_RValid : in std_logic := '0';
|
||||
M_Axi_RReady : out std_logic
|
||||
);
|
||||
generic(
|
||||
AxiDataWidth_g : natural range 64 to 1024 := 64;
|
||||
AxiMaxBeats_g : natural range 1 to 256 := 256;
|
||||
AxiMaxOpenTrasactions_g : natural range 1 to 8 := 8;
|
||||
MaxOpenCommands_g : positive := 16;
|
||||
DataFifoDepth_g : natural := 1024;
|
||||
AxiFifoDepth_g : natural := 1024;
|
||||
RamBehavior_g : string := "RBW"
|
||||
);
|
||||
port(
|
||||
-- Control Signals
|
||||
Clk : in std_logic;
|
||||
Rst_n : in std_logic;
|
||||
-- Write Command
|
||||
Cmd_Addr : in std_logic_vector(31 downto 0);
|
||||
Cmd_Size : in std_logic_vector(31 downto 0);
|
||||
Cmd_Vld : in std_logic;
|
||||
Cmd_Rdy : out std_logic;
|
||||
-- Write Data
|
||||
Dat_Data : in std_logic_vector(63 downto 0);
|
||||
Dat_Vld : in std_logic;
|
||||
Dat_Rdy : out std_logic;
|
||||
-- Response
|
||||
Done : out std_logic;
|
||||
-- AXI Address Write Channel
|
||||
M_Axi_AwAddr : out std_logic_vector(31 downto 0);
|
||||
M_Axi_AwLen : out std_logic_vector(7 downto 0);
|
||||
M_Axi_AwSize : out std_logic_vector(2 downto 0);
|
||||
M_Axi_AwBurst : out std_logic_vector(1 downto 0);
|
||||
M_Axi_AwLock : out std_logic;
|
||||
M_Axi_AwCache : out std_logic_vector(3 downto 0);
|
||||
M_Axi_AwProt : out std_logic_vector(2 downto 0);
|
||||
M_Axi_AwValid : out std_logic;
|
||||
M_Axi_AwReady : in std_logic := '0';
|
||||
-- AXI Write Data Channel
|
||||
M_Axi_WData : out std_logic_vector(AxiDataWidth_g - 1 downto 0);
|
||||
M_Axi_WStrb : out std_logic_vector(AxiDataWidth_g / 8 - 1 downto 0);
|
||||
M_Axi_WLast : out std_logic;
|
||||
M_Axi_WValid : out std_logic;
|
||||
M_Axi_WReady : in std_logic := '0';
|
||||
-- AXI Write Response Channel
|
||||
M_Axi_BResp : in std_logic_vector(1 downto 0) := (others => '0');
|
||||
M_Axi_BValid : in std_logic := '0';
|
||||
M_Axi_BReady : out std_logic;
|
||||
-- AXI Read Address Channel
|
||||
M_Axi_ArAddr : out std_logic_vector(31 downto 0);
|
||||
M_Axi_ArLen : out std_logic_vector(7 downto 0);
|
||||
M_Axi_ArSize : out std_logic_vector(2 downto 0);
|
||||
M_Axi_ArBurst : out std_logic_vector(1 downto 0);
|
||||
M_Axi_ArLock : out std_logic;
|
||||
M_Axi_ArCache : out std_logic_vector(3 downto 0);
|
||||
M_Axi_ArProt : out std_logic_vector(2 downto 0);
|
||||
M_Axi_ArValid : out std_logic;
|
||||
M_Axi_ArReady : in std_logic := '0';
|
||||
-- AXI Read Data Channel
|
||||
M_Axi_RData : in std_logic_vector(AxiDataWidth_g - 1 downto 0) := (others => '0');
|
||||
M_Axi_RResp : in std_logic_vector(1 downto 0) := (others => '0');
|
||||
M_Axi_RLast : in std_logic := '0';
|
||||
M_Axi_RValid : in std_logic := '0';
|
||||
M_Axi_RReady : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture Declaration
|
||||
------------------------------------------------------------------------------
|
||||
architecture rtl of psi_ms_daq_axi_if is
|
||||
signal Rst : std_logic;
|
||||
|
||||
subtype CommandAddrRng_c is natural range 31 downto 0;
|
||||
subtype CommandSizeRng_c is natural range 63 downto 32;
|
||||
constant WrCmdWidth_c : integer := CommandSizeRng_c'high+1;
|
||||
signal InfoFifoIn : std_logic_vector(WrCmdWidth_c-1 downto 0);
|
||||
signal InfoFifoOut : std_logic_vector(WrCmdWidth_c-1 downto 0);
|
||||
signal WrCmdFifo_Vld : std_logic;
|
||||
signal WrCmdFifo_Rdy : std_logic;
|
||||
signal WrCmdFifo_Addr : std_logic_vector(31 downto 0);
|
||||
signal WrCmdFifo_Size : std_logic_vector(31 downto 0);
|
||||
signal DoneI : std_logic;
|
||||
signal ErrorI : std_logic;
|
||||
|
||||
architecture rtl of psi_ms_daq_axi_if is
|
||||
signal Rst : std_logic;
|
||||
|
||||
subtype CommandAddrRng_c is natural range 31 downto 0;
|
||||
subtype CommandSizeRng_c is natural range 63 downto 32;
|
||||
constant WrCmdWidth_c : integer := CommandSizeRng_c'high + 1;
|
||||
signal InfoFifoIn : std_logic_vector(WrCmdWidth_c - 1 downto 0);
|
||||
signal InfoFifoOut : std_logic_vector(WrCmdWidth_c - 1 downto 0);
|
||||
signal WrCmdFifo_Vld : std_logic;
|
||||
signal WrCmdFifo_Rdy : std_logic;
|
||||
signal WrCmdFifo_Addr : std_logic_vector(31 downto 0);
|
||||
signal WrCmdFifo_Size : std_logic_vector(31 downto 0);
|
||||
signal DoneI : std_logic;
|
||||
signal ErrorI : std_logic;
|
||||
|
||||
begin
|
||||
Rst <= not Rst_n;
|
||||
|
||||
InfoFifoIn(CommandAddrRng_c) <= Cmd_Addr;
|
||||
InfoFifoIn(CommandSizeRng_c) <= Cmd_Size;
|
||||
|
||||
i_wrinfo_fifo : entity work.psi_common_sync_fifo
|
||||
generic map (
|
||||
Width_g => WrCmdWidth_c,
|
||||
Depth_g => MaxOpenCommands_g,
|
||||
RamStyle_g => "distributed"
|
||||
)
|
||||
port map (
|
||||
Clk => Clk,
|
||||
Rst => Rst,
|
||||
InData => InfoFifoIn,
|
||||
InVld => Cmd_Vld,
|
||||
InRdy => Cmd_Rdy,
|
||||
OutData => InfoFifoOut,
|
||||
OutVld => WrCmdFifo_Vld,
|
||||
OutRdy => WrCmdFifo_Rdy
|
||||
);
|
||||
|
||||
WrCmdFifo_Addr <= InfoFifoOut(CommandAddrRng_c);
|
||||
WrCmdFifo_Size <= InfoFifoOut(CommandSizeRng_c);
|
||||
Rst <= not Rst_n;
|
||||
|
||||
i_axi : entity work.psi_common_axi_master_full
|
||||
generic map (
|
||||
AxiAddrWidth_g => 32,
|
||||
AxiDataWidth_g => AxiDataWidth_g,
|
||||
AxiMaxBeats_g => AxiMaxBeats_g,
|
||||
AxiMaxOpenTrasactions_g => AxiMaxOpenTrasactions_g,
|
||||
UserTransactionSizeBits_g => 32,
|
||||
DataFifoDepth_g => DataFifoDepth_g,
|
||||
DataWidth_g => 64,
|
||||
ImplRead_g => false,
|
||||
ImplWrite_g => true,
|
||||
RamBehavior_g => RamBehavior_g
|
||||
)
|
||||
port map (
|
||||
-- Control Signals
|
||||
M_Axi_Aclk => Clk,
|
||||
M_Axi_Aresetn => Rst_n,
|
||||
-- User Command Interface Write
|
||||
CmdWr_Addr => WrCmdFifo_Addr,
|
||||
CmdWr_Size => WrCmdFifo_Size,
|
||||
CmdWr_LowLat => '0',
|
||||
CmdWr_Vld => WrCmdFifo_Vld,
|
||||
CmdWr_Rdy => WrCmdFifo_Rdy,
|
||||
-- User Command Interface Read (unused)
|
||||
CmdRd_Addr => (others => '0'),
|
||||
CmdRd_Size => (others => '0'),
|
||||
CmdRd_LowLat => '0',
|
||||
CmdRd_Vld => '0',
|
||||
CmdRd_Rdy => open,
|
||||
-- Write Data
|
||||
WrDat_Data => Dat_Data,
|
||||
WrDat_Vld => Dat_Vld,
|
||||
WrDat_Rdy => Dat_Rdy,
|
||||
-- Read Data (unused)
|
||||
RdDat_Data => open,
|
||||
RdDat_Vld => open,
|
||||
RdDat_Rdy => '0',
|
||||
-- Response
|
||||
Wr_Done => DoneI,
|
||||
Wr_Error => ErrorI,
|
||||
Rd_Done => open,
|
||||
Rd_Error => open,
|
||||
-- AXI Address Write Channel
|
||||
M_Axi_AwAddr => M_Axi_AwAddr,
|
||||
M_Axi_AwLen => M_Axi_AwLen,
|
||||
M_Axi_AwSize => M_Axi_AwSize,
|
||||
M_Axi_AwBurst => M_Axi_AwBurst,
|
||||
M_Axi_AwLock => M_Axi_AwLock,
|
||||
M_Axi_AwCache => M_Axi_AwCache,
|
||||
M_Axi_AwProt => M_Axi_AwProt,
|
||||
M_Axi_AwValid => M_Axi_AwValid,
|
||||
M_Axi_AwReady => M_Axi_AwReady,
|
||||
-- AXI Write Data Channel
|
||||
M_Axi_WData => M_Axi_WData,
|
||||
M_Axi_WStrb => M_Axi_WStrb,
|
||||
M_Axi_WLast => M_Axi_WLast,
|
||||
M_Axi_WValid => M_Axi_WValid,
|
||||
M_Axi_WReady => M_Axi_WReady,
|
||||
-- AXI Write Response Channel
|
||||
M_Axi_BResp => M_Axi_BResp,
|
||||
M_Axi_BValid => M_Axi_BValid,
|
||||
M_Axi_BReady => M_Axi_BReady,
|
||||
-- AXI Read Address Channel
|
||||
M_Axi_ArAddr => M_Axi_ArAddr,
|
||||
M_Axi_ArLen => M_Axi_ArLen,
|
||||
M_Axi_ArSize => M_Axi_ArSize,
|
||||
M_Axi_ArBurst => M_Axi_ArBurst,
|
||||
M_Axi_ArLock => M_Axi_ArLock,
|
||||
M_Axi_ArCache => M_Axi_ArCache,
|
||||
M_Axi_ArProt => M_Axi_ArProt,
|
||||
M_Axi_ArValid => M_Axi_ArValid,
|
||||
M_Axi_ArReady => M_Axi_ArReady,
|
||||
-- AXI Read Data Channel
|
||||
M_Axi_RData => M_Axi_RData,
|
||||
M_Axi_RResp => M_Axi_RResp,
|
||||
M_Axi_RLast => M_Axi_RLast,
|
||||
M_Axi_RValid => M_Axi_RValid,
|
||||
M_Axi_RReady => M_Axi_RReady
|
||||
);
|
||||
|
||||
Done <= DoneI or ErrorI;
|
||||
|
||||
|
||||
end;
|
||||
InfoFifoIn(CommandAddrRng_c) <= Cmd_Addr;
|
||||
InfoFifoIn(CommandSizeRng_c) <= Cmd_Size;
|
||||
|
||||
i_wrinfo_fifo : entity work.psi_common_sync_fifo
|
||||
generic map(
|
||||
width_g => WrCmdWidth_c,
|
||||
depth_g => MaxOpenCommands_g,
|
||||
ram_style_g => "distributed"
|
||||
)
|
||||
port map(
|
||||
clk_i => Clk,
|
||||
rst_i => Rst,
|
||||
dat_i => InfoFifoIn,
|
||||
vld_i => Cmd_Vld,
|
||||
rdy_o => Cmd_Rdy,
|
||||
dat_o => InfoFifoOut,
|
||||
vld_o => WrCmdFifo_Vld,
|
||||
rdy_i => WrCmdFifo_Rdy
|
||||
);
|
||||
|
||||
WrCmdFifo_Addr <= InfoFifoOut(CommandAddrRng_c);
|
||||
WrCmdFifo_Size <= InfoFifoOut(CommandSizeRng_c);
|
||||
|
||||
i_axi : entity work.psi_common_axi_master_full
|
||||
generic map(
|
||||
axi_addr_width_g => 32,
|
||||
axi_data_width_g => AxiDataWidth_g,
|
||||
axi_max_beats_g => AxiMaxBeats_g,
|
||||
axi_max_open_trasactions_g => AxiMaxOpenTrasactions_g,
|
||||
user_transaction_size_bits_g => 32,
|
||||
data_fifo_depth_g => DataFifoDepth_g,
|
||||
data_width_g => 64,
|
||||
impl_read_g => false,
|
||||
impl_write_g => true,
|
||||
ram_behavior_g => RamBehavior_g
|
||||
)
|
||||
port map(
|
||||
-- Control Signals
|
||||
m_axi_aclk => Clk,
|
||||
m_axi_aresetn => Rst_n,
|
||||
-- User Command Interface Write
|
||||
cmd_wr_addr_i => WrCmdFifo_Addr,
|
||||
cmd_wr_size_i => WrCmdFifo_Size,
|
||||
cmd_wr_low_lat_i => '0',
|
||||
cmd_wr_vld_i => WrCmdFifo_Vld,
|
||||
cmd_wr_rdy_o => WrCmdFifo_Rdy,
|
||||
-- User Command Interface Read (unused)
|
||||
cmd_rd_addr_i => (others => '0'),
|
||||
cmd_rd_size_o => (others => '0'),
|
||||
cmd_rd_low_lat_i => '0',
|
||||
cmd_rd_vld_i => '0',
|
||||
cmd_rd_rdy_o => open,
|
||||
-- Write Data
|
||||
wr_dat_i => Dat_Data,
|
||||
wr_vld_i => Dat_Vld,
|
||||
wr_rdy_o => Dat_Rdy,
|
||||
-- Read Data (unused)
|
||||
rd_dat_o => open,
|
||||
rd_vld_o => open,
|
||||
rd_rdy_i => '0',
|
||||
-- Response
|
||||
wr_done_o => DoneI,
|
||||
wr_error_o => ErrorI,
|
||||
rd_done_o => open,
|
||||
rd_error_o => open,
|
||||
-- AXI Address Write Channel
|
||||
m_axi_awaddr => M_Axi_AwAddr,
|
||||
m_axi_awlen => M_Axi_AwLen,
|
||||
m_axi_awsize => M_Axi_AwSize,
|
||||
m_axi_awburst => M_Axi_AwBurst,
|
||||
m_axi_awlock => M_Axi_AwLock,
|
||||
m_axi_awcache => M_Axi_AwCache,
|
||||
m_axi_awprot => M_Axi_AwProt,
|
||||
m_axi_awvalid => M_Axi_AwValid,
|
||||
m_axi_awready => M_Axi_AwReady,
|
||||
-- AXI Write Data Channel
|
||||
m_axi_wdata => M_Axi_WData,
|
||||
m_axi_wstrb => M_Axi_WStrb,
|
||||
m_axi_wlast => M_Axi_WLast,
|
||||
m_axi_wvalid => M_Axi_WValid,
|
||||
m_axi_wready => M_Axi_WReady,
|
||||
-- AXI Write Response Channel
|
||||
m_axi_bresp => M_Axi_BResp,
|
||||
m_axi_bvalid => M_Axi_BValid,
|
||||
m_axi_bready => M_Axi_BReady,
|
||||
-- AXI Read Address Channel
|
||||
m_axi_araddr => M_Axi_ArAddr,
|
||||
m_axi_arlen => M_Axi_ArLen,
|
||||
m_axi_arsize => M_Axi_ArSize,
|
||||
m_axi_arburst => M_Axi_ArBurst,
|
||||
m_axi_arlock => M_Axi_ArLock,
|
||||
m_axi_arcache => M_Axi_ArCache,
|
||||
m_axi_arprot => M_Axi_ArProt,
|
||||
m_axi_arvalid => M_Axi_ArValid,
|
||||
m_axi_arready => M_Axi_ArReady,
|
||||
-- AXI Read Data Channel
|
||||
m_axi_rdata => M_Axi_RData,
|
||||
m_axi_rresp => M_Axi_RResp,
|
||||
m_axi_rlast => M_Axi_RLast,
|
||||
m_axi_rvalid => M_Axi_RValid,
|
||||
m_axi_rready => M_Axi_RReady
|
||||
);
|
||||
|
||||
Done <= DoneI or ErrorI;
|
||||
|
||||
end;
|
||||
|
||||
|
||||
@ -13,14 +13,14 @@
|
||||
-- Libraries
|
||||
------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_logic_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_logic_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
@ -29,372 +29,364 @@ library work;
|
||||
-- $$ processes=control,input,mem_cmd,mem_dat $$
|
||||
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg,work.psi_tb_activity_pkg $$
|
||||
entity psi_ms_daq_daq_dma is
|
||||
generic (
|
||||
Streams_g : positive range 1 to 32 := 4 -- $$ constant=4 $$
|
||||
);
|
||||
port (
|
||||
-- Control signals
|
||||
Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=control,input,mem_dat,mem_cmd $$
|
||||
Rst : in std_logic; -- $$ type=rst; clk=Clk; proc=control $$
|
||||
generic(
|
||||
Streams_g : positive range 1 to 32 := 4 -- $$ constant=4 $$
|
||||
);
|
||||
port(
|
||||
-- Control signals
|
||||
Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=control,input,mem_dat,mem_cmd $$
|
||||
Rst : in std_logic; -- $$ type=rst; clk=Clk; proc=control $$
|
||||
|
||||
-- DAQ Statemachione Connections
|
||||
DaqSm_Cmd : in DaqSm2DaqDma_Cmd_t; -- $$ proc=control $$
|
||||
DaqSm_Cmd_Vld : in std_logic; -- $$ proc=control $$
|
||||
DaqSm_Resp : out DaqDma2DaqSm_Resp_t; -- $$ proc=control $$
|
||||
DaqSm_Resp_Vld : out std_logic; -- $$ proc=control $$
|
||||
DaqSm_Resp_Rdy : in std_logic; -- $$ proc=control $$
|
||||
DaqSm_HasLast : out std_logic_vector(Streams_g-1 downto 0); -- $$ proc=control $$
|
||||
|
||||
-- Input handling connections
|
||||
Inp_Vld : in std_logic_vector(Streams_g-1 downto 0); -- $$ proc=input $$
|
||||
Inp_Rdy : out std_logic_vector(Streams_g-1 downto 0); -- $$ proc=input $$
|
||||
Inp_Data : in Input2Daq_Data_a(Streams_g-1 downto 0); -- $$ proc=input $$
|
||||
|
||||
-- Memory interface connections
|
||||
Mem_CmdAddr : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
|
||||
Mem_CmdSize : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
|
||||
Mem_CmdVld : out std_logic; -- $$ proc=mem_cmd $$
|
||||
Mem_CmdRdy : in std_logic; -- $$ proc=mem_cmd $$
|
||||
Mem_DatData : out std_logic_vector(63 downto 0); -- $$ proc=mem_dat $$
|
||||
Mem_DatVld : out std_logic; -- $$ proc=mem_dat $$
|
||||
Mem_DatRdy : in std_logic -- $$ proc=mem_dat $$
|
||||
);
|
||||
-- DAQ Statemachione Connections
|
||||
DaqSm_Cmd : in DaqSm2DaqDma_Cmd_t; -- $$ proc=control $$
|
||||
DaqSm_Cmd_Vld : in std_logic; -- $$ proc=control $$
|
||||
DaqSm_Resp : out DaqDma2DaqSm_Resp_t; -- $$ proc=control $$
|
||||
DaqSm_Resp_Vld : out std_logic; -- $$ proc=control $$
|
||||
DaqSm_Resp_Rdy : in std_logic; -- $$ proc=control $$
|
||||
DaqSm_HasLast : out std_logic_vector(Streams_g - 1 downto 0); -- $$ proc=control $$
|
||||
|
||||
-- Input handling connections
|
||||
Inp_Vld : in std_logic_vector(Streams_g - 1 downto 0); -- $$ proc=input $$
|
||||
Inp_Rdy : out std_logic_vector(Streams_g - 1 downto 0); -- $$ proc=input $$
|
||||
Inp_Data : in Input2Daq_Data_a(Streams_g - 1 downto 0); -- $$ proc=input $$
|
||||
|
||||
-- Memory interface connections
|
||||
Mem_CmdAddr : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
|
||||
Mem_CmdSize : out std_logic_vector(31 downto 0); -- $$ proc=mem_cmd $$
|
||||
Mem_CmdVld : out std_logic; -- $$ proc=mem_cmd $$
|
||||
Mem_CmdRdy : in std_logic; -- $$ proc=mem_cmd $$
|
||||
Mem_DatData : out std_logic_vector(63 downto 0); -- $$ proc=mem_dat $$
|
||||
Mem_DatVld : out std_logic; -- $$ proc=mem_dat $$
|
||||
Mem_DatRdy : in std_logic -- $$ proc=mem_dat $$
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture Declaration
|
||||
------------------------------------------------------------------------------
|
||||
architecture rtl of psi_ms_daq_daq_dma is
|
||||
|
||||
-- Constants
|
||||
constant BufferFifoDepth_c : integer := 32;
|
||||
|
||||
-- Number of bits to encode stream is at least 1 (otherwise the special case for one stream would require separate code).
|
||||
-- .. The overhead generated by this is regarded as aceptable (better wasting a few LUTs than much development time)
|
||||
constant StreamBits_c : integer := max(log2ceil(Streams_g), 1);
|
||||
-- Constants
|
||||
constant BufferFifoDepth_c : integer := 32;
|
||||
|
||||
|
||||
-- Component Connection Signals
|
||||
signal CmdFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
|
||||
signal CmdFifo_InData : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c-1 downto 0);
|
||||
signal CmdFifo_OutData : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c-1 downto 0);
|
||||
signal CmdFifo_Cmd : DaqSm2DaqDma_Cmd_t;
|
||||
signal CmdFifo_Vld : std_logic;
|
||||
signal RspFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
|
||||
signal RspFifo_InData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
|
||||
signal RspFifo_OutData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
|
||||
signal DatFifo_Level_Dbg : std_logic_vector(log2ceil(BufferFifoDepth_c) downto 0);
|
||||
signal DatFifo_AlmFull : std_logic;
|
||||
signal Rem_RdBytes : std_logic_vector(2 downto 0);
|
||||
signal Rem_Data : std_logic_vector(63 downto 0);
|
||||
signal Rem_Trigger : std_logic;
|
||||
signal Rem_Last : std_logic;
|
||||
|
||||
-- Types
|
||||
type State_t is (Idle_s, RemRd1_s, RemRd2_s, Transfer_s, Done_s, Cmd_s);
|
||||
-- Number of bits to encode stream is at least 1 (otherwise the special case for one stream would require separate code).
|
||||
-- .. The overhead generated by this is regarded as aceptable (better wasting a few LUTs than much development time)
|
||||
constant StreamBits_c : integer := max(log2ceil(Streams_g), 1);
|
||||
|
||||
-- Component Connection Signals
|
||||
signal CmdFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
|
||||
signal CmdFifo_InData : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c - 1 downto 0);
|
||||
signal CmdFifo_OutData : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c - 1 downto 0);
|
||||
signal CmdFifo_Cmd : DaqSm2DaqDma_Cmd_t;
|
||||
signal CmdFifo_Vld : std_logic;
|
||||
signal RspFifo_Level_Dbg : std_logic_vector(StreamBits_c downto 0);
|
||||
signal RspFifo_InData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c - 1 downto 0);
|
||||
signal RspFifo_OutData : std_logic_vector(DaqDma2DaqSm_Resp_Size_c - 1 downto 0);
|
||||
signal DatFifo_Level_Dbg : std_logic_vector(log2ceil(BufferFifoDepth_c) downto 0);
|
||||
signal DatFifo_AlmFull : std_logic;
|
||||
signal Rem_RdBytes : std_logic_vector(2 downto 0);
|
||||
signal Rem_Data : std_logic_vector(63 downto 0);
|
||||
signal Rem_Trigger : std_logic;
|
||||
signal Rem_Last : std_logic;
|
||||
|
||||
-- Types
|
||||
type State_t is (Idle_s, RemRd1_s, RemRd2_s, Transfer_s, Done_s, Cmd_s);
|
||||
|
||||
-- Two process method
|
||||
type two_process_r is record
|
||||
CmdFifo_Rdy : std_logic;
|
||||
RspFifo_Vld : std_logic;
|
||||
RspFifo_Data : DaqDma2DaqSm_Resp_t;
|
||||
Mem_DataVld : std_logic;
|
||||
StreamStdlv : std_logic_vector(StreamBits_c - 1 downto 0);
|
||||
RemWen : std_logic;
|
||||
RemWrBytes : std_logic_vector(2 downto 0);
|
||||
RemData : std_logic_vector(63 downto 0);
|
||||
RemTrigger : std_logic;
|
||||
RemLast : std_logic;
|
||||
RemWrTrigger : std_logic;
|
||||
RemWrLast : std_logic;
|
||||
State : State_t;
|
||||
HndlMaxSize : unsigned(15 downto 0);
|
||||
RdBytes : unsigned(15 downto 0);
|
||||
WrBytes : unsigned(15 downto 0);
|
||||
HndlStream : integer range 0 to MaxStreams_c - 1;
|
||||
HndlAddress : std_logic_vector(31 downto 0);
|
||||
UpdateLast : std_logic;
|
||||
HndlSft : unsigned(2 downto 0);
|
||||
FirstDma : std_logic_vector(Streams_g - 1 downto 0);
|
||||
Mem_CmdVld : std_logic;
|
||||
Trigger : std_logic;
|
||||
Last : std_logic;
|
||||
DataSft : std_logic_vector(127 downto 0);
|
||||
NextDone : std_logic;
|
||||
DataWritten : std_logic;
|
||||
HasLast : std_logic_vector(Streams_g - 1 downto 0);
|
||||
end record;
|
||||
signal r, r_next : two_process_r;
|
||||
|
||||
-- Two process method
|
||||
type two_process_r is record
|
||||
CmdFifo_Rdy : std_logic;
|
||||
RspFifo_Vld : std_logic;
|
||||
RspFifo_Data : DaqDma2DaqSm_Resp_t;
|
||||
Mem_DataVld : std_logic;
|
||||
StreamStdlv : std_logic_vector(StreamBits_c-1 downto 0);
|
||||
RemWen : std_logic;
|
||||
RemWrBytes : std_logic_vector(2 downto 0);
|
||||
RemData : std_logic_vector(63 downto 0);
|
||||
RemTrigger : std_logic;
|
||||
RemLast : std_logic;
|
||||
RemWrTrigger : std_logic;
|
||||
RemWrLast : std_logic;
|
||||
State : State_t;
|
||||
HndlMaxSize : unsigned(15 downto 0);
|
||||
RdBytes : unsigned(15 downto 0);
|
||||
WrBytes : unsigned(15 downto 0);
|
||||
HndlStream : integer range 0 to MaxStreams_c-1;
|
||||
HndlAddress : std_logic_vector(31 downto 0);
|
||||
UpdateLast : std_logic;
|
||||
HndlSft : unsigned(2 downto 0);
|
||||
FirstDma : std_logic_vector(Streams_g-1 downto 0);
|
||||
Mem_CmdVld : std_logic;
|
||||
Trigger : std_logic;
|
||||
Last : std_logic;
|
||||
DataSft : std_logic_vector(127 downto 0);
|
||||
NextDone : std_logic;
|
||||
DataWritten : std_logic;
|
||||
HasLast : std_logic_vector(Streams_g-1 downto 0);
|
||||
end record;
|
||||
signal r, r_next : two_process_r;
|
||||
|
||||
|
||||
begin
|
||||
--------------------------------------------
|
||||
-- Combinatorial Process
|
||||
--------------------------------------------
|
||||
p_comb : process( r, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp_Rdy, Inp_Vld, Inp_Data, Mem_CmdRdy, Mem_DatRdy,
|
||||
CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull, Rem_RdBytes, Rem_Data, Rem_Trigger, Rem_Last)
|
||||
variable v : two_process_r;
|
||||
variable ThisByte_v : std_logic_vector(7 downto 0);
|
||||
variable RemSft_v : integer range 0 to 7;
|
||||
begin
|
||||
-- *** Hold variables stable ***
|
||||
v := r;
|
||||
|
||||
-- *** Default Values ***
|
||||
v.CmdFifo_Rdy := '0';
|
||||
Inp_Rdy <= (others => '0');
|
||||
v.Mem_DataVld := '0';
|
||||
v.RspFifo_Vld := '0';
|
||||
v.RemWen := '0';
|
||||
v.UpdateLast := '0';
|
||||
|
||||
-- *** State Machine ***
|
||||
case r.State is
|
||||
|
||||
when Idle_s =>
|
||||
v.HndlMaxSize := unsigned(CmdFifo_Cmd.MaxSize);
|
||||
v.HndlStream := CmdFifo_Cmd.Stream;
|
||||
v.StreamStdlv := std_logic_vector(to_unsigned(CmdFifo_Cmd.Stream, v.StreamStdlv'length));
|
||||
v.HndlAddress := CmdFifo_Cmd.Address;
|
||||
v.Trigger := '0';
|
||||
v.Last := '0';
|
||||
if CmdFifo_Vld = '1' then
|
||||
v.CmdFifo_Rdy := '1';
|
||||
v.State := RemRd1_s;
|
||||
end if;
|
||||
|
||||
when RemRd1_s =>
|
||||
v.State := RemRd2_s;
|
||||
|
||||
when RemRd2_s =>
|
||||
-- Prevent RAM data from before reset to have an influence
|
||||
v.WrBytes := (others => '0');
|
||||
if r.FirstDma(r.HndlStream) = '1' then
|
||||
v.HndlSft := (others => '0');
|
||||
v.RdBytes := (others => '0');
|
||||
v.DataSft := (others => '0');
|
||||
v.RemTrigger := '0';
|
||||
v.RemLast := '0';
|
||||
else
|
||||
v.HndlSft := unsigned(Rem_RdBytes);
|
||||
v.DataSft(127 downto 64) := Rem_Data;
|
||||
v.RdBytes := resize(unsigned(Rem_RdBytes), v.RdBytes'length);
|
||||
v.RemTrigger := Rem_Trigger;
|
||||
v.RemLast := Rem_Last;
|
||||
end if;
|
||||
v.FirstDma(r.HndlStream) := '0';
|
||||
v.State := Transfer_s;
|
||||
v.NextDone := '0';
|
||||
v.DataWritten := '0';
|
||||
|
||||
when Transfer_s =>
|
||||
-- TF done because of maximum size reached
|
||||
if r.WrBytes >= r.HndlMaxSize then
|
||||
v.State := Done_s;
|
||||
elsif DatFifo_AlmFull = '0' then
|
||||
if r.NextDone = '0' and Inp_Vld(r.HndlStream) = '1' and r.RemLast = '0' then
|
||||
v.RdBytes := r.RdBytes + unsigned(Inp_Data(r.HndlStream).Bytes);
|
||||
end if;
|
||||
v.WrBytes := r.WrBytes + 8;
|
||||
-- Combinatorial handling because of fall-through interface at input
|
||||
if r.RdBytes < r.HndlMaxSize and r.NextDone = '0' and r.RemLast = '0' then
|
||||
Inp_Rdy(r.HndlStream) <= '1';
|
||||
end if;
|
||||
-- Handling of last frame
|
||||
if (Inp_Data(r.HndlStream).Last = '1') or (r.RemLast = '1') then
|
||||
-- Do one more word if not all data can be transferred in the current beat (NextDone = 1)
|
||||
if (r.HndlSft + unsigned(Inp_Data(r.HndlStream).Bytes) <= 8) or (r.RemLast = '1') then
|
||||
v.State := Done_s;
|
||||
else
|
||||
v.NextDone := '1';
|
||||
end if;
|
||||
if (Inp_Data(r.HndlStream).IsTrig = '1') or (r.RemTrigger = '1') then
|
||||
v.Trigger :='1';
|
||||
end if;
|
||||
v.Last := '1';
|
||||
end if;
|
||||
if r.NextDone = '1' or Inp_Vld(r.HndlStream) = '0' then
|
||||
v.State := Done_s;
|
||||
end if;
|
||||
-- Data handling
|
||||
v.DataSft(63 downto 0) := r.DataSft(127 downto 64);
|
||||
v.DataSft(8*to_integer(r.HndlSft)+63 downto 8*to_integer(r.HndlSft)) := Inp_Data(r.HndlStream).Data;
|
||||
if Inp_Vld(r.HndlStream) = '1' or r.HndlSft /= 0 then
|
||||
v.Mem_DataVld := '1';
|
||||
v.DataWritten := '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when Done_s =>
|
||||
RemSft_v := to_integer(resize(r.HndlMaxSize, 3));
|
||||
v.RemWrTrigger := '0';
|
||||
v.RemWrLast := '0';
|
||||
if r.HndlMaxSize < r.RdBytes then
|
||||
v.RemWrBytes := std_logic_vector(resize(r.RdBytes - r.HndlMaxSize, v.RemWrBytes'length));
|
||||
v.RdBytes := r.HndlMaxSize;
|
||||
v.RemWrTrigger := r.Trigger;
|
||||
v.RemWrLast := r.Last;
|
||||
v.HasLast(r.HndlStream) := r.Last;
|
||||
else
|
||||
v.RemWrBytes := (others => '0');
|
||||
v.HasLast(r.HndlStream) := '0';
|
||||
end if;
|
||||
v.RemData := v.DataSft(8*RemSft_v+63 downto 8*RemSft_v);
|
||||
v.State := Cmd_s;
|
||||
if r.DataWritten = '1' then
|
||||
v.Mem_CmdVld := '1';
|
||||
end if;
|
||||
v.RemWen := '1';
|
||||
|
||||
when Cmd_s =>
|
||||
if Mem_CmdRdy = '1' or r.Mem_CmdVld = '0' then
|
||||
v.State := Idle_s;
|
||||
v.Mem_CmdVld := '0';
|
||||
v.RspFifo_Vld := '1';
|
||||
v.RspFifo_Data.Size := std_logic_vector(r.RdBytes);
|
||||
-- Only mark as trigger if all samples are completely written to memory (no remaining samples in REM RAM)
|
||||
if (unsigned(r.RemWrBytes) = 0) and (r.Trigger = '1') then
|
||||
v.RspFifo_Data.Trigger := '1';
|
||||
else
|
||||
v.RspFifo_Data.Trigger := '0';
|
||||
end if;
|
||||
v.RspFifo_Data.Stream := r.HndlStream;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
-- *** Assign to signal ***
|
||||
r_next <= v;
|
||||
|
||||
end process;
|
||||
|
||||
-- *** Registered Outputs ***
|
||||
Mem_CmdAddr <= r.HndlAddress;
|
||||
Mem_CmdSize(r.RdBytes'range) <= std_logic_vector(r.RdBytes);
|
||||
Mem_CmdSize(Mem_CmdSize'high downto r.RdBytes'high+1) <= (others => '0');
|
||||
Mem_CmdVld <= r.Mem_CmdVld;
|
||||
DaqSm_HasLast <= r.HasLast;
|
||||
|
||||
|
||||
--------------------------------------------
|
||||
-- Sequential Process
|
||||
--------------------------------------------
|
||||
p_seq : process(Clk)
|
||||
begin
|
||||
if rising_edge(Clk) then
|
||||
r <= r_next;
|
||||
if Rst = '1' then
|
||||
r.CmdFifo_Rdy <= '0';
|
||||
r.RspFifo_Vld <= '0';
|
||||
r.Mem_DataVld <= '0';
|
||||
r.RemWen <= '0';
|
||||
r.State <= Idle_s;
|
||||
r.FirstDma <= (others => '1');
|
||||
r.Mem_CmdVld <= '0';
|
||||
r.HasLast <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------
|
||||
-- Component Instantiation
|
||||
--------------------------------------------
|
||||
-- *** Command FIFO ***
|
||||
CmdFifo_InData <= DaqSm2DaqDma_Cmd_ToStdlv(DaqSm_Cmd);
|
||||
i_fifocmd : entity work.psi_common_sync_fifo
|
||||
generic map (
|
||||
Width_g => DaqSm2DaqDma_Cmd_Size_c,
|
||||
Depth_g => 2**StreamBits_c,
|
||||
RamStyle_g => "distributed",
|
||||
RamBehavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
Clk => Clk,
|
||||
Rst => Rst,
|
||||
InData => CmdFifo_InData,
|
||||
InVld => DaqSm_Cmd_Vld,
|
||||
OutData => CmdFifo_OutData,
|
||||
OutVld => CmdFifo_Vld,
|
||||
OutRdy => r.CmdFifo_Rdy,
|
||||
OutLevel => CmdFifo_Level_Dbg
|
||||
);
|
||||
CmdFifo_Cmd <= DaqSm2DaqDma_Cmd_FromStdlv(CmdFifo_OutData);
|
||||
|
||||
-- *** Response FIFO ***
|
||||
-- Ready not required for system reasons: There is never more commands open than streams.
|
||||
RspFifo_InData <= DaqDma2DaqSm_Resp_ToStdlv(r.RspFifo_Data);
|
||||
i_fiforsp : entity work.psi_common_sync_fifo
|
||||
generic map (
|
||||
Width_g => DaqDma2DaqSm_Resp_Size_c,
|
||||
Depth_g => 2**StreamBits_c,
|
||||
RamStyle_g => "distributed",
|
||||
RamBehavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
Clk => Clk,
|
||||
Rst => Rst,
|
||||
InData => RspFifo_InData,
|
||||
InVld => r.RspFifo_Vld,
|
||||
OutData => RspFifo_OutData,
|
||||
OutVld => DaqSm_Resp_Vld,
|
||||
OutRdy => DaqSm_Resp_Rdy,
|
||||
OutLevel => RspFifo_Level_Dbg
|
||||
);
|
||||
DaqSm_Resp <= DaqDme2DaqSm_Resp_FromStdlv(RspFifo_OutData);
|
||||
|
||||
-- *** Buffer FIFO ***
|
||||
-- This FIFO allows buffering data for the time the state machine requires to react on a "memory interface not ready for more data" situation.
|
||||
-- As a result, the backpressure must not handled in the complete pipeline of this block.
|
||||
-- Rdy is not required since the data pipeline is stopped based on the almost full flag
|
||||
i_fifodata : entity work.psi_common_sync_fifo
|
||||
generic map (
|
||||
Width_g => 64,
|
||||
Depth_g => BufferFifoDepth_c,
|
||||
AlmFullOn_g => true,
|
||||
AlmFullLevel_g => BufferFifoDepth_c/2,
|
||||
RamStyle_g => "distributed",
|
||||
RamBehavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
Clk => Clk,
|
||||
Rst => Rst,
|
||||
InData => r.DataSft(63 downto 0),
|
||||
InVld => r.Mem_DataVld,
|
||||
OutData => Mem_DatData,
|
||||
OutVld => Mem_DatVld,
|
||||
OutRdy => Mem_DatRdy,
|
||||
OutLevel => DatFifo_Level_Dbg,
|
||||
AlmFull => DatFifo_AlmFull
|
||||
);
|
||||
|
||||
-- *** Remaining Data RAM ***
|
||||
i_remram : entity work.psi_common_sdp_ram
|
||||
generic map (
|
||||
Depth_g => 2**StreamBits_c,
|
||||
Width_g => 1+1+3+64,
|
||||
IsAsync_g => false,
|
||||
RamStyle_g => "distributed",
|
||||
Behavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
Clk => Clk,
|
||||
RdClk => Rst,
|
||||
WrAddr => r.StreamStdlv,
|
||||
Wr => r.RemWen,
|
||||
WrData(68) => r.RemWrLast,
|
||||
WrData(67) => r.RemWrTrigger,
|
||||
WrData(66 downto 64) => r.RemWrBytes,
|
||||
WrData(63 downto 0) => r.RemData,
|
||||
RdAddr => r.StreamStdlv,
|
||||
RdDAta(68) => Rem_Last,
|
||||
RdData(67) => Rem_Trigger,
|
||||
RdData(66 downto 64) => Rem_RdBytes,
|
||||
RdData(63 downto 0) => Rem_Data
|
||||
);
|
||||
|
||||
end;
|
||||
--------------------------------------------
|
||||
-- Combinatorial Process
|
||||
--------------------------------------------
|
||||
p_comb : process(r, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp_Rdy, Inp_Vld, Inp_Data, Mem_CmdRdy, Mem_DatRdy, CmdFifo_Cmd, CmdFifo_Vld, DatFifo_AlmFull, Rem_RdBytes, Rem_Data, Rem_Trigger, Rem_Last)
|
||||
variable v : two_process_r;
|
||||
variable ThisByte_v : std_logic_vector(7 downto 0);
|
||||
variable RemSft_v : integer range 0 to 7;
|
||||
begin
|
||||
-- *** Hold variables stable ***
|
||||
v := r;
|
||||
|
||||
-- *** Default Values ***
|
||||
v.CmdFifo_Rdy := '0';
|
||||
Inp_Rdy <= (others => '0');
|
||||
v.Mem_DataVld := '0';
|
||||
v.RspFifo_Vld := '0';
|
||||
v.RemWen := '0';
|
||||
v.UpdateLast := '0';
|
||||
|
||||
-- *** State Machine ***
|
||||
case r.State is
|
||||
|
||||
when Idle_s =>
|
||||
v.HndlMaxSize := unsigned(CmdFifo_Cmd.MaxSize);
|
||||
v.HndlStream := CmdFifo_Cmd.Stream;
|
||||
v.StreamStdlv := std_logic_vector(to_unsigned(CmdFifo_Cmd.Stream, v.StreamStdlv'length));
|
||||
v.HndlAddress := CmdFifo_Cmd.Address;
|
||||
v.Trigger := '0';
|
||||
v.Last := '0';
|
||||
if CmdFifo_Vld = '1' then
|
||||
v.CmdFifo_Rdy := '1';
|
||||
v.State := RemRd1_s;
|
||||
end if;
|
||||
|
||||
when RemRd1_s =>
|
||||
v.State := RemRd2_s;
|
||||
|
||||
when RemRd2_s =>
|
||||
-- Prevent RAM data from before reset to have an influence
|
||||
v.WrBytes := (others => '0');
|
||||
if r.FirstDma(r.HndlStream) = '1' then
|
||||
v.HndlSft := (others => '0');
|
||||
v.RdBytes := (others => '0');
|
||||
v.DataSft := (others => '0');
|
||||
v.RemTrigger := '0';
|
||||
v.RemLast := '0';
|
||||
else
|
||||
v.HndlSft := unsigned(Rem_RdBytes);
|
||||
v.DataSft(127 downto 64) := Rem_Data;
|
||||
v.RdBytes := resize(unsigned(Rem_RdBytes), v.RdBytes'length);
|
||||
v.RemTrigger := Rem_Trigger;
|
||||
v.RemLast := Rem_Last;
|
||||
end if;
|
||||
v.FirstDma(r.HndlStream) := '0';
|
||||
v.State := Transfer_s;
|
||||
v.NextDone := '0';
|
||||
v.DataWritten := '0';
|
||||
|
||||
when Transfer_s =>
|
||||
-- TF done because of maximum size reached
|
||||
if r.WrBytes >= r.HndlMaxSize then
|
||||
v.State := Done_s;
|
||||
elsif DatFifo_AlmFull = '0' then
|
||||
if r.NextDone = '0' and Inp_Vld(r.HndlStream) = '1' and r.RemLast = '0' then
|
||||
v.RdBytes := r.RdBytes + unsigned(Inp_Data(r.HndlStream).Bytes);
|
||||
end if;
|
||||
v.WrBytes := r.WrBytes + 8;
|
||||
-- Combinatorial handling because of fall-through interface at input
|
||||
if r.RdBytes < r.HndlMaxSize and r.NextDone = '0' and r.RemLast = '0' then
|
||||
Inp_Rdy(r.HndlStream) <= '1';
|
||||
end if;
|
||||
-- Handling of last frame
|
||||
if (Inp_Data(r.HndlStream).Last = '1') or (r.RemLast = '1') then
|
||||
-- Do one more word if not all data can be transferred in the current beat (NextDone = 1)
|
||||
if (r.HndlSft + unsigned(Inp_Data(r.HndlStream).Bytes) <= 8) or (r.RemLast = '1') then
|
||||
v.State := Done_s;
|
||||
else
|
||||
v.NextDone := '1';
|
||||
end if;
|
||||
if (Inp_Data(r.HndlStream).IsTrig = '1') or (r.RemTrigger = '1') then
|
||||
v.Trigger := '1';
|
||||
end if;
|
||||
v.Last := '1';
|
||||
end if;
|
||||
if r.NextDone = '1' or Inp_Vld(r.HndlStream) = '0' then
|
||||
v.State := Done_s;
|
||||
end if;
|
||||
-- Data handling
|
||||
v.DataSft(63 downto 0) := r.DataSft(127 downto 64);
|
||||
v.DataSft(8 * to_integer(r.HndlSft) + 63 downto 8 * to_integer(r.HndlSft)) := Inp_Data(r.HndlStream).Data;
|
||||
if Inp_Vld(r.HndlStream) = '1' or r.HndlSft /= 0 then
|
||||
v.Mem_DataVld := '1';
|
||||
v.DataWritten := '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when Done_s =>
|
||||
RemSft_v := to_integer(resize(r.HndlMaxSize, 3));
|
||||
v.RemWrTrigger := '0';
|
||||
v.RemWrLast := '0';
|
||||
if r.HndlMaxSize < r.RdBytes then
|
||||
v.RemWrBytes := std_logic_vector(resize(r.RdBytes - r.HndlMaxSize, v.RemWrBytes'length));
|
||||
v.RdBytes := r.HndlMaxSize;
|
||||
v.RemWrTrigger := r.Trigger;
|
||||
v.RemWrLast := r.Last;
|
||||
v.HasLast(r.HndlStream) := r.Last;
|
||||
else
|
||||
v.RemWrBytes := (others => '0');
|
||||
v.HasLast(r.HndlStream) := '0';
|
||||
end if;
|
||||
v.RemData := v.DataSft(8 * RemSft_v + 63 downto 8 * RemSft_v);
|
||||
v.State := Cmd_s;
|
||||
if r.DataWritten = '1' then
|
||||
v.Mem_CmdVld := '1';
|
||||
end if;
|
||||
v.RemWen := '1';
|
||||
|
||||
when Cmd_s =>
|
||||
if Mem_CmdRdy = '1' or r.Mem_CmdVld = '0' then
|
||||
v.State := Idle_s;
|
||||
v.Mem_CmdVld := '0';
|
||||
v.RspFifo_Vld := '1';
|
||||
v.RspFifo_Data.Size := std_logic_vector(r.RdBytes);
|
||||
-- Only mark as trigger if all samples are completely written to memory (no remaining samples in REM RAM)
|
||||
if (unsigned(r.RemWrBytes) = 0) and (r.Trigger = '1') then
|
||||
v.RspFifo_Data.Trigger := '1';
|
||||
else
|
||||
v.RspFifo_Data.Trigger := '0';
|
||||
end if;
|
||||
v.RspFifo_Data.Stream := r.HndlStream;
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
-- *** Assign to signal ***
|
||||
r_next <= v;
|
||||
|
||||
end process;
|
||||
|
||||
-- *** Registered Outputs ***
|
||||
Mem_CmdAddr <= r.HndlAddress;
|
||||
Mem_CmdSize(r.RdBytes'range) <= std_logic_vector(r.RdBytes);
|
||||
Mem_CmdSize(Mem_CmdSize'high downto r.RdBytes'high + 1) <= (others => '0');
|
||||
Mem_CmdVld <= r.Mem_CmdVld;
|
||||
DaqSm_HasLast <= r.HasLast;
|
||||
|
||||
--------------------------------------------
|
||||
-- Sequential Process
|
||||
--------------------------------------------
|
||||
p_seq : process(Clk)
|
||||
begin
|
||||
if rising_edge(Clk) then
|
||||
r <= r_next;
|
||||
if Rst = '1' then
|
||||
r.CmdFifo_Rdy <= '0';
|
||||
r.RspFifo_Vld <= '0';
|
||||
r.Mem_DataVld <= '0';
|
||||
r.RemWen <= '0';
|
||||
r.State <= Idle_s;
|
||||
r.FirstDma <= (others => '1');
|
||||
r.Mem_CmdVld <= '0';
|
||||
r.HasLast <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------
|
||||
-- Component Instantiation
|
||||
--------------------------------------------
|
||||
-- *** Command FIFO ***
|
||||
CmdFifo_InData <= DaqSm2DaqDma_Cmd_ToStdlv(DaqSm_Cmd);
|
||||
i_fifocmd : entity work.psi_common_sync_fifo
|
||||
generic map(
|
||||
width_g => DaqSm2DaqDma_Cmd_Size_c,
|
||||
depth_g => 2**StreamBits_c,
|
||||
ram_style_g => "distributed",
|
||||
ram_behavior_g => "RBW"
|
||||
)
|
||||
port map(
|
||||
clk_i => Clk,
|
||||
rst_i => Rst,
|
||||
dat_i => CmdFifo_InData,
|
||||
vld_i => DaqSm_Cmd_Vld,
|
||||
dat_o => CmdFifo_OutData,
|
||||
vld_o => CmdFifo_Vld,
|
||||
rdy_i => r.CmdFifo_Rdy,
|
||||
out_level_o => CmdFifo_Level_Dbg
|
||||
);
|
||||
CmdFifo_Cmd <= DaqSm2DaqDma_Cmd_FromStdlv(CmdFifo_OutData);
|
||||
|
||||
-- *** Response FIFO ***
|
||||
-- Ready not required for system reasons: There is never more commands open than streams.
|
||||
RspFifo_InData <= DaqDma2DaqSm_Resp_ToStdlv(r.RspFifo_Data);
|
||||
i_fiforsp : entity work.psi_common_sync_fifo
|
||||
generic map(
|
||||
width_g => DaqDma2DaqSm_Resp_Size_c,
|
||||
depth_g => 2**StreamBits_c,
|
||||
ram_style_g => "distributed",
|
||||
ram_behavior_g => "RBW"
|
||||
)
|
||||
port map(
|
||||
clk_i => Clk,
|
||||
rst_i => Rst,
|
||||
dat_i => RspFifo_InData,
|
||||
vld_i => r.RspFifo_Vld,
|
||||
dat_o => RspFifo_OutData,
|
||||
vld_o => DaqSm_Resp_Vld,
|
||||
rdy_i => DaqSm_Resp_Rdy,
|
||||
out_level_o => RspFifo_Level_Dbg
|
||||
);
|
||||
DaqSm_Resp <= DaqDme2DaqSm_Resp_FromStdlv(RspFifo_OutData);
|
||||
|
||||
-- *** Buffer FIFO ***
|
||||
-- This FIFO allows buffering data for the time the state machine requires to react on a "memory interface not ready for more data" situation.
|
||||
-- As a result, the backpressure must not handled in the complete pipeline of this block.
|
||||
-- Rdy is not required since the data pipeline is stopped based on the almost full flag
|
||||
i_fifodata : entity work.psi_common_sync_fifo
|
||||
generic map(
|
||||
width_g => 64,
|
||||
depth_g => BufferFifoDepth_c,
|
||||
alm_full_on_g => true,
|
||||
alm_full_level_g => BufferFifoDepth_c / 2,
|
||||
ram_style_g => "distributed",
|
||||
ram_behavior_g => "RBW"
|
||||
)
|
||||
port map(
|
||||
clk_i => Clk,
|
||||
rst_i => Rst,
|
||||
dat_i => r.DataSft(63 downto 0),
|
||||
vld_i => r.Mem_DataVld,
|
||||
dat_o => Mem_DatData,
|
||||
vld_o => Mem_DatVld,
|
||||
rdy_i => Mem_DatRdy,
|
||||
out_level_o => DatFifo_Level_Dbg,
|
||||
alm_full_o => DatFifo_AlmFull
|
||||
);
|
||||
|
||||
-- *** Remaining Data RAM ***
|
||||
i_remram : entity work.psi_common_sdp_ram
|
||||
generic map(
|
||||
depth_g => 2**StreamBits_c,
|
||||
width_g => 1 + 1 + 3 + 64,
|
||||
is_async_g => false,
|
||||
ram_style_g => "distributed",
|
||||
ram_behavior_g => "RBW"
|
||||
)
|
||||
port map(
|
||||
wr_clk_i => Clk,
|
||||
rd_clk_i => Rst,
|
||||
wr_addr_i => r.StreamStdlv,
|
||||
wr_i => r.RemWen,
|
||||
wr_dat_i(68) => r.RemWrLast,
|
||||
wr_dat_i(67) => r.RemWrTrigger,
|
||||
wr_dat_i(66 downto 64) => r.RemWrBytes,
|
||||
wr_dat_i(63 downto 0) => r.RemData,
|
||||
rd_addr_i => r.StreamStdlv,
|
||||
rd_dat_o(68) => Rem_Last,
|
||||
rd_dat_o(67) => Rem_Trigger,
|
||||
rd_dat_o(66 downto 64) => Rem_RdBytes,
|
||||
rd_dat_o(63 downto 0) => Rem_Data
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -8,157 +8,153 @@
|
||||
-- Libraries
|
||||
------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_math_pkg.all;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------------------------
|
||||
package psi_ms_daq_pkg is
|
||||
|
||||
constant MaxStreams_c : integer := 32;
|
||||
constant MaxWindows_c : integer := 32;
|
||||
constant MaxStreamsBits_c : integer := log2ceil(MaxStreams_c);
|
||||
constant MaxWindowsBits_c : integer := log2ceil(MaxWindows_c);
|
||||
constant MaxStreamWidth_c : integer := 64;
|
||||
|
||||
subtype RecMode_t is std_logic_vector(1 downto 0);
|
||||
constant RecMode_Continuous_c : RecMode_t := std_logic_vector(to_unsigned(0, RecMode_t'length));
|
||||
constant RecMode_TriggerMask_c : RecMode_t := std_logic_vector(to_unsigned(1, RecMode_t'length));
|
||||
constant RecMode_SingleShot_c : RecMode_t := std_logic_vector(to_unsigned(2, RecMode_t'length));
|
||||
constant RecMode_ManuelMode_c : RecMode_t := std_logic_vector(to_unsigned(3, RecMode_t'length));
|
||||
|
||||
subtype WinType_t is std_logic_vector(MaxWindowsBits_c-1 downto 0);
|
||||
type WinType_a is array (natural range <>) of WinType_t;
|
||||
|
||||
type Input2Daq_Data_t is record
|
||||
Last : std_logic;
|
||||
Data : std_logic_vector(63 downto 0);
|
||||
Bytes : std_logic_vector(3 downto 0);
|
||||
IsTo : std_logic;
|
||||
IsTrig : std_logic;
|
||||
end record;
|
||||
type Input2Daq_Data_a is array (natural range <>) of Input2Daq_Data_t;
|
||||
|
||||
type DaqSm2DaqDma_Cmd_t is record
|
||||
Address : std_logic_vector(31 downto 0);
|
||||
MaxSize : std_logic_vector(15 downto 0);
|
||||
Stream : integer range 0 to MaxStreams_c-1;
|
||||
end record;
|
||||
constant DaqSm2DaqDma_Cmd_Size_c : integer := 32+16+MaxStreamsBits_c;
|
||||
function DaqSm2DaqDma_Cmd_ToStdlv( rec : DaqSm2DaqDma_Cmd_t) return std_logic_vector;
|
||||
function DaqSm2DaqDma_Cmd_FromStdlv( stdlv : std_logic_vector) return DaqSm2DaqDma_Cmd_t;
|
||||
|
||||
type DaqDma2DaqSm_Resp_t is record
|
||||
Size : std_logic_vector(15 downto 0);
|
||||
Trigger : std_logic;
|
||||
Stream : integer range 0 to MaxStreams_c-1;
|
||||
end record;
|
||||
constant DaqDma2DaqSm_Resp_Size_c : integer := 16+1+MaxStreamsBits_c;
|
||||
function DaqDma2DaqSm_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector;
|
||||
function DaqDme2DaqSm_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t;
|
||||
|
||||
type ToCtxStr_t is record
|
||||
Stream : integer range 0 to MaxStreams_c-1;
|
||||
Sel : std_logic_vector(1 downto 0);
|
||||
Rd : std_logic;
|
||||
WenLo : std_logic;
|
||||
WenHi : std_logic;
|
||||
WdatLo : std_logic_vector(31 downto 0);
|
||||
WdatHi : std_logic_vector(31 downto 0);
|
||||
end record;
|
||||
constant CtxStr_Sel_ScfgBufstart_c : std_logic_vector(1 downto 0) := "00";
|
||||
constant CtxStr_Sel_WinsizePtr_c : std_logic_vector(1 downto 0) := "01";
|
||||
constant CtxStr_Sel_Winend_c : std_logic_vector(1 downto 0) := "10";
|
||||
constant CtxStr_Sft_SCFG_RINGBUF_c : integer := 0;
|
||||
constant CtxStr_Sft_SCFG_OVERWRITE_c : integer := 8;
|
||||
constant CtxStr_Sft_SCFG_WINCNT_c : integer := 16;
|
||||
constant CtxStr_Sft_SCFG_WINCUR_c : integer := 24;
|
||||
|
||||
type ToCtxWin_t is record
|
||||
Stream : integer range 0 to MaxStreams_c-1;
|
||||
Window : integer range 0 to MaxWindows_c-1;
|
||||
Sel : std_logic_vector(0 downto 0);
|
||||
Rd : std_logic;
|
||||
WenLo : std_logic;
|
||||
WenHi : std_logic;
|
||||
WdatLo : std_logic_vector(31 downto 0);
|
||||
WdatHi : std_logic_vector(31 downto 0);
|
||||
end record;
|
||||
constant CtxWin_Sel_WincntWinlast_c : std_logic_vector(0 downto 0) := "0";
|
||||
constant CtxWin_Sel_WinTs_c : std_logic_vector(0 downto 0) := "1";
|
||||
|
||||
type FromCtx_t is record
|
||||
RdatLo : std_logic_vector(31 downto 0);
|
||||
RdatHi : std_logic_vector(31 downto 0);
|
||||
end record;
|
||||
|
||||
type TmemRqst_t is record
|
||||
ADD : std_logic_vector(23 downto 0);
|
||||
DATW : std_logic_vector(63 downto 0);
|
||||
ENA : std_logic;
|
||||
WE : std_logic_vector(7 downto 0);
|
||||
CS : std_logic_vector(1 downto 0);
|
||||
end record;
|
||||
constant TmemRqst_init_c : TmemRqst_t := ((others => '0'), (others => '0'), '0', (others => '0'), (others => '0'));
|
||||
|
||||
type TmemResp_t is record
|
||||
DATR : std_logic_vector(63 downto 0);
|
||||
BUSY : std_logic;
|
||||
PIPE : std_logic_vector(1 downto 0);
|
||||
end record;
|
||||
|
||||
end psi_ms_daq_pkg;
|
||||
constant MaxStreams_c : integer := 32;
|
||||
constant MaxWindows_c : integer := 32;
|
||||
constant MaxStreamsBits_c : integer := log2ceil(MaxStreams_c);
|
||||
constant MaxWindowsBits_c : integer := log2ceil(MaxWindows_c);
|
||||
constant MaxStreamWidth_c : integer := 64;
|
||||
|
||||
subtype RecMode_t is std_logic_vector(1 downto 0);
|
||||
constant RecMode_Continuous_c : RecMode_t := std_logic_vector(to_unsigned(0, RecMode_t'length));
|
||||
constant RecMode_TriggerMask_c : RecMode_t := std_logic_vector(to_unsigned(1, RecMode_t'length));
|
||||
constant RecMode_SingleShot_c : RecMode_t := std_logic_vector(to_unsigned(2, RecMode_t'length));
|
||||
constant RecMode_ManuelMode_c : RecMode_t := std_logic_vector(to_unsigned(3, RecMode_t'length));
|
||||
|
||||
subtype WinType_t is std_logic_vector(MaxWindowsBits_c - 1 downto 0);
|
||||
type WinType_a is array (natural range <>) of WinType_t;
|
||||
|
||||
type Input2Daq_Data_t is record
|
||||
Last : std_logic;
|
||||
Data : std_logic_vector(63 downto 0);
|
||||
Bytes : std_logic_vector(3 downto 0);
|
||||
IsTo : std_logic;
|
||||
IsTrig : std_logic;
|
||||
end record;
|
||||
type Input2Daq_Data_a is array (natural range <>) of Input2Daq_Data_t;
|
||||
|
||||
type DaqSm2DaqDma_Cmd_t is record
|
||||
Address : std_logic_vector(31 downto 0);
|
||||
MaxSize : std_logic_vector(15 downto 0);
|
||||
Stream : integer range 0 to MaxStreams_c - 1;
|
||||
end record;
|
||||
constant DaqSm2DaqDma_Cmd_Size_c : integer := 32 + 16 + MaxStreamsBits_c;
|
||||
function DaqSm2DaqDma_Cmd_ToStdlv(rec : DaqSm2DaqDma_Cmd_t) return std_logic_vector;
|
||||
function DaqSm2DaqDma_Cmd_FromStdlv(stdlv : std_logic_vector) return DaqSm2DaqDma_Cmd_t;
|
||||
|
||||
type DaqDma2DaqSm_Resp_t is record
|
||||
Size : std_logic_vector(15 downto 0);
|
||||
Trigger : std_logic;
|
||||
Stream : integer range 0 to MaxStreams_c - 1;
|
||||
end record;
|
||||
constant DaqDma2DaqSm_Resp_Size_c : integer := 16 + 1 + MaxStreamsBits_c;
|
||||
function DaqDma2DaqSm_Resp_ToStdlv(rec : DaqDma2DaqSm_Resp_t) return std_logic_vector;
|
||||
function DaqDme2DaqSm_Resp_FromStdlv(stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t;
|
||||
|
||||
type ToCtxStr_t is record
|
||||
Stream : integer range 0 to MaxStreams_c - 1;
|
||||
Sel : std_logic_vector(1 downto 0);
|
||||
Rd : std_logic;
|
||||
WenLo : std_logic;
|
||||
WenHi : std_logic;
|
||||
WdatLo : std_logic_vector(31 downto 0);
|
||||
WdatHi : std_logic_vector(31 downto 0);
|
||||
end record;
|
||||
constant CtxStr_Sel_ScfgBufstart_c : std_logic_vector(1 downto 0) := "00";
|
||||
constant CtxStr_Sel_WinsizePtr_c : std_logic_vector(1 downto 0) := "01";
|
||||
constant CtxStr_Sel_Winend_c : std_logic_vector(1 downto 0) := "10";
|
||||
constant CtxStr_Sft_SCFG_RINGBUF_c : integer := 0;
|
||||
constant CtxStr_Sft_SCFG_OVERWRITE_c : integer := 8;
|
||||
constant CtxStr_Sft_SCFG_WINCNT_c : integer := 16;
|
||||
constant CtxStr_Sft_SCFG_WINCUR_c : integer := 24;
|
||||
|
||||
type ToCtxWin_t is record
|
||||
Stream : integer range 0 to MaxStreams_c - 1;
|
||||
Window : integer range 0 to MaxWindows_c - 1;
|
||||
Sel : std_logic_vector(0 downto 0);
|
||||
Rd : std_logic;
|
||||
WenLo : std_logic;
|
||||
WenHi : std_logic;
|
||||
WdatLo : std_logic_vector(31 downto 0);
|
||||
WdatHi : std_logic_vector(31 downto 0);
|
||||
end record;
|
||||
constant CtxWin_Sel_WincntWinlast_c : std_logic_vector(0 downto 0) := "0";
|
||||
constant CtxWin_Sel_WinTs_c : std_logic_vector(0 downto 0) := "1";
|
||||
|
||||
type FromCtx_t is record
|
||||
RdatLo : std_logic_vector(31 downto 0);
|
||||
RdatHi : std_logic_vector(31 downto 0);
|
||||
end record;
|
||||
|
||||
type TmemRqst_t is record
|
||||
ADD : std_logic_vector(23 downto 0);
|
||||
DATW : std_logic_vector(63 downto 0);
|
||||
ENA : std_logic;
|
||||
WE : std_logic_vector(7 downto 0);
|
||||
CS : std_logic_vector(1 downto 0);
|
||||
end record;
|
||||
constant TmemRqst_init_c : TmemRqst_t := ((others => '0'), (others => '0'), '0', (others => '0'), (others => '0'));
|
||||
|
||||
type TmemResp_t is record
|
||||
DATR : std_logic_vector(63 downto 0);
|
||||
BUSY : std_logic;
|
||||
PIPE : std_logic_vector(1 downto 0);
|
||||
end record;
|
||||
|
||||
end psi_ms_daq_pkg;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------------------------
|
||||
package body psi_ms_daq_pkg is
|
||||
|
||||
-- *** DaqSm2DaqDma_Cmd ***
|
||||
function DaqSm2DaqDma_Cmd_ToStdlv( rec : DaqSm2DaqDma_Cmd_t) return std_logic_vector is
|
||||
variable stdlv : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c-1 downto 0);
|
||||
begin
|
||||
stdlv(31 downto 0) := rec.Address;
|
||||
stdlv(47 downto 32) := rec.MaxSize;
|
||||
stdlv(stdlv'left downto 48) := std_logic_vector(to_unsigned(rec.Stream, MaxStreamsBits_c));
|
||||
return stdlv;
|
||||
end function;
|
||||
|
||||
function DaqSm2DaqDma_Cmd_FromStdlv( stdlv : std_logic_vector) return DaqSm2DaqDma_Cmd_t is
|
||||
variable rec : DaqSm2DaqDma_Cmd_t;
|
||||
begin
|
||||
rec.Address := stdlv(31 downto 0);
|
||||
rec.MaxSize := stdlv(47 downto 32);
|
||||
rec.Stream := to_integer(unsigned(stdlv(stdlv'left downto 48)));
|
||||
return rec;
|
||||
end function;
|
||||
|
||||
-- *** DaqDma2DaqSm_Resp ***
|
||||
function DaqDma2DaqSm_Resp_ToStdlv( rec : DaqDma2DaqSm_Resp_t) return std_logic_vector is
|
||||
variable stdlv : std_logic_vector(DaqDma2DaqSm_Resp_Size_c-1 downto 0);
|
||||
begin
|
||||
stdlv(15 downto 0) := rec.Size;
|
||||
stdlv(16) := rec.Trigger;
|
||||
stdlv(stdlv'left downto 17) := std_logic_vector(to_unsigned(rec.Stream, MaxStreamsBits_c));
|
||||
return stdlv;
|
||||
end function;
|
||||
|
||||
function DaqDme2DaqSm_Resp_FromStdlv( stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t is
|
||||
variable rec : DaqDma2DaqSm_Resp_t;
|
||||
begin
|
||||
rec.Size := stdlv(15 downto 0);
|
||||
rec.Trigger := stdlv(16);
|
||||
rec.Stream := to_integer(unsigned(stdlv(stdlv'left downto 17)));
|
||||
return rec;
|
||||
end function;
|
||||
|
||||
package body psi_ms_daq_pkg is
|
||||
|
||||
-- *** DaqSm2DaqDma_Cmd ***
|
||||
function DaqSm2DaqDma_Cmd_ToStdlv(rec : DaqSm2DaqDma_Cmd_t) return std_logic_vector is
|
||||
variable stdlv : std_logic_vector(DaqSm2DaqDma_Cmd_Size_c - 1 downto 0);
|
||||
begin
|
||||
stdlv(31 downto 0) := rec.Address;
|
||||
stdlv(47 downto 32) := rec.MaxSize;
|
||||
stdlv(stdlv'left downto 48) := std_logic_vector(to_unsigned(rec.Stream, MaxStreamsBits_c));
|
||||
return stdlv;
|
||||
end function;
|
||||
|
||||
function DaqSm2DaqDma_Cmd_FromStdlv(stdlv : std_logic_vector) return DaqSm2DaqDma_Cmd_t is
|
||||
variable rec : DaqSm2DaqDma_Cmd_t;
|
||||
begin
|
||||
rec.Address := stdlv(31 downto 0);
|
||||
rec.MaxSize := stdlv(47 downto 32);
|
||||
rec.Stream := to_integer(unsigned(stdlv(stdlv'left downto 48)));
|
||||
return rec;
|
||||
end function;
|
||||
|
||||
-- *** DaqDma2DaqSm_Resp ***
|
||||
function DaqDma2DaqSm_Resp_ToStdlv(rec : DaqDma2DaqSm_Resp_t) return std_logic_vector is
|
||||
variable stdlv : std_logic_vector(DaqDma2DaqSm_Resp_Size_c - 1 downto 0);
|
||||
begin
|
||||
stdlv(15 downto 0) := rec.Size;
|
||||
stdlv(16) := rec.Trigger;
|
||||
stdlv(stdlv'left downto 17) := std_logic_vector(to_unsigned(rec.Stream, MaxStreamsBits_c));
|
||||
return stdlv;
|
||||
end function;
|
||||
|
||||
function DaqDme2DaqSm_Resp_FromStdlv(stdlv : std_logic_vector) return DaqDma2DaqSm_Resp_t is
|
||||
variable rec : DaqDma2DaqSm_Resp_t;
|
||||
begin
|
||||
rec.Size := stdlv(15 downto 0);
|
||||
rec.Trigger := stdlv(16);
|
||||
rec.Stream := to_integer(unsigned(stdlv(stdlv'left downto 17)));
|
||||
return rec;
|
||||
end function;
|
||||
|
||||
end psi_ms_daq_pkg;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user