AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Made Project compiling using ISE

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This commit is contained in:
Oliver Bruendler
2018-08-31 15:39:35 +02:00
parent b2ff03c1db
commit e96dddc623
2 changed files with 12 additions and 8 deletions
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8
hdl/psi_ms_daq.vhd
View File

@ -156,10 +156,12 @@ begin
-- Input Logic Instantiation
--------------------------------------------
g_input : for str in 0 to Streams_g-1 generate
signal InRst : std_logic;
signal InRst : std_logic;
signal StrInput : std_logic_vector(StreamWidth_g(str)-1 downto 0);
begin
-- Reset if stream is disabled
InRst <= Rst or not Cfg_StrEna(str) or not Cfg_GlbEna;
InRst <= Rst or not Cfg_StrEna(str) or not Cfg_GlbEna;
StrInput <= Str_Data(str)(StrInput'range);
-- Instantiation
i_input : entity work.psi_ms_daq_input
@ -175,7 +177,7 @@ begin
Str_Clk => Str_Clk(str),
Str_Vld => Str_Vld(str),
Str_Rdy => Str_Rdy(str),
Str_Data => Str_Data(str),
Str_Data => StrInput,
Str_Trig => Str_Trig(str),
Str_Ts => Str_Ts(str),
Clk => Tosca_Clk,

12
hdl/psi_ms_daq_reg_tmem.vhd
View File

@ -261,7 +261,7 @@ begin
)
port map (
ClkA => ToscaClk,
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 4),
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 3),
WrA => CtxStr_WeLo,
DinA => TmemRqst.DATW(31 downto 0),
DoutA => CtxStr_Rdval(31 downto 0),
@ -280,7 +280,7 @@ begin
)
port map (
ClkA => ToscaClk,
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 4),
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 3),
WrA => CtxStr_WeHi,
DinA => TmemRqst.DATW(63 downto 32),
DoutA => CtxStr_Rdval(63 downto 32),
@ -296,7 +296,9 @@ begin
AddrCtxWin <= TmemRqst.ADD(23 downto 14) = X"00" & "01";
CtxWin_WeLo <= '1' when TmemRqst.WE(WeLow_c) = DwWrite_c and AddrCtxWin else '0';
CtxWin_WeHi <= '1' when TmemRqst.WE(WeHigh_c) = DwWrite_c and AddrCtxWin else '0';
CtxWin_AddrB <= std_logic_vector(to_unsigned(CtxWin_Cmd.Stream, log2ceil(Streams_g))) & CtxWin_Cmd.Sel;
CtxWin_AddrB <= std_logic_vector(to_unsigned(CtxWin_Cmd.Stream, log2ceil(Streams_g))) &
std_logic_vector(to_unsigned(CtxWin_Cmd.Window, log2ceil(MaxWindows_g))) &
CtxWin_Cmd.Sel;
-- Low DWORD memory
i_mem_win_lo : entity work.psi_common_tdp_ram_rbw
@ -306,7 +308,7 @@ begin
)
port map (
ClkA => ToscaClk,
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 4),
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 3),
WrA => CtxWin_WeLo,
DinA => TmemRqst.DATW(31 downto 0),
DoutA => CtxWin_Rdval(31 downto 0),
@ -325,7 +327,7 @@ begin
)
port map (
ClkA => ToscaClk,
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 4),
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 3),
WrA => CtxWin_WeHi,
DinA => TmemRqst.DATW(63 downto 32),
DoutA => CtxWin_Rdval(63 downto 32),