DEVEL: Work on top level TB

hdl/psi_ms_daq_pkg.vhd

@@ -92,6 +92,7 @@ package psi_ms_daq_pkg is
 		WE 			: std_logic_vector(7 downto 0);
 		CS			: std_logic_vector(1 downto 0);
 	end record;
+	constant TmemRqst_init_c : TmemRqst_t	:= ((others => '0'), (others => '0'), '0', (others => '0'), (others => '0'));
 	
 	type TmemResp_t is record
 		DATR 		: std_logic_vector(63 downto 0);

sim/config.tcl

@@ -71,6 +71,7 @@ add_sources "../tb" {
 	psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_cmd_full.vhd \
 	psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd \
 	psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd \
+	psi_ms_daq/psi_ms_daq_tb.vhd \
 } -tag tb
 	
 #TB Runs

tb/psi_ms_daq/psi_ms_daq_tb.vhd

@@ -0,0 +1,187 @@
+------------------------------------------------------------
+-- Testbench generated by TbGen.py
+------------------------------------------------------------
+-- see Library/Python/TbGenerator
+
+------------------------------------------------------------
+-- Libraries
+------------------------------------------------------------
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+library work;
+	use work.psi_common_math_pkg.all;
+	use work.psi_common_array_pkg.all;
+	use work.psi_ms_daq_pkg.all;
+
+library work;
+	use work.psi_tb_txt_util.all;
+	use work.psi_tb_compare_pkg.all;
+	use work.smem_master_types_pkg.all;
+
+
+------------------------------------------------------------
+-- Entity Declaration
+------------------------------------------------------------
+entity psi_ms_daq_tb is
+end entity;
+
+------------------------------------------------------------
+-- Architecture
+------------------------------------------------------------
+architecture sim of psi_ms_daq_tb is
+
+	-- TB Control
+	signal TbRunning 	: boolean := true;
+
+	-- Constants
+	constant StrCount_c	: integer	:= 4;
+	constant ClkFreq_c	: t_areal	:= (0=>250.0e6,	1=>125.0e-6,	2=>80.0e-6,	3=>200.0e-6);
+	constant MemSize_c	: integer	:= 2**16;
+
+	-- Port signals
+	signal Str_Clk		: std_logic_vector(StrCount_c-1 downto 0)	:= (others => '0');
+	signal Str0_Data	: std_logic_vector(7 downto 0)				:= (others => '0');
+	signal Str1_Data	: std_logic_vector(15 downto 0)				:= (others => '0');
+	signal Str2_Data	: std_logic_vector(15 downto 0)				:= (others => '0');
+	signal Str3_Data	: std_logic_vector(31 downto 0)				:= (others => '0');
+	signal Timestamp	: t_aslv64(StrCount_c-1 downto 0)			:= (others => (others => '0'));
+	signal Str_Vld		: std_logic_vector(StrCount_c-1 downto 0)	:= (others => '0');
+	signal Str_Rdy		: std_logic_vector(StrCount_c-1 downto 0)	:= (others => '0');
+	signal Str_Trig		: std_logic_vector(StrCount_c-1 downto 0)	:= (others => '0');
+	signal Tosca_Clk	: std_logic									:= '0';
+	signal Tmem_Rst		: std_logic									:= '1';
+	signal Smem_Rst		: std_logic									:= '1';
+	signal TmemAcq		: TmemRqst_t								:= TmemRqst_init_c;
+	signal AcqTmem		: TmemResp_t;
+	signal SmemAcq		: FromSmemWr_t								:= (others => (others => '0'));
+	signal AcqSmem		: ToSmemWr_t;
+	signal Irq			: std_logic									:= '0';
+	
+	-- Memory
+	shared variable Memory_v : t_aslv8(0 to MemSize_c-1);
+	
+begin
+	------------------------------------------------------------
+	-- DUT Instantiation
+	------------------------------------------------------------
+	i_dut : entity work.psi_ms_daq
+		generic map (
+			Streams_g				=> StrCount_c,
+			StreamWidth_g			=> (0=>8, 		1=>16, 			2=>16, 		3=>32),
+			StreamPrio_g			=> (0=>1, 		1=>3,  			2=>2,  		3=>2),
+			StreamBuffer_g			=> (0=>32, 		1=>128, 		2=>128, 	3=>128),
+			StreamTimeout_g			=> (0=>5.0e-6,	1=>1.0e-3,		2=>1.0e-3,	3=>1.0e-3),
+			StreamClkFreq_g			=> ClkFreq_c,
+			StreamTsFifoDepth_g		=> (0=>16,		1=>16,			2=>16,		3=>16),
+			StreamUseTs_g			=> (0=>true,	1=>true,		2=>true,	3=>false),
+			MaxWindows_g			=> 16,
+			MinBurstSize_g			=> 16,
+			MaxBurstSize_g			=> 128
+		)
+		port map (
+			Str_Clk						=> Str_Clk,
+			Str_Data(0)(7 downto 0)		=> Str0_Data,
+			Str_Data(0)(63 downto 8)	=> (others => '0'),
+			Str_Data(1)(15 downto 0)	=> Str1_Data,
+			Str_Data(1)(63 downto 16)	=> (others => '0'),
+			Str_Data(2)(15 downto 0)	=> Str2_Data,
+			Str_Data(2)(63 downto 16)	=> (others => '0'),
+			Str_Data(3)(31 downto 0)	=> Str3_Data,
+			Str_Data(3)(63 downto 32)	=> (others => '0'),
+			Str_Ts						=> Timestamp,
+			Str_Vld						=> Str_Vld,
+			Str_Rdy						=> Str_Rdy,
+			Str_Trig					=> Str_Trig,
+			Tosca_Clk					=> Tosca_Clk,
+			Tmem_Rst					=> Tmem_Rst,
+			Smem_Rst					=> Smem_Rst,
+			TmemAcq						=> TmemAcq,
+			AcqTmem						=> AcqTmem,
+			AcqSmem						=> AcqSmem,
+			SmemAcq						=> SmemAcq,
+			Irq							=> Irq
+		);
+		
+	------------------------------------------------------------
+	-- Emulate Memory
+	------------------------------------------------------------	
+	p_mem : process
+		variable Address_v		: integer;
+		variable Size_v			: integer;
+	begin
+		while TbRunning loop
+			wait until (rising_edge(Tosca_Clk) and AcqSmem.WREQ = SMEM_REQ_Request_c) or (not TbRunning);
+			if TbRunning then
+				wait until rising_edge(Tosca_Clk);
+				Address_v	:= to_integer(unsigned(AcqSmem.WADD));
+				Size_v		:= to_integer(unsigned(AcqSmem.WSIZ));
+				SmemAcq.WACK <= SMEM_ACK_Grant_c;
+				wait until rising_edge(Tosca_Clk);
+				SmemAcq.WACK <= SMEM_ACK_Burst_c;	
+				wait until rising_edge(Tosca_Clk);	
+				wait until rising_edge(Tosca_Clk);
+				wait until rising_edge(Tosca_Clk);
+				for qw in 0 to Size_v-1 loop
+					if qw = Size_v-1 then
+						SmemAcq.WACK <= SMEM_ACK_Done_c;
+					end if;
+					wait until rising_edge(Tosca_Clk);
+					for byte in 0 to 7 loop
+						if AcqSmem.WBE(byte) = '1' then
+							Memory_v(Address_v+qw*8+byte) := AcqSmem.WDAT(byte*8+7 downto byte*8);
+						end if;
+					end loop;
+				end loop;
+				SmemAcq.WACK <= SMEM_ACK_Idle_c;
+				wait until rising_edge(Tosca_Clk);				
+			end if;
+		end loop;
+		wait;			
+	end process;
+	
+	------------------------------------------------------------
+	-- Clocks 
+	------------------------------------------------------------	
+	
+	p_clk_tosca : process
+		constant Frequency_c : real := real(200e6);
+	begin
+		while TbRunning loop
+			wait for 0.5*(1 sec)/Frequency_c;
+			Tosca_Clk <= not Tosca_Clk;
+		end loop;
+		wait;
+	end process;
+	
+	g_clk_str : for i in 0 to StrCount_c-1 generate
+		p_clk_str : process
+		begin
+			while TbRunning loop
+				wait for 0.5*(1 sec)/(ClkFreq_c(i)+0.1e6);
+				Tosca_Clk <= not Tosca_Clk;
+			end loop;
+			wait;				
+		end process;
+	end generate;
+
+	------------------------------------------------------------
+	-- TBD
+	------------------------------------------------------------
+	-- No influence when disabled
+	-- Disable / re-enable
+		
+	------------------------------------------------------------
+	-- TMEM Process
+	------------------------------------------------------------
+	
+	------------------------------------------------------------
+	-- Data Generation Processes
+	------------------------------------------------------------	
+	
+	------------------------------------------------------------
+	-- Check Process
+	------------------------------------------------------------	
+	
+end;