AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

DEVEL: Top-Level Compiles

Browse Source
This commit is contained in:
Oliver Bruendler
2018-08-31 10:57:23 +02:00
parent 46bc02e36f
commit b64efa1f22
4 changed files with 38 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
hdl/psi_ms_daq.vhd
View File

@ -21,10 +21,10 @@ entity psi_ms_daq is
StreamWidth_g : t_ainteger := (16, 16);
StreamPrio_g : t_ainteger := (1, 1);
StreamBuffer_g : t_ainteger := (1024, 1024);
StreamTimout_g : t_areal := (1.0e-3, 1.0e-3);
StreamTimeout_g : t_areal := (1.0e-3, 1.0e-3);
StreamClkFreq_g : t_areal := (100.0e6, 100.0e6);
StreamTsFifoDepth_g : t_ainteger := (16, 16);
StreamUseTs_g : t_aboolean := (true, true);
StreamUseTs_g : t_abool := (true, true);
MaxWindows_g : positive range 1 to 32 := 16;
MinBurstSize_g : integer := 512;
MaxBurstSize_g : integer := 512
@ -68,7 +68,7 @@ architecture rtl of psi_ms_daq is
signal InpSm_HasTlast : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_TsVld : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_TsRdy : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_Level : t_aslv16/Streams_g-1 downto 0);
signal InpSm_Level : t_aslv16(Streams_g-1 downto 0);
signal InpSm_TsData : t_aslv64(Streams_g-1 downto 0);
-- Statemachine/Dma
@ -129,7 +129,8 @@ begin
--------------------------------------------
i_reg : entity work.psi_ms_daq_reg_tmem
generic map (
Streams_g => Streams_g
Streams_g => Streams_g,
MaxWindows_g => MaxWindows_g
)
port map (
ToscaClk => Tosca_Clk,
@ -280,8 +281,8 @@ begin
Dat_Vld => DmaMem_DatVld,
Dat_Rdy => DmaMem_DatRdy,
Done => MemSm_Done,
ToSmem => ToSmem,
FromSmem => FromSmem
ToSmem => AcqSmem,
FromSmem => SmemAcq
);
end;

4
hdl/psi_ms_daq_pkg.vhd
View File

@ -88,10 +88,10 @@ package psi_ms_daq_pkg is
type TmemRqst_t is record
ADD : std_logic_vector(23 downto 0);
DATW : std_logic_vector(63 downto 0);
ENA ; std_logic;
ENA : std_logic;
WE : std_logic_vector(7 downto 0);
CS : std_logic_vector(1 downto 0);
end reord;
end record;
type TmemResp_t is record
DATR : std_logic_vector(63 downto 0);

46
hdl/psi_ms_daq_reg_tmem.vhd
View File

@ -7,7 +7,9 @@
library work;
use work.psi_common_math_pkg.all;
use work.psi_fix_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_ms_daq_pkg.all;
------------------------------------------------------------------------------
-- Entity Declaration
@ -16,7 +18,7 @@ entity psi_ms_daq_reg_tmem is
generic (
Streams_g : in integer range 1 to 32;
MaxWindows_g : in integer range 1 to 32
)
);
port (
-- control Ports
ToscaClk : in std_logic;
@ -73,7 +75,7 @@ architecture rtl of psi_ms_daq_reg_tmem is
signal CtxStr_WeLo : std_logic;
signal CtxStr_WeHi : std_logic;
signal CtxStr_Rdval : std_logic_vector(63 downto 0);
signal CtxStr_AddrB : std_logic_vector(log2ceil(DepthCtxStr_c-1 downto 0);
signal CtxStr_AddrB : std_logic_vector(log2ceil(DepthCtxStr_c)-1 downto 0);
signal AddrCtxStr : boolean;
constant DepthCtxWin_c : integer := Streams_g*MaxWindows_g*16/8;
@ -81,7 +83,7 @@ architecture rtl of psi_ms_daq_reg_tmem is
signal CtxWin_WeLo : std_logic;
signal CtxWin_WeHi : std_logic;
signal CtxWin_Rdval : std_logic_vector(63 downto 0);
signal CtxWin_AddrB : std_logic_vector(log2ceil(DepthCtxWin_c-1 downto 0);
signal CtxWin_AddrB : std_logic_vector(log2ceil(DepthCtxWin_c)-1 downto 0);
signal AddrCtxWin : boolean;
begin
--------------------------------------------
@ -108,10 +110,10 @@ begin
-- GCFG / GSTAT
when X"000000" =>
-- GCFG
if Rqst.WE(0) = '1' then
if TmemRqst.WE(0) = '1' then
v.Reg_Gcfg_Ena := TmemRqst.DATW(0);
end if;
if Rqst.WE(1) = '1' then
if TmemRqst.WE(1) = '1' then
v.Reg_Gcfg_Ena := TmemRqst.DATW(8);
end if;
v.RegRdval(0) := r.Reg_Gcfg_Ena;
@ -120,12 +122,12 @@ begin
-- IRQVEC / IRQENA
when X"000010" =>
-- IRQVEC
if Rqst.WE(WeLow_c) = DwWrite_c then
v.Reg_IrqVec := r.IrqVec and (not TmemRqst.DATW(Streams_g-1 downto 0));
if TmemRqst.WE(WeLow_c) = DwWrite_c then
v.Reg_IrqVec := r.Reg_IrqVec and (not TmemRqst.DATW(Streams_g-1 downto 0));
end if;
v.RegRdval(Streams_g-1 downto 0) := r.Reg_IrqVec;
-- IRQENA
if Rqst.WE(WeHigh_c) = DwWrite_c then
if TmemRqst.WE(WeHigh_c) = DwWrite_c then
v.Reg_IrqEna := TmemRqst.DATW(Streams_g+32-1 downto 32);
end if;
v.RegRdval(Streams_g+32-1 downto 32) := r.Reg_IrqEna;
@ -133,7 +135,7 @@ begin
-- STRENA
when X"000020" =>
-- STRENA
if Rqst.WE(WeLow_c) = DwWrite_c then
if TmemRqst.WE(WeLow_c) = DwWrite_c then
v.Reg_StrEna := TmemRqst.DATW(Streams_g-1 downto 0);
end if;
v.RegRdval(Streams_g-1 downto 0) := r.Reg_StrEna;
@ -144,19 +146,19 @@ begin
end case;
-- *** Stream Register Accesses ***
v.Reg_Mode_Arm <= (others => '0');
v.Reg_Mode_Arm := (others => '0');
if TmemRqst.ADD(23 downto 9) = X"000" & "001" then
Stream_v := to_integer(unsigned(TmemRqst.ADD(8 downto 4)));
-- MAXLVLn / POSTTRIGn
if TmemRqst.ADD(3 downto 0) = X"0" then
-- MAXLVLn
if Rqst.WE(WeLow_c) = DwWrite_c then
if TmemRqst.WE(WeLow_c) = DwWrite_c then
v.Reg_MaxLvl(Stream_v) := (others => '0');
end if;
v.RegRdval(15 downto 0) := r.Reg_MaxLvl(Stream_v);
-- POSTTRIGn
if Rqst.WE(WeHigh_c) = DwWrite_c then
if TmemRqst.WE(WeHigh_c) = DwWrite_c then
v.Reg_PostTrig(Stream_v) := TmemRqst.DATW(63 downto 32);
end if;
v.RegRdval(63 downto 32) := r.Reg_PostTrig(Stream_v);
@ -165,10 +167,10 @@ begin
-- MODEn
if TmemRqst.ADD(3 downto 0) = X"8" then
-- MODEn
if Rqst.WE(0) = '1' then
if TmemRqst.WE(0) = '1' then
v.Reg_Mode_Recm(Stream_v) := TmemRqst.DATW(1 downto 0);
end if;
if Rqst.WE(1) = '1' then
if TmemRqst.WE(1) = '1' then
v.Reg_Mode_Arm(Stream_v) := TmemRqst.DATW(8);
end if;
v.RegRdval(1 downto 0) := r.Reg_Mode_Recm(Stream_v);
@ -186,15 +188,15 @@ begin
v.RdVal := CtxStr_Rdval;
elsif r.AddrReg(23 downto 14) = X"00" & "01" then
v.RdVal := CtxWin_Rdval;
end case;
end if;
-- *** IRQ Handling ***
for i in 0 to Streams_g-1 loop
if StrIrq(i) = '1' then
v.Reg_IrqVec(i) := '1';
end if;
end if;
if (r.Reg_IrqVec and r.Reg_IrqEna /= ZerosVector(Streams_g)) and (r.Reg_Gcfg_IrqEna = '1') then
end loop;
if ((r.Reg_IrqVec and r.Reg_IrqEna) /= ZerosVector(Streams_g)) and (r.Reg_Gcfg_IrqEna = '1') then
v.Irq := '1';
else
v.Irq := '0';
@ -247,8 +249,8 @@ begin
-- *** Stream Context Memory ***
-- Signal Assembly
AddrCtxStr <= TmemRqst.ADD(23 downto 12) = X"001";
CtxStr_WeLo <= '1' when Rqst.WE(WeLow_c) = DwWrite_c and AddrCtxStr else '0';
CtxStr_WeHi <= '1' when Rqst.WE(WeHigh_c) = DwWrite_c and AddrCtxStr else '0';
CtxStr_WeLo <= '1' when TmemRqst.WE(WeLow_c) = DwWrite_c and AddrCtxStr else '0';
CtxStr_WeHi <= '1' when TmemRqst.WE(WeHigh_c) = DwWrite_c and AddrCtxStr else '0';
CtxStr_AddrB <= std_logic_vector(to_unsigned(CtxStr_Cmd.Stream, log2ceil(Streams_g))) & CtxStr_Cmd.Sel;
-- Low DWORD memory
@ -292,8 +294,8 @@ begin
-- *** Window Context Memory ***
-- Signal Assembly
AddrCtxWin <= TmemRqst.ADD(23 downto 14) = X"00" & "01";
CtxWin_WeLo <= '1' when Rqst.WE(WeLow_c) = DwWrite_c and AddrCtxWin else '0';
CtxWin_WeHi <= '1' when Rqst.WE(WeHigh_c) = DwWrite_c and AddrCtxWin else '0';
CtxWin_WeLo <= '1' when TmemRqst.WE(WeLow_c) = DwWrite_c and AddrCtxWin else '0';
CtxWin_WeHi <= '1' when TmemRqst.WE(WeHigh_c) = DwWrite_c and AddrCtxWin else '0';
CtxWin_AddrB <= std_logic_vector(to_unsigned(CtxWin_Cmd.Stream, log2ceil(Streams_g))) & CtxWin_Cmd.Sel;
-- Low DWORD memory

5
sim/config.tcl
View File

@ -26,6 +26,9 @@ add_sources $LibPath {
psi_common/hdl/psi_common_async_fifo.vhd \
psi_common/hdl/psi_common_arb_priority.vhd \
psi_common/hdl/psi_common_sync_fifo.vhd \
psi_common/hdl/psi_common_tdp_ram_rbw.vhd \
../../BoardSupport/IFC1210/smem_master/hdl/smem_master_types_pkg.vhd \
../../BoardSupport/IFC1210/smem_master/hdl/smem_master_write.vhd \
} -tag lib
# project sources
@ -34,6 +37,8 @@ add_sources "../hdl" {
psi_ms_daq_input.vhd \
psi_ms_daq_daq_sm.vhd \
psi_ms_daq_daq_dma.vhd \
psi_ms_daq_reg_tmem.vhd \
psi_ms_daq.vhd \
} -tag src
# testbenches