AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Added stream 1 to top level TB

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This commit is contained in:
Oliver Bruendler
2018-09-04 09:07:10 +02:00
parent 7b0dc7eb45
commit 8c925be1f8
4 changed files with 155 additions and 3 deletions
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1
sim/config.tcl
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@ -74,6 +74,7 @@ add_sources "../tb" {
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd \
psi_ms_daq/psi_ms_daq_tb_pkg.vhd \
psi_ms_daq/psi_ms_daq_tb_str0_pkg.vhd \
psi_ms_daq/psi_ms_daq_tb_str1_pkg.vhd \
psi_ms_daq/psi_ms_daq_tb.vhd \
} -tag tb

25
tb/psi_ms_daq/psi_ms_daq_tb.vhd
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@ -21,6 +21,7 @@ library work;
use work.smem_master_types_pkg.all;
use work.psi_ms_daq_tb_pkg.all;
use work.psi_ms_daq_tb_str0_pkg.all;
use work.psi_ms_daq_tb_str1_pkg.all;
------------------------------------------------------------
@ -77,6 +78,7 @@ architecture sim of psi_ms_daq_tb is
if slv(i) = '1' then
case i is
when 0 => Str0Handler(clk, rqst, rsp);
when 1 => Str1Handler(clk, rqst, rsp);
when others => null;
end case;
end if;
@ -205,6 +207,7 @@ begin
------------------------------------------------------------
p_tmem : process
variable StartTime_v : time;
variable Stream1Armed_v : boolean := false;
begin
wait for 1 us;
Tmem_Rst <= '0';
@ -221,17 +224,32 @@ begin
TmemWriteAndRead32(16#1000#, 16#00020001#, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#1004#, 16#1000#, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#1008#, 100, Tosca_Clk, TmemAcq, AcqTmem);
-- Stream 1 (Single Shot, linear, 1 window, 0x2000-0x3000)
TmemExpect32(16#0210#, 0, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#0214#, 250, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#0218#, 16#0003#, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#1020#, 16#00000000#, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#1024#, 16#2000#, Tosca_Clk, TmemAcq, AcqTmem);
TmemWriteAndRead32(16#1028#, 500, Tosca_Clk, TmemAcq, AcqTmem);
-- Enable
TmemWriteAndRead32(16#0000#, 16#0101#, Tosca_Clk, TmemAcq, AcqTmem);
-- *** Run Test ***
StartTime_v := now;
while now < StartTime_v+100 us loop
wait until rising_edge(Tosca_Clk);
-- IRQ Handling
if Irq = '1' then
IrqHandler(Tosca_Clk, TmemAcq, AcqTmem);
end if;
-- ARM Stream 1 after 100 samples
if unsigned(Str1_Data) = 99 and not Stream1Armed_v then
Stream1Armed_v := true;
TmemWrite32(16#0218#, 16#0103#, Tosca_Clk, TmemAcq, AcqTmem);
end if;
end loop;
TbRunning <= false;
@ -264,6 +282,13 @@ begin
while TbRunning loop
Str0Sample(Str_Clk(0), Str_Vld(0), Str_Trig(0), Str0_Data);
end loop;
wait;
end process;
p_str1 : process
begin
Str1Data(Str_Clk(1), Str_Vld(1), Str_Trig(1), Str1_Data);
wait;
end process;
------------------------------------------------------------

6
tb/psi_ms_daq/psi_ms_daq_tb_str0_pkg.vhd
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@ -129,14 +129,15 @@ package body psi_ms_daq_tb_str0_pkg is
-- Windows full because dat received for quite some time
IntCompare(100, wincnt, "WINCNT wrong");
-- Check Values
addr := winlast + 1;
addr := winlast;
for i in 256+30+3-99 to 256+30+3 loop
StdlvCompareInt (i mod 256, Memory(addr), "Wrong value", false);
if addr = winend then
addr := winstart;
else
addr := addr + 1;
end if;
StdlvCompareInt (i mod 256, Memory(addr), "Wrong value at 0x" & to_hstring(to_unsigned(addr,32)), false);
end loop;
when 1 =>
@ -153,7 +154,6 @@ package body psi_ms_daq_tb_str0_pkg is
when 2 =>
-- Trigger following each other with 30 samples difference
IntCompare(30, wincnt, "WINCNT wrong");
print(to_string(tslo) & " " & to_string(Str0LastTs));
IntCompare(30*2, tslo-Str0LastTs, "TS difference wrong");
-- Check Values
addr := winstart;

126
tb/psi_ms_daq/psi_ms_daq_tb_str1_pkg.vhd Normal file
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@ -0,0 +1,126 @@
------------------------------------------------------------
-- Description
------------------------------------------------------------
-- Stream 1 works in manual recording mode. The data is arriving
-- in bursts (samples back-to-back withing bursts) and does
-- not contain any trigger events.
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_ms_daq_tb_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_tb_str1_pkg is
-- Memory
alias Memory1 : t_aslv8(0 to 16#0FFF#) is Memory(16#2000# to 16#2FFF#);
--------------------------------------------------------
-- Persistent State
--------------------------------------------------------
shared variable Str1NextWin : integer := 0;
shared variable Str1WinCheck : integer := 0;
shared variable Str1LastTs : integer;
shared variable Str1IrqOn : boolean := false;
--------------------------------------------------------
-- Data Generation
--------------------------------------------------------
procedure Str1Data( signal clk : in std_logic;
signal vld : out std_logic;
signal trig : out std_logic;
signal data : out std_logic_vector(15 downto 0));
--------------------------------------------------------
-- IRQ Handler
--------------------------------------------------------
procedure Str1Handler( signal clk : in std_logic;
signal rqst : out TmemRqst_t;
signal rsp : in TmemResp_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_tb_str1_pkg is
--------------------------------------------------------
-- Data Generation
--------------------------------------------------------
procedure Str1Data( signal clk : in std_logic;
signal vld : out std_logic;
signal trig : out std_logic;
signal data : out std_logic_vector(15 downto 0)) is
variable cnt : integer := 0;
begin
while now < 10 us loop
wait until rising_edge(clk);
end loop;
for i in 0 to 19 loop
vld <= '1';
for k in 0 to 49 loop
data <= std_logic_vector(to_unsigned(cnt, 16));
cnt := cnt + 1;
wait until rising_edge(clk);
end loop;
vld <= '0';
wait for 1 us;
wait until rising_edge(clk);
end loop;
end procedure;
--------------------------------------------------------
-- IRQ Handler
--------------------------------------------------------
procedure Str1Handler( signal clk : in std_logic;
signal rqst : out TmemRqst_t;
signal rsp : in TmemResp_t) is
variable v : integer;
variable curwin : integer;
variable wincnt : integer;
variable winlast : integer;
variable valRead : unsigned(15 downto 0);
begin
print("------------ Stream 1 Handler ------------");
TmemRead32(16#0210#, v, clk, rqst, rsp);
print("MAXLVL: " & to_string(v));
TmemRead32(16#102C#, v, clk, rqst, rsp);
print("PTR: " & to_string(v));
TmemRead32(16#1020#, v, clk, rqst, rsp);
curwin := v/(2**24);
print("CURWIN: " & to_string(curwin));
IntCompare(0, curwin, "CURWIN wrong");
-- Check window content
TmemRead32(16#4100#, wincnt, clk, rqst, rsp);
print("WINCNT: " & to_string(wincnt));
IntCompare(250, wincnt, "WINCNT wrong");
TmemRead32(16#4104#, winlast, clk, rqst, rsp);
print("WINLAST: " & to_string(winlast));
IntCompare(16#2000#+498, winlast, "WINLAST wrong");
for spl in 0 to 249 loop
valRead(7 downto 0) := unsigned(Memory1(spl*2));
valRead(15 downto 8) := unsigned(Memory1(spl*2+1));
-- first 100 samples are before arming
StdlvCompareInt (spl+100, std_logic_vector(valRead), "Wrong value", false);
end loop;
print("");
end procedure;
end;