DEVEL: Moved Tosca component to separate repository
This commit is contained in:
Oliver Bruendler
@ -1,3 +1,7 @@
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## 0.9.0
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* Added AXI version
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* Moved Tosca version to separate repo
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## 0.2.0
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* Updated according to new library versions after open sourcing
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@ -19,15 +19,12 @@ See [Changelog](Changelog.md)
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# Dependencies
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## Library
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Directory structure as given below
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* BoardSupport
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* IFC1210
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* [smem\_master](https://git.psi.ch/GFA/Libraries/BoardSupport/IFC1210/smem_master) (not released yet)
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* Firmware
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* TCL
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* [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) (2.0.0 or higher, for development only)
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* [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) (2.1.0 or higher, for development only)
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* VHDL
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* [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (2.0.0 or higher)
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* [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (2.0.0 or higher, for development only)
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* [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (2.4.0 or higher)
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* [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (2.2.1 or higher, for development only)
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* [**psi\_multi\_stream\_daq**](https://git.psi.ch/GFA/Libraries/Firmware/VHDL/psi_multi_stream_daq)
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## External
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@ -8,8 +8,7 @@ library ieee;
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library work;
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use work.psi_common_math_pkg.all;
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use work.smem_master_types_pkg.all;
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------------------------------------------------------------------------------
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-- Entity Declaration
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------------------------------------------------------------------------------
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@ -1,438 +0,0 @@
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------------------------------------------------------------------------------
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-- Libraries
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_common_array_pkg.all;
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use work.psi_common_logic_pkg.all;
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use work.psi_ms_daq_pkg.all;
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------------------------------------------------------------------------------
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-- Entity Declaration
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------------------------------------------------------------------------------
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entity psi_ms_daq_reg_tmem is
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generic (
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Streams_g : in integer range 1 to 32;
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MaxWindows_g : in integer range 1 to 32
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);
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port (
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-- TMEM Interface
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ClkTmem : in std_logic;
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RstTmem : in std_logic;
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TmemRqst : in TmemRqst_t;
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TmemResp : out TmemResp_t;
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-- Control Signals (TMEM Clk)
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Arm : out std_logic_vector(Streams_g-1 downto 0);
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IsArmed : in std_logic_vector(Streams_g-1 downto 0);
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IsRecording : in std_logic_vector(Streams_g-1 downto 0);
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PostTrig : out t_aslv32(Streams_g-1 downto 0);
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RecMode : out t_aslv2(Streams_g-1 downto 0);
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IrqOut : out std_logic;
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-- SMEM Clock domain control singals
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ClkSmem : in std_logic;
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RstSmem : in std_logic;
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-- Context Memory Interface (SMEM Clk)
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CtxStr_Cmd : in ToCtxStr_t;
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CtxStr_Resp : out FromCtx_t;
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CtxWin_Cmd : in ToCtxWin_t;
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CtxWin_Resp : out FromCtx_t;
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-- Logic Interface (SMEM Clk)
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StrIrq : in std_logic_vector(Streams_g-1 downto 0);
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StrLastWin : in WinType_a(Streams_g-1 downto 0);
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StrEna : out std_logic_vector(Streams_g-1 downto 0);
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GlbEna : out std_logic;
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InLevel : in t_aslv16(Streams_g-1 downto 0)
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);
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end entity;
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architecture rtl of psi_ms_daq_reg_tmem is
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-- Two process method
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type two_process_r is record
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Reg_Gcfg_Ena : std_logic;
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Reg_Gcfg_IrqEna : std_logic;
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Reg_IrqVec : std_logic_vector(Streams_g-1 downto 0);
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Reg_IrqEna : std_logic_vector(Streams_g-1 downto 0);
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Reg_StrEna : std_logic_vector(Streams_g-1 downto 0);
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Reg_PostTrig : t_aslv32(Streams_g-1 downto 0);
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Reg_Mode_Recm : t_aslv2(Streams_g-1 downto 0);
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Reg_Mode_Arm : std_logic_vector(Streams_g-1 downto 0);
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Irq : std_logic;
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RegRdval : std_logic_vector(63 downto 0);
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RdVal : std_logic_vector(63 downto 0);
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AddrReg : std_logic_vector(23 downto 0);
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MaxLvlClr : std_logic_vector(Streams_g-1 downto 0);
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end record;
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signal r, r_next : two_process_r;
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constant DwWrite_c : std_logic_vector(3 downto 0) := "1111";
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subtype WeHigh_c is natural range 7 downto 4;
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subtype WeLow_c is natural range 3 downto 0;
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constant DepthCtxStr_c : integer := Streams_g*32/8;
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constant CtxStrAddrHigh_c : integer := log2ceil(Streams_g*32)-1;
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signal CtxStr_WeLo : std_logic;
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signal CtxStr_WeHi : std_logic;
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signal CtxStr_Rdval : std_logic_vector(63 downto 0);
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signal CtxStr_AddrB : std_logic_vector(log2ceil(DepthCtxStr_c)-1 downto 0);
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signal AddrCtxStr : boolean;
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constant DepthCtxWin_c : integer := Streams_g*MaxWindows_g*16/8;
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constant CtxWinAddrHigh_c : integer := log2ceil(Streams_g*MaxWindows_g*16)-1;
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signal CtxWin_WeLo : std_logic;
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signal CtxWin_WeHi : std_logic;
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signal CtxWin_Rdval : std_logic_vector(63 downto 0);
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signal CtxWin_AddrB : std_logic_vector(log2ceil(DepthCtxWin_c)-1 downto 0);
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signal AddrCtxWin : boolean;
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-- Maximum Level Latching
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signal MaxLevel : t_aslv16(Streams_g-1 downto 0);
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-- Clock Crossing Signals
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signal StrIrq_Sync : std_logic_vector(Streams_g-1 downto 0);
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signal StrLastWin_Sync : WinType_a(Streams_g-1 downto 0);
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signal MaxLevel_Sync : t_aslv16(Streams_g-1 downto 0);
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signal MaxLevelClr_Sync : std_logic_vector(Streams_g-1 downto 0);
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begin
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--------------------------------------------
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-- Combinatorial Process
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--------------------------------------------
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p_comb : process( r, TmemRqst, StrIrq_Sync, IsArmed, IsRecording, CtxStr_Rdval, CtxWin_Rdval, MaxLevel, StrLastWin_Sync)
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variable v : two_process_r;
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variable Stream_v : integer range 0 to Streams_g-1;
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begin
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-- *** Hold variables stable ***
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v := r;
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-- *** General Register Accesses ***
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v.RegRdval := (others => '0');
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if TmemRqst.ENA = '1' then
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case TmemRqst.ADD is
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-- GCFG / GSTAT
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when X"000000" =>
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-- GCFG
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if TmemRqst.WE(0) = '1' then
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v.Reg_Gcfg_Ena := TmemRqst.DATW(0);
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end if;
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if TmemRqst.WE(1) = '1' then
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v.Reg_Gcfg_IrqEna := TmemRqst.DATW(8);
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end if;
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v.RegRdval(0) := r.Reg_Gcfg_Ena;
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v.RegRdval(8) := r.Reg_Gcfg_IrqEna;
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-- IRQVEC / IRQENA
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when X"000010" =>
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-- IRQVEC
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if TmemRqst.WE(WeLow_c) = DwWrite_c then
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v.Reg_IrqVec := r.Reg_IrqVec and (not TmemRqst.DATW(Streams_g-1 downto 0));
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end if;
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v.RegRdval(Streams_g-1 downto 0) := r.Reg_IrqVec;
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-- IRQENA
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if TmemRqst.WE(WeHigh_c) = DwWrite_c then
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v.Reg_IrqEna := TmemRqst.DATW(Streams_g+32-1 downto 32);
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end if;
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v.RegRdval(Streams_g+32-1 downto 32) := r.Reg_IrqEna;
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-- STRENA
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when X"000020" =>
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-- STRENA
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if TmemRqst.WE(WeLow_c) = DwWrite_c then
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v.Reg_StrEna := TmemRqst.DATW(Streams_g-1 downto 0);
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end if;
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v.RegRdval(Streams_g-1 downto 0) := r.Reg_StrEna;
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-- others clause
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when others => null;
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end case;
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end if;
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-- *** Stream Register Accesses ***
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v.Reg_Mode_Arm := (others => '0');
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v.MaxLvlClr := (others => '0');
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if TmemRqst.ENA = '1' then
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if TmemRqst.ADD(23 downto 9) = X"000" & "001" then
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Stream_v := to_integer(unsigned(TmemRqst.ADD(8 downto 4)));
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-- MAXLVLn / POSTTRIGn
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if TmemRqst.ADD(3 downto 0) = X"0" then
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-- MAXLVLn
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if TmemRqst.WE(WeLow_c) = DwWrite_c then
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v.MaxLvlClr(Stream_v) := '1';
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end if;
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v.RegRdval(15 downto 0) := MaxLevel(Stream_v);
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-- POSTTRIGn
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if TmemRqst.WE(WeHigh_c) = DwWrite_c then
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v.Reg_PostTrig(Stream_v) := TmemRqst.DATW(63 downto 32);
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end if;
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v.RegRdval(63 downto 32) := r.Reg_PostTrig(Stream_v);
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end if;
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-- MODEn / LASTWINn
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if TmemRqst.ADD(3 downto 0) = X"8" then
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-- MODEn
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if TmemRqst.WE(0) = '1' then
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v.Reg_Mode_Recm(Stream_v) := TmemRqst.DATW(1 downto 0);
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end if;
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if TmemRqst.WE(1) = '1' then
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v.Reg_Mode_Arm(Stream_v) := TmemRqst.DATW(8);
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end if;
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v.RegRdval(1 downto 0) := r.Reg_Mode_Recm(Stream_v);
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v.RegRdval(8) := IsArmed(Stream_v);
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v.RegRdval(16) := IsRecording(Stream_v);
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-- LASTWINn
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v.RegRdval(StrLastWin_Sync(Stream_v)'high+32 downto 32) := StrLastWin_Sync(Stream_v);
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end if;
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end if;
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end if;
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-- *** Read Data MUX ***
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v.AddrReg := TmemRqst.ADD;
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v.RdVal := (others => '0');
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if r.AddrReg(23 downto 12) = X"000" then
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v.RdVal := r.RegRdval;
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elsif r.AddrReg(23 downto 12) = X"001" then
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v.RdVal := CtxStr_Rdval;
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elsif r.AddrReg(23 downto 14) = X"00" & "01" then
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v.RdVal := CtxWin_Rdval;
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end if;
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-- *** IRQ Handling ***
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for i in 0 to Streams_g-1 loop
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if (StrIrq_Sync(i) = '1') and (r.Reg_StrEna(i) = '1') then
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v.Reg_IrqVec(i) := '1';
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end if;
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end loop;
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if ((r.Reg_IrqVec and r.Reg_IrqEna) /= ZerosVector(Streams_g)) and (r.Reg_Gcfg_IrqEna = '1') then
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v.Irq := '1';
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else
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v.Irq := '0';
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end if;
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-- *** Assign to signal ***
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r_next <= v;
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end process;
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-- *** Registered Outputs ***
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TmemResp.PIPE <= "10";
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TmemResp.BUSY <= '0';
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TmemResp.DATR <= r.RdVal;
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IrqOut <= r.Irq;
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PostTrig <= r.Reg_PostTrig;
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Arm <= r.Reg_Mode_Arm;
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RecMode <= r.Reg_Mode_Recm;
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--------------------------------------------
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-- Sequential Process
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--------------------------------------------
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p_seq : process(ClkTmem)
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begin
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if rising_edge(ClkTmem) then
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r <= r_next;
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if RstTmem = '1' then
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r.Reg_Gcfg_Ena <= '0';
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r.Reg_Gcfg_IrqEna <= '0';
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r.Reg_IrqVec <= (others => '0');
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r.Reg_IrqEna <= (others => '0');
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r.Reg_StrEna <= (others => '0');
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r.Irq <= '0';
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r.Reg_PostTrig <= (others => (others => '0'));
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r.Reg_Mode_Recm <= (others => (others => '0'));
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r.Reg_Mode_Arm <= (others => '0');
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end if;
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end if;
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end process;
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--------------------------------------------
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-- Maximum Level Latching (SmemClk)
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--------------------------------------------
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p_maxlvl : process(ClkSmem)
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begin
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if rising_edge(ClkSmem) then
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if RstSmem = '1' then
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MaxLevel <= (others => (others => '0'));
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else
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-- Latch maximum level
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for i in 0 to Streams_g-1 loop
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if MaxLevelClr_Sync(i) = '1' then
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MaxLevel(i) <= (others => '0');
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elsif unsigned(InLevel(i)) > unsigned(MaxLevel(i)) then
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MaxLevel(i) <= InLevel(i);
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end if;
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end loop;
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end if;
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end if;
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end process;
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--------------------------------------------
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-- Component Instantiations
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--------------------------------------------
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-- *** Clock Crossings ***
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blk_cc_irq : block
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begin
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g_in : for i in 0 to Streams_g-1 generate
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i_cc_irq : entity work.psi_common_simple_cc
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generic map (
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DataWidth_g => log2ceil(MaxWindows_c)
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)
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port map (
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ClkA => ClkSmem,
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RstInA => RstSmem,
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DataA => StrLastWin(i),
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VldA => StrIrq(i),
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ClkB => ClkTmem,
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RstInB => RstTmem,
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DataB => StrLastWin_Sync(i),
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VldB => StrIrq_Sync(i)
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);
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end generate;
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end block;
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blk_cc_smem_out : block
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signal ccIn, ccOut : std_logic_vector(Streams_g downto 0);
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begin
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-- Input Assembly
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ccIn(Streams_g-1 downto 0) <= r.Reg_StrEna;
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ccIn(Streams_g) <= r.Reg_Gcfg_Ena;
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-- Instantiation
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i_cc_smem_out : entity work.psi_common_bit_cc
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generic map (
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NumBits_g => Streams_g+1
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)
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port map (
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BitsA => ccIn,
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ClkB => ClkSmem,
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BitsB => ccOut
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);
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-- Output assembly
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StrEna <= ccOut(Streams_g-1 downto 0);
|
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GlbEna <= ccOut(Streams_g);
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end block;
|
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|
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i_cc_smem_out_pulse : entity work.psi_common_pulse_cc
|
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generic map (
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NumPulses_g => Streams_g
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)
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||||
port map (
|
||||
ClkA => ClkTmem,
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||||
RstInA => RstTmem,
|
||||
PulseA => r.MaxLvlClr,
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||||
ClkB => ClkSmem,
|
||||
RstInB => RstSmem,
|
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PulseB => MaxLevelClr_Sync
|
||||
);
|
||||
|
||||
|
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-- *** Stream Context Memory ***
|
||||
-- Signal Assembly
|
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AddrCtxStr <= TmemRqst.ADD(23 downto 12) = X"001";
|
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CtxStr_WeLo <= '1' when TmemRqst.WE(WeLow_c) = DwWrite_c and AddrCtxStr and TmemRqst.ENA = '1' else '0';
|
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CtxStr_WeHi <= '1' when TmemRqst.WE(WeHigh_c) = DwWrite_c and AddrCtxStr and TmemRqst.ENA = '1' else '0';
|
||||
CtxStr_AddrB <= std_logic_vector(to_unsigned(CtxStr_Cmd.Stream, log2ceil(Streams_g))) & CtxStr_Cmd.Sel;
|
||||
|
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-- Low DWORD memory
|
||||
i_mem_ctx_lo : entity work.psi_common_tdp_ram
|
||||
generic map (
|
||||
Depth_g => DepthCtxStr_c,
|
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Width_g => 32,
|
||||
Behavior_g => "RBW"
|
||||
)
|
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port map (
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 3),
|
||||
WrA => CtxStr_WeLo,
|
||||
DinA => TmemRqst.DATW(31 downto 0),
|
||||
DoutA => CtxStr_Rdval(31 downto 0),
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxStr_AddrB,
|
||||
WrB => CtxStr_Cmd.WenLo,
|
||||
DinB => CtxStr_Cmd.WdatLo,
|
||||
DoutB => CtxStr_Resp.RdatLo
|
||||
);
|
||||
|
||||
-- High DWORD memory
|
||||
i_mem_ctx_hi : entity work.psi_common_tdp_ram
|
||||
generic map (
|
||||
Depth_g => DepthCtxStr_c,
|
||||
Width_g => 32,
|
||||
Behavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 3),
|
||||
WrA => CtxStr_WeHi,
|
||||
DinA => TmemRqst.DATW(63 downto 32),
|
||||
DoutA => CtxStr_Rdval(63 downto 32),
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxStr_AddrB,
|
||||
WrB => CtxStr_Cmd.WenHi,
|
||||
DinB => CtxStr_Cmd.WdatHi,
|
||||
DoutB => CtxStr_Resp.RdatHi
|
||||
);
|
||||
|
||||
-- *** Window Context Memory ***
|
||||
-- Signal Assembly
|
||||
AddrCtxWin <= TmemRqst.ADD(23 downto 14) = X"00" & "01";
|
||||
CtxWin_WeLo <= '1' when TmemRqst.WE(WeLow_c) = DwWrite_c and AddrCtxWin and TmemRqst.ENA = '1' else '0';
|
||||
CtxWin_WeHi <= '1' when TmemRqst.WE(WeHigh_c) = DwWrite_c and AddrCtxWin and TmemRqst.ENA = '1'else '0';
|
||||
CtxWin_AddrB <= std_logic_vector(to_unsigned(CtxWin_Cmd.Stream, log2ceil(Streams_g))) &
|
||||
std_logic_vector(to_unsigned(CtxWin_Cmd.Window, log2ceil(MaxWindows_g))) &
|
||||
CtxWin_Cmd.Sel;
|
||||
|
||||
-- Low DWORD memory
|
||||
i_mem_win_lo : entity work.psi_common_tdp_ram
|
||||
generic map (
|
||||
Depth_g => DepthCtxWin_c,
|
||||
Width_g => 32,
|
||||
Behavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 3),
|
||||
WrA => CtxWin_WeLo,
|
||||
DinA => TmemRqst.DATW(31 downto 0),
|
||||
DoutA => CtxWin_Rdval(31 downto 0),
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxWin_AddrB,
|
||||
WrB => CtxWin_Cmd.WenLo,
|
||||
DinB => CtxWin_Cmd.WdatLo,
|
||||
DoutB => CtxWin_Resp.RdatLo
|
||||
);
|
||||
|
||||
-- High DWORD memory
|
||||
i_mem_win_hi : entity work.psi_common_tdp_ram
|
||||
generic map (
|
||||
Depth_g => DepthCtxWin_c,
|
||||
Width_g => 32,
|
||||
Behavior_g => "RBW"
|
||||
)
|
||||
port map (
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 3),
|
||||
WrA => CtxWin_WeHi,
|
||||
DinA => TmemRqst.DATW(63 downto 32),
|
||||
DoutA => CtxWin_Rdval(63 downto 32),
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxWin_AddrB,
|
||||
WrB => CtxWin_Cmd.WenHi,
|
||||
DinB => CtxWin_Cmd.WdatHi,
|
||||
DoutB => CtxWin_Resp.RdatHi
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -1,302 +0,0 @@
|
||||
------------------------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.smem_master_types_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
------------------------------------------------------------------------------
|
||||
entity psi_ms_daq_tosca is
|
||||
generic (
|
||||
Streams_g : positive range 1 to 32 := 2;
|
||||
StreamWidth_g : t_ainteger := (16, 16);
|
||||
StreamPrio_g : t_ainteger := (1, 1);
|
||||
StreamBuffer_g : t_ainteger := (1024, 1024);
|
||||
StreamTimeout_g : t_areal := (1.0e-3, 1.0e-3);
|
||||
StreamClkFreq_g : t_areal := (100.0e6, 100.0e6);
|
||||
StreamTsFifoDepth_g : t_ainteger := (16, 16);
|
||||
StreamUseTs_g : t_abool := (true, true);
|
||||
MaxWindows_g : positive range 1 to 32 := 16;
|
||||
MinBurstSize_g : integer range 1 to 512 := 512;
|
||||
MaxBurstSize_g : integer range 1 to 512 := 512
|
||||
);
|
||||
port (
|
||||
-- Data Stream Input
|
||||
Str_Clk : in std_logic_vector(Streams_g-1 downto 0);
|
||||
Str_Data : in t_aslv64(Streams_g-1 downto 0);
|
||||
Str_Ts : in t_aslv64(Streams_g-1 downto 0);
|
||||
Str_Vld : in std_logic_vector(Streams_g-1 downto 0);
|
||||
Str_Rdy : out std_logic_vector(Streams_g-1 downto 0);
|
||||
Str_Trig : in std_logic_vector(Streams_g-1 downto 0);
|
||||
|
||||
-- TMEM Interface
|
||||
Tmem_Clk : in std_logic;
|
||||
Tmem_Rst : in std_logic;
|
||||
TmemAcq : in TmemRqst_t;
|
||||
AcqTmem : out TmemResp_t;
|
||||
|
||||
-- SMEM Interface
|
||||
Smem_Clk : in std_logic;
|
||||
Smem_Rst : in std_logic;
|
||||
AcqSmem : out ToSmemWr_t;
|
||||
SmemAcq : in FromSmemWr_t;
|
||||
|
||||
-- Miscellaneous
|
||||
Irq : out std_logic -- TMEM clock domain
|
||||
);
|
||||
end entity;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- Architecture Declaration
|
||||
------------------------------------------------------------------------------
|
||||
architecture rtl of psi_ms_daq_tosca is
|
||||
|
||||
-- Control Signals
|
||||
signal Rst : std_logic;
|
||||
|
||||
-- Input/Statemachine Signals
|
||||
signal InpSm_HasTlast : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpSm_TsVld : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpSm_TsRdy : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpSm_Level : t_aslv16(Streams_g-1 downto 0);
|
||||
signal InpSm_TsData : t_aslv64(Streams_g-1 downto 0);
|
||||
|
||||
-- Statemachine/Dma
|
||||
signal SmDma_Cmd : DaqSm2DaqDma_Cmd_t;
|
||||
signal SmDma_CmdVld : std_logic;
|
||||
signal DmaSm_Resp : DaqDma2DaqSm_Resp_t;
|
||||
signal DmaSm_RespVld : std_logic;
|
||||
signal DmaSm_RespRdy : std_logic;
|
||||
signal DmaSm_HasLast : std_logic_vector(Streams_g-1 downto 0);
|
||||
|
||||
-- Input/Dma
|
||||
signal InpDma_Vld : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpDma_Rdy : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal InpDma_Data : Input2Daq_Data_a(Streams_g-1 downto 0);
|
||||
|
||||
-- Dma/Mem
|
||||
signal DmaMem_CmdAddr : std_logic_vector(31 downto 0);
|
||||
signal DmaMem_CmdSize : std_logic_vector(31 downto 0);
|
||||
signal DmaMem_CmdVld : std_logic;
|
||||
signal DmaMem_CmdRdy : std_logic;
|
||||
signal DmaMem_DatData : std_logic_vector(63 downto 0);
|
||||
signal DmaMem_DatVld : std_logic;
|
||||
signal DmaMem_DatRdy : std_logic;
|
||||
|
||||
-- Mem/Statemachine
|
||||
signal MemSm_Done : std_logic;
|
||||
|
||||
-- Configuration
|
||||
signal Cfg_StrEna : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Cfg_GlbEna : std_logic;
|
||||
signal Cfg_PostTrig : t_aslv32(Streams_g-1 downto 0);
|
||||
signal Cfg_Arm : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Cfg_RecMode : t_aslv2(Streams_g-1 downto 0);
|
||||
|
||||
-- Status
|
||||
signal Stat_StrIrq : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Stat_StrLastWin : WinType_a(Streams_g-1 downto 0);
|
||||
signal Stat_IsArmed : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal Stat_IsRecording : std_logic_vector(Streams_g-1 downto 0);
|
||||
|
||||
-- Context Memory Connections
|
||||
signal CtxStr_Cmd : ToCtxStr_t;
|
||||
signal CtxStr_Resp : FromCtx_t;
|
||||
signal CtxWin_Cmd : ToCtxWin_t;
|
||||
signal CtxWin_Resp : FromCtx_t;
|
||||
|
||||
-- Others
|
||||
signal Sm_HasLast : std_logic_vector(Streams_g-1 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------
|
||||
-- TMEM Interface
|
||||
--------------------------------------------
|
||||
i_reg : entity work.psi_ms_daq_reg_tmem
|
||||
generic map (
|
||||
Streams_g => Streams_g,
|
||||
MaxWindows_g => MaxWindows_g
|
||||
)
|
||||
port map (
|
||||
ClkTmem => Tmem_Clk,
|
||||
RstTmem => Tmem_Rst,
|
||||
TmemRqst => TmemAcq,
|
||||
TmemResp => AcqTmem,
|
||||
IrqOut => Irq,
|
||||
PostTrig => Cfg_PostTrig,
|
||||
Arm => Cfg_Arm,
|
||||
IsArmed => Stat_IsArmed,
|
||||
IsRecording => Stat_IsRecording,
|
||||
RecMode => Cfg_RecMode,
|
||||
ClkSmem => Smem_Clk,
|
||||
RstSmem => Smem_Rst,
|
||||
CtxStr_Cmd => CtxStr_Cmd,
|
||||
CtxStr_Resp => CtxStr_Resp,
|
||||
CtxWin_Cmd => CtxWin_Cmd,
|
||||
CtxWin_Resp => CtxWin_Resp,
|
||||
InLevel => InpSm_Level,
|
||||
StrIrq => Stat_StrIrq,
|
||||
StrLastWin => Stat_StrLastWin,
|
||||
StrEna => Cfg_StrEna,
|
||||
GlbEna => Cfg_GlbEna
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- Input Logic Instantiation
|
||||
--------------------------------------------
|
||||
g_input : for str in 0 to Streams_g-1 generate
|
||||
signal InRst : std_logic;
|
||||
signal StrInput : std_logic_vector(StreamWidth_g(str)-1 downto 0);
|
||||
begin
|
||||
-- Reset if stream is disabled
|
||||
InRst <= Smem_Rst or not Cfg_StrEna(str) or not Cfg_GlbEna;
|
||||
StrInput <= Str_Data(str)(StrInput'range);
|
||||
|
||||
-- Instantiation
|
||||
i_input : entity work.psi_ms_daq_input
|
||||
generic map (
|
||||
StreamWidth_g => StreamWidth_g(str),
|
||||
StreamBuffer_g => StreamBuffer_g(str),
|
||||
StreamTimeout_g => StreamTimeout_g(str),
|
||||
StreamClkFreq_g => StreamClkFreq_g(str),
|
||||
StreamTsFifoDepth_g => StreamTsFifoDepth_g(str),
|
||||
StreamUseTs_g => StreamUseTs_g(str)
|
||||
)
|
||||
port map (
|
||||
Str_Clk => Str_Clk(str),
|
||||
Str_Vld => Str_Vld(str),
|
||||
Str_Rdy => Str_Rdy(str),
|
||||
Str_Data => StrInput,
|
||||
Str_Trig => Str_Trig(str),
|
||||
Str_Ts => Str_Ts(str),
|
||||
ClkReg => Tmem_Clk,
|
||||
RstReg => Tmem_Rst,
|
||||
PostTrigSpls => Cfg_PostTrig(str),
|
||||
Mode => Cfg_RecMode(str),
|
||||
Arm => Cfg_Arm(str),
|
||||
IsArmed => Stat_IsArmed(str),
|
||||
IsRecording => Stat_IsRecording(str),
|
||||
ClkMem => Smem_Clk,
|
||||
RstMem => InRst,
|
||||
Daq_Vld => InpDma_Vld(str),
|
||||
Daq_Rdy => InpDma_Rdy(str),
|
||||
Daq_Data => InpDma_Data(str),
|
||||
Daq_Level => InpSm_Level(str),
|
||||
Daq_HasLast => InpSm_HasTlast(str),
|
||||
Ts_Vld => InpSm_TsVld(str),
|
||||
Ts_Rdy => InpSm_TsRdy(str),
|
||||
Ts_Data => InpSm_TsData(str)
|
||||
);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------
|
||||
-- Control State Machine
|
||||
--------------------------------------------
|
||||
-- Detect end-of frame in input buffer or DMA buffer
|
||||
Sm_HasLast <= InpSm_HasTlast or DmaSm_HasLast;
|
||||
|
||||
-- Instantiation
|
||||
i_statemachine : entity work.psi_ms_daq_daq_sm
|
||||
generic map (
|
||||
Streams_g => Streams_g,
|
||||
StreamPrio_g => StreamPrio_g,
|
||||
StreamWidth_g => StreamWidth_g,
|
||||
Windows_g => MaxWindows_g,
|
||||
MinBurstSize_g => MinBurstSize_g,
|
||||
MaxBurstSize_g => MaxBurstSize_g
|
||||
)
|
||||
port map (
|
||||
Clk => Smem_Clk,
|
||||
Rst => Smem_Rst,
|
||||
GlbEna => Cfg_GlbEna,
|
||||
StrEna => Cfg_StrEna,
|
||||
StrIrq => Stat_StrIrq,
|
||||
StrLastWin => Stat_StrLastWin,
|
||||
Inp_HasLast => Sm_HasLast,
|
||||
Inp_Level => InpSm_Level,
|
||||
Ts_Vld => InpSm_TsVld,
|
||||
Ts_Rdy => InpSm_TsRdy,
|
||||
Ts_Data => InpSm_TsData,
|
||||
Dma_Cmd => SmDma_Cmd,
|
||||
Dma_Cmd_Vld => SmDma_CmdVld,
|
||||
Dma_Resp => DmaSm_Resp,
|
||||
Dma_Resp_Vld => DmaSm_RespVld,
|
||||
Dma_Resp_Rdy => DmaSm_RespRdy,
|
||||
TfDone => MemSm_Done,
|
||||
|
||||
-- Context RAM connections
|
||||
CtxStr_Cmd => CtxStr_Cmd,
|
||||
CtxStr_Resp => CtxStr_Resp,
|
||||
CtxWin_Cmd => CtxWin_Cmd,
|
||||
CtxWin_Resp => CtxWin_Resp
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- DMA Engine
|
||||
--------------------------------------------
|
||||
i_dma : entity work.psi_ms_daq_daq_dma
|
||||
generic map (
|
||||
Streams_g => Streams_g
|
||||
)
|
||||
port map (
|
||||
Clk => Smem_Clk,
|
||||
Rst => Smem_Rst,
|
||||
DaqSm_Cmd => SmDma_Cmd,
|
||||
DaqSm_Cmd_Vld => SmDma_CmdVld,
|
||||
DaqSm_Resp => DmaSm_Resp,
|
||||
DaqSm_Resp_Vld => DmaSm_RespVld,
|
||||
DaqSm_Resp_Rdy => DmaSm_RespRdy,
|
||||
DaqSm_HasLast => DmaSm_HasLast,
|
||||
Inp_Vld => InpDma_Vld,
|
||||
Inp_Rdy => InpDma_Rdy,
|
||||
Inp_Data => InpDma_Data,
|
||||
Mem_CmdAddr => DmaMem_CmdAddr,
|
||||
Mem_CmdSize => DmaMem_CmdSize,
|
||||
Mem_CmdVld => DmaMem_CmdVld,
|
||||
Mem_CmdRdy => DmaMem_CmdRdy,
|
||||
Mem_DatData => DmaMem_DatData,
|
||||
Mem_DatVld => DmaMem_DatVld,
|
||||
Mem_DatRdy => DmaMem_DatRdy
|
||||
);
|
||||
|
||||
--------------------------------------------
|
||||
-- SMEM Controller
|
||||
--------------------------------------------
|
||||
i_memif : entity work.smem_master_write
|
||||
generic map (
|
||||
MaxBurstSize_g => 512,
|
||||
MemBlockSize_g => 4096,
|
||||
DataBufferSize_g => 1024,
|
||||
MaxOpenTransactions_g => Streams_g
|
||||
)
|
||||
port map (
|
||||
Clk => Smem_Clk,
|
||||
Rst => Smem_Rst,
|
||||
Cmd_Addr => DmaMem_CmdAddr,
|
||||
Cmd_Size => DmaMem_CmdSize,
|
||||
Cmd_Vld => DmaMem_CmdVld,
|
||||
Cmd_Rdy => DmaMem_CmdRdy,
|
||||
Dat_Data => DmaMem_DatData,
|
||||
Dat_Vld => DmaMem_DatVld,
|
||||
Dat_Rdy => DmaMem_DatRdy,
|
||||
Done => MemSm_Done,
|
||||
ToSmem => AcqSmem,
|
||||
FromSmem => SmemAcq
|
||||
);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -32,8 +32,6 @@ add_sources $LibPath {
|
||||
psi_common/hdl/psi_common_axi_master_simple.vhd \
|
||||
psi_common/hdl/psi_common_wconv_n2xn.vhd \
|
||||
psi_common/hdl/psi_common_axi_master_full.vhd \
|
||||
../../BoardSupport/IFC1210/smem_master/hdl/smem_master_types_pkg.vhd \
|
||||
../../BoardSupport/IFC1210/smem_master/hdl/smem_master_write.vhd \
|
||||
../VivadoIp/axi_slave_ipif_package/hdl/axi_slave_ipif_package.vhd \
|
||||
} -tag lib
|
||||
|
||||
@ -43,8 +41,6 @@ add_sources "../hdl" {
|
||||
psi_ms_daq_input.vhd \
|
||||
psi_ms_daq_daq_sm.vhd \
|
||||
psi_ms_daq_daq_dma.vhd \
|
||||
psi_ms_daq_reg_tmem.vhd \
|
||||
psi_ms_daq_tosca.vhd \
|
||||
psi_ms_daq_axi_if.vhd \
|
||||
psi_ms_daq_reg_axi.vhd \
|
||||
psi_ms_daq_axi.vhd \
|
||||
@ -81,12 +77,6 @@ add_sources "../tb" {
|
||||
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_aligned.vhd \
|
||||
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_errors.vhd \
|
||||
psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb.vhd \
|
||||
psi_ms_daq_tosca/psi_ms_daq_tosca_tb_pkg.vhd \
|
||||
psi_ms_daq_tosca/psi_ms_daq_tosca_tb_str0_pkg.vhd \
|
||||
psi_ms_daq_tosca/psi_ms_daq_tosca_tb_str1_pkg.vhd \
|
||||
psi_ms_daq_tosca/psi_ms_daq_tosca_tb_str2_pkg.vhd \
|
||||
psi_ms_daq_tosca/psi_ms_daq_tosca_tb_str3_pkg.vhd \
|
||||
psi_ms_daq_tosca/psi_ms_daq_tosca_tb.vhd \
|
||||
psi_ms_daq_axi/psi_ms_daq_axi_tb_pkg.vhd \
|
||||
psi_ms_daq_axi/psi_ms_daq_axi_tb_str0_pkg.vhd \
|
||||
psi_ms_daq_axi/psi_ms_daq_axi_tb_str1_pkg.vhd \
|
||||
@ -112,9 +102,6 @@ add_tb_run
|
||||
create_tb_run "psi_ms_daq_daq_dma_tb"
|
||||
add_tb_run
|
||||
|
||||
create_tb_run "psi_ms_daq_tosca_tb"
|
||||
add_tb_run
|
||||
|
||||
create_tb_run "psi_ms_daq_axi_tb"
|
||||
add_tb_run
|
||||
|
||||
|
||||
@ -1,318 +0,0 @@
|
||||
------------------------------------------------------------
|
||||
-- Testbench generated by TbGen.py
|
||||
------------------------------------------------------------
|
||||
-- see Library/Python/TbGenerator
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.smem_master_types_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_str0_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_str1_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_str2_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_str3_pkg.all;
|
||||
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Entity Declaration
|
||||
------------------------------------------------------------
|
||||
entity psi_ms_daq_tosca_tb is
|
||||
end entity;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Architecture
|
||||
------------------------------------------------------------
|
||||
architecture sim of psi_ms_daq_tosca_tb is
|
||||
|
||||
-- TB Control
|
||||
signal TbRunning : boolean := true;
|
||||
signal PrintIrq_c : boolean := PrintDefault_c;
|
||||
|
||||
-- Constants
|
||||
constant StrCount_c : integer := 4;
|
||||
constant ClkFreq_c : t_areal := (0=>250.0e6, 1=>125.0e6, 2=>80.0e6, 3=>200.0e6);
|
||||
|
||||
|
||||
-- Port signals
|
||||
signal Str_Clk : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Str0_Data : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal Str1_Data : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal Str2_Data : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal Str3_Data : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal Timestamp : t_aslv64(StrCount_c-1 downto 0) := (others => (others => '0'));
|
||||
signal Str_Vld : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Str_Rdy : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Str_Trig : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Tmem_Clk : std_logic := '0';
|
||||
signal Smem_Clk : std_logic := '0';
|
||||
signal Tmem_Rst : std_logic := '1';
|
||||
signal Smem_Rst : std_logic := '1';
|
||||
signal TmemAcq : TmemRqst_t := TmemRqst_init_c;
|
||||
signal AcqTmem : TmemResp_t;
|
||||
signal SmemAcq : FromSmemWr_t := (others => (others => '0'));
|
||||
signal AcqSmem : ToSmemWr_t;
|
||||
signal Irq : std_logic := '0';
|
||||
|
||||
|
||||
procedure IrqHandler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
variable slv : std_logic_vector(31 downto 0);
|
||||
begin
|
||||
print("###################################### IRQ Detected #########################################", PrintIrq_c);
|
||||
wait until rising_edge(clk);
|
||||
TmemRead32(16#0010#, v, clk, rqst, rsp);
|
||||
slv := std_logic_vector(to_unsigned(v, 32));
|
||||
TmemWrite32(16#0010#, v, clk, rqst, rsp);
|
||||
for i in 0 to StrCount_c-1 loop
|
||||
if slv(i) = '1' then
|
||||
case i is
|
||||
when 0 => Str0Handler(clk, rqst, rsp);
|
||||
when 1 => Str1Handler(clk, rqst, rsp);
|
||||
when 2 => Str2Handler(clk, rqst, rsp);
|
||||
when 3 => Str3Handler(clk, rqst, rsp);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end loop;
|
||||
-- Delay to ensure IRQ is cleared
|
||||
for i in 0 to 5 loop
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
|
||||
begin
|
||||
------------------------------------------------------------
|
||||
-- DUT Instantiation
|
||||
------------------------------------------------------------
|
||||
i_dut : entity work.psi_ms_daq_tosca
|
||||
generic map (
|
||||
Streams_g => StrCount_c,
|
||||
StreamWidth_g => (0=>8, 1=>16, 2=>16, 3=>32),
|
||||
StreamPrio_g => (0=>1, 1=>3, 2=>2, 3=>2),
|
||||
StreamBuffer_g => (0=>32, 1=>128, 2=>128, 3=>128),
|
||||
StreamTimeout_g => (0=>5.0e-6, 1=>1.0e-3, 2=>1.0e-3, 3=>1.0e-3),
|
||||
StreamClkFreq_g => ClkFreq_c,
|
||||
StreamTsFifoDepth_g => (0=>16, 1=>16, 2=>16, 3=>16),
|
||||
StreamUseTs_g => (0=>true, 1=>true, 2=>true, 3=>false),
|
||||
MaxWindows_g => work.psi_ms_daq_tosca_tb_pkg.MaxWindows_c,
|
||||
MinBurstSize_g => 16,
|
||||
MaxBurstSize_g => 128
|
||||
)
|
||||
port map (
|
||||
Str_Clk => Str_Clk,
|
||||
Str_Data(0)(7 downto 0) => Str0_Data,
|
||||
Str_Data(0)(63 downto 8) => (others => '0'),
|
||||
Str_Data(1)(15 downto 0) => Str1_Data,
|
||||
Str_Data(1)(63 downto 16) => (others => '0'),
|
||||
Str_Data(2)(15 downto 0) => Str2_Data,
|
||||
Str_Data(2)(63 downto 16) => (others => '0'),
|
||||
Str_Data(3)(31 downto 0) => Str3_Data,
|
||||
Str_Data(3)(63 downto 32) => (others => '0'),
|
||||
Str_Ts => Timestamp,
|
||||
Str_Vld => Str_Vld,
|
||||
Str_Rdy => Str_Rdy,
|
||||
Str_Trig => Str_Trig,
|
||||
Tmem_Clk => Tmem_Clk,
|
||||
Tmem_Rst => Tmem_Rst,
|
||||
Smem_Clk => Smem_Clk,
|
||||
Smem_Rst => Smem_Rst,
|
||||
TmemAcq => TmemAcq,
|
||||
AcqTmem => AcqTmem,
|
||||
AcqSmem => AcqSmem,
|
||||
SmemAcq => SmemAcq,
|
||||
Irq => Irq
|
||||
);
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Emulate Memory
|
||||
------------------------------------------------------------
|
||||
p_mem : process
|
||||
variable Address_v : integer;
|
||||
variable Size_v : integer;
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait until (rising_edge(Smem_Clk) and AcqSmem.WREQ = SMEM_REQ_Request_c) or (not TbRunning);
|
||||
if TbRunning then
|
||||
wait until rising_edge(Smem_Clk);
|
||||
Address_v := to_integer(unsigned(AcqSmem.WADD));
|
||||
Size_v := to_integer(unsigned(AcqSmem.WSIZ));
|
||||
SmemAcq.WACK <= SMEM_ACK_Grant_c;
|
||||
wait until rising_edge(Smem_Clk);
|
||||
SmemAcq.WACK <= SMEM_ACK_Burst_c;
|
||||
wait until rising_edge(Smem_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
for qw in 0 to Size_v-1 loop
|
||||
if qw = Size_v-1 then
|
||||
SmemAcq.WACK <= SMEM_ACK_Done_c;
|
||||
end if;
|
||||
wait until rising_edge(Smem_Clk);
|
||||
for byte in 0 to 7 loop
|
||||
if AcqSmem.WBE(byte) = '1' then
|
||||
Memory(Address_v+qw*8+byte) <= AcqSmem.WDAT(byte*8+7 downto byte*8);
|
||||
end if;
|
||||
end loop;
|
||||
end loop;
|
||||
SmemAcq.WACK <= SMEM_ACK_Idle_c;
|
||||
wait until rising_edge(Smem_Clk);
|
||||
end if;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Clocks
|
||||
------------------------------------------------------------
|
||||
|
||||
p_clk_smem : process
|
||||
constant Frequency_c : real := real(200e6);
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/Frequency_c;
|
||||
Smem_Clk <= not Smem_Clk;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_clk_tmem : process
|
||||
constant Frequency_c : real := real(166e6);
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/Frequency_c;
|
||||
Tmem_Clk <= not Tmem_Clk;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
g_clk_str : for i in 0 to StrCount_c-1 generate
|
||||
p_clk_str : process
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/(ClkFreq_c(i)+0.1e6);
|
||||
Str_Clk(i) <= not Str_Clk(i);
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- TMEM Process
|
||||
------------------------------------------------------------
|
||||
p_tmem : process
|
||||
variable StartTime_v : time;
|
||||
variable Stream1Armed_v : boolean := false;
|
||||
variable Stream2Armed_v : boolean := false;
|
||||
begin
|
||||
print("*** Info ***");
|
||||
print("This testbench does not print any status information by default (only errors).");
|
||||
print("To change this behavior, change the constant PrintDefault_c in psi_ms_daq_tosca_tb_pkg.");
|
||||
|
||||
wait for 1 us;
|
||||
Tmem_Rst <= '0';
|
||||
Smem_Rst <= '0';
|
||||
|
||||
-- *** Initial Configuration ***
|
||||
TmemExpect32(16#0010#, 0, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0014#, 16#000F#, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0020#, 16#000F#, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
-- Stream Setup
|
||||
Str0Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str1Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str2Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str3Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
|
||||
-- Enable
|
||||
TmemWriteAndRead32(16#0000#, 16#0101#, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
|
||||
|
||||
-- *** Run Test ***
|
||||
StartTime_v := now;
|
||||
while now < StartTime_v+150 us loop
|
||||
wait until rising_edge(Tmem_Clk);
|
||||
-- IRQ Handling
|
||||
if Irq = '1' then
|
||||
IrqHandler(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
end if;
|
||||
-- Regular actions
|
||||
Str0Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str1Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str2Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str3Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
|
||||
end loop;
|
||||
TbRunning <= false;
|
||||
|
||||
-- *** Check end state ***
|
||||
assert Str0WinCheck >= 4 report "###ERROR###: Stream 0 checks not completed" severity error;
|
||||
assert Str1WinCheck = 1 report "###ERROR###: Stream 1 checks not completed" severity error;
|
||||
assert Str2WinCheck = 2 report "###ERROR###: Stream 2 checks not completed" severity error;
|
||||
assert Str3WinCheck = 2 report "###ERROR###: Stream 3 checks not completed" severity error;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Timestamp Processes
|
||||
------------------------------------------------------------
|
||||
g_ts : for i in 0 to StrCount_c-1 generate
|
||||
p_ts : process
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait until rising_edge(Str_Clk(0));
|
||||
Timestamp(0) <= std_logic_vector(unsigned(Timestamp(0)) + 1);
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Data Generation Processes
|
||||
------------------------------------------------------------
|
||||
p_str0 : process
|
||||
variable IrqOn : boolean := false;
|
||||
begin
|
||||
wait until rising_edge(Str_Clk(0));
|
||||
while TbRunning loop
|
||||
Str0Sample(Str_Clk(0), Str_Vld(0), Str_Trig(0), Str0_Data);
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_str1 : process
|
||||
begin
|
||||
Str1Data(Str_Clk(1), Str_Vld(1), Str_Trig(1), Str1_Data);
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_str2 : process
|
||||
begin
|
||||
Str2Data(Str_Clk(2), Str_Vld(2), Str_Trig(2), Str2_Data);
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_str3 : process
|
||||
begin
|
||||
Str3Data(Str_Clk(3), Str_Vld(3), Str_Trig(3), Str3_Data);
|
||||
wait;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Check Process
|
||||
------------------------------------------------------------
|
||||
|
||||
end;
|
||||
@ -1,500 +0,0 @@
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
||||
package psi_ms_daq_tosca_tb_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Global Stuff
|
||||
--------------------------------------------------------
|
||||
constant MemSize_c : integer := 16#10000#;
|
||||
signal Memory : t_aslv8(0 to MemSize_c-1);
|
||||
constant MaxWindows_c : integer := 16;
|
||||
|
||||
constant PrintDefault_c : boolean := false;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Register MAP
|
||||
--------------------------------------------------------
|
||||
constant REG_CONF_REGION : integer := 16#0000#;
|
||||
constant REG_CONF_GCFG_ADDR : integer := REG_CONF_REGION+16#000#;
|
||||
constant REG_CONF_GSTAT_ADDR : integer := REG_CONF_REGION+16#004#;
|
||||
constant REG_CONF_IRQVEC_ADDR : integer := REG_CONF_REGION+16#010#;
|
||||
constant REG_CONF_IRQENA_ADDR : integer := REG_CONF_REGION+16#014#;
|
||||
constant REG_CONF_STRENA_ADDR : integer := REG_CONF_REGION+16#020#;
|
||||
constant REG_CONF_Xn_STEP : integer := 16#10#;
|
||||
constant REG_CONF_MAXLVLn : integer := 16#200#;
|
||||
constant REG_CONF_POSTTRIGn : integer := 16#204#;
|
||||
constant REG_CONF_MODEn : integer := 16#208#;
|
||||
constant REG_CONF_LASTWINn : integer := 16#20C#;
|
||||
constant VAL_MODE_RECM_CONT : integer := 0*2**0;
|
||||
constant VAL_MODE_RECM_TRIGMASK : integer := 1*2**0;
|
||||
constant VAL_MODE_RECM_SINGLE : integer := 2*2**0;
|
||||
constant VAL_MODE_RECM_MANUAL : integer := 3*2**0;
|
||||
constant VAL_MODE_ARM : integer := 1*2**8;
|
||||
constant VAL_MODE_RECORDING : integer := 1*2**16;
|
||||
|
||||
constant REG_CTX_REGION : integer := 16#1000#;
|
||||
constant REG_CTX_Xn_STEP : integer := 16#20#;
|
||||
constant REG_CTX_SCFGn : integer := 16#00#;
|
||||
constant VAL_SCFG_RINGBUF : integer := 1*2**0;
|
||||
constant VAL_SCFG_OVERWRITE : integer := 1*2**8;
|
||||
constant SFT_SCFG_WINCNT : integer := 16;
|
||||
constant SFT_SCFG_WINCUR : integer := 24;
|
||||
constant MSK_SCFG_WINCUR : integer := 16#1F000000#;
|
||||
constant REG_CTX_BUFSTARTn : integer := 16#04#;
|
||||
constant REG_CTX_WINSIZEn : integer := 16#08#;
|
||||
constant REG_CTX_PTRn : integer := 16#0C#;
|
||||
|
||||
constant REG_WIN_REGION : integer := 16#4000#;
|
||||
constant REG_WIN_STRn_STEP : integer := MaxWindows_c*16#10#;
|
||||
constant REG_WIN_WINn_STEP : integer := 16#10#;
|
||||
constant REG_WIN_WINCNT : integer := 16#00#;
|
||||
constant MSK_WIN_WINCNT_CNT : integer := 16#7FFFFFFF#;
|
||||
constant REG_WIN_WINLAST : integer := 16#04#;
|
||||
constant REG_WIN_TSLO : integer := 16#08#;
|
||||
constant REG_WIN_TSHI : integer := 16#0C#;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Helper Procedures
|
||||
--------------------------------------------------------
|
||||
function IntAnd( int : in integer;
|
||||
op : in integer) return integer;
|
||||
|
||||
procedure print( str : in string;
|
||||
ena : in boolean);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- TMEM Procedures
|
||||
--------------------------------------------------------
|
||||
procedure TmemWrite32( address : in integer;
|
||||
value : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure TmemRead32( address : in integer;
|
||||
value : out integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure TmemExpect32( address : in integer;
|
||||
value : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure TmemWriteAndRead32( address : in integer;
|
||||
value : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- High Level Procedures
|
||||
--------------------------------------------------------
|
||||
procedure HlCheckMaxLvl( str : in integer;
|
||||
expLevel : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure HlSetPostTrig( str : in integer;
|
||||
val : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure HlSetMode( str : in integer;
|
||||
val : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure HlConfStream( str : in integer;
|
||||
bufstart : in integer;
|
||||
ringbuf : in boolean;
|
||||
overwrite : in boolean;
|
||||
wincnt : in integer;
|
||||
winsize : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure HlIsRecording( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out boolean);
|
||||
|
||||
procedure HlGetPtr( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlGetMaxLvl( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlGetLastWin( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlGetCurWin( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlGetWinCnt( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlIsTrigWin( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out boolean);
|
||||
|
||||
procedure HlClrWinCnt( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
procedure HlGetWinLast( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlGetTsLo( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
procedure HlGetTsHi( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer);
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_tosca_tb_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Helper Procedures
|
||||
--------------------------------------------------------
|
||||
function IntAnd( int : in integer;
|
||||
op : in integer) return integer is
|
||||
variable intu, opu : signed(31 downto 0);
|
||||
begin
|
||||
intu := to_signed(int, 32);
|
||||
opu := to_signed(op, 32);
|
||||
return to_integer(intu and opu);
|
||||
end function;
|
||||
|
||||
procedure print( str : in string;
|
||||
ena : in boolean) is
|
||||
begin
|
||||
if ena then
|
||||
print(str);
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- TMEM Procedures
|
||||
--------------------------------------------------------
|
||||
procedure TmemWrite32( address : in integer;
|
||||
value : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
rqst.ADD <= std_logic_vector(to_unsigned(address, 24)) and X"FFFFF8";
|
||||
rqst.ENA <= '1';
|
||||
rqst.DATW <= (others => '0');
|
||||
rqst.WE <= (others => '0');
|
||||
if address mod 8 = 0 then
|
||||
rqst.DATW(31 downto 0) <= std_logic_vector(to_unsigned(value, 32));
|
||||
rqst.WE(3 downto 0) <= (others => '1');
|
||||
else
|
||||
rqst.DATW(63 downto 32) <= std_logic_vector(to_unsigned(value, 32));
|
||||
rqst.WE(7 downto 4) <= (others => '1');
|
||||
end if;
|
||||
wait until rising_edge(clk);
|
||||
rqst.ENA <= '0';
|
||||
rqst.WE <= (others => '0');
|
||||
end procedure;
|
||||
|
||||
procedure TmemRead32( address : in integer;
|
||||
value : out integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
rqst.ADD <= std_logic_vector(to_unsigned(address, 24)) and X"FFFFF8";
|
||||
rqst.ENA <= '1';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
if address mod 8 = 0 then
|
||||
value := to_integer(signed(rsp.DATR(31 downto 0)));
|
||||
else
|
||||
value := to_integer(signed(rsp.DATR(63 downto 32)));
|
||||
end if;
|
||||
rqst.ENA <= '0';
|
||||
end procedure;
|
||||
|
||||
procedure TmemExpect32( address : in integer;
|
||||
value : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable readVal : integer;
|
||||
begin
|
||||
TmemRead32(address, readVal, clk, rqst, rsp);
|
||||
IntCompare(value, readVal, "Unexpected value at address 0x" & to_hstring(to_unsigned(address, 32)));
|
||||
end procedure;
|
||||
|
||||
|
||||
procedure TmemWriteAndRead32( address : in integer;
|
||||
value : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
TmemWrite32(address, value, clk, rqst, rsp);
|
||||
wait for 400 ns;
|
||||
wait until rising_edge(clk);
|
||||
TmemExpect32(address, value, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- High Level Procedures
|
||||
--------------------------------------------------------
|
||||
procedure HlCheckMaxLvl( str : in integer;
|
||||
expLevel : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
TmemExpect32(REG_CONF_MAXLVLn+REG_CONF_Xn_STEP*str, expLevel, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlSetPostTrig( str : in integer;
|
||||
val : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
TmemWriteAndRead32(REG_CONF_POSTTRIGn+REG_CONF_Xn_STEP*str, val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlSetMode( str : in integer;
|
||||
val : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
TmemWrite32(REG_CONF_MODEn+REG_CONF_Xn_STEP*str, val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlConfStream( str : in integer;
|
||||
bufstart : in integer;
|
||||
ringbuf : in boolean;
|
||||
overwrite : in boolean;
|
||||
wincnt : in integer;
|
||||
winsize : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer := 0;
|
||||
begin
|
||||
TmemWriteAndRead32( REG_CTX_REGION+REG_CTX_BUFSTARTn+REG_CTX_Xn_STEP*str,
|
||||
bufstart, clk, rqst, rsp);
|
||||
TmemWriteAndRead32( REG_CTX_REGION+REG_CTX_WINSIZEn+REG_CTX_Xn_STEP*str,
|
||||
winsize, clk, rqst, rsp);
|
||||
if ringbuf then
|
||||
v := v + VAL_SCFG_RINGBUF;
|
||||
end if;
|
||||
if overwrite then
|
||||
v := v + VAL_SCFG_OVERWRITE;
|
||||
end if;
|
||||
v := v + (2**SFT_SCFG_WINCNT)*(wincnt-1);
|
||||
TmemWriteAndRead32( REG_CTX_REGION+REG_CTX_SCFGn+REG_CTX_Xn_STEP*str,
|
||||
v, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlIsRecording( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out boolean) is
|
||||
variable v : integer := 0;
|
||||
begin
|
||||
TmemRead32( REG_CONF_REGION+REG_CONF_MODEn+REG_CONF_Xn_STEP*str,
|
||||
v, clk, rqst, rsp);
|
||||
if IntAnd(v, VAL_MODE_RECORDING) /= 0 then
|
||||
val := true;
|
||||
else
|
||||
val := false;
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
procedure HlGetPtr( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
begin
|
||||
TmemRead32( REG_CTX_REGION+REG_CTX_PTRn+REG_CTX_Xn_STEP*str,
|
||||
val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlGetMaxLvl( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
begin
|
||||
TmemRead32( REG_CONF_REGION+REG_CONF_MAXLVLn+REG_CONF_Xn_STEP*str,
|
||||
val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlGetLastWin( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
begin
|
||||
TmemRead32( REG_CONF_REGION+REG_CONF_LASTWINn+REG_CONF_Xn_STEP*str,
|
||||
val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlGetCurWin( str : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemRead32( REG_CTX_REGION+REG_CTX_SCFGn+REG_CTX_Xn_STEP*str,
|
||||
v, clk, rqst, rsp);
|
||||
v := IntAnd(v, MSK_SCFG_WINCUR);
|
||||
v := v / (2**SFT_SCFG_WINCUR);
|
||||
val := v;
|
||||
end procedure;
|
||||
|
||||
procedure HlGetWinCnt( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemRead32( REG_WIN_REGION+REG_WIN_WINCNT+REG_WIN_STRn_STEP*str+REG_WIN_WINn_STEP*win,
|
||||
v, clk, rqst, rsp);
|
||||
val := IntAnd(v, MSK_WIN_WINCNT_CNT);
|
||||
end procedure;
|
||||
|
||||
procedure HlIsTrigWin( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out boolean) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemRead32( REG_WIN_REGION+REG_WIN_WINCNT+REG_WIN_STRn_STEP*str+REG_WIN_WINn_STEP*win,
|
||||
v, clk, rqst, rsp);
|
||||
val := v < 0;
|
||||
end procedure;
|
||||
|
||||
procedure HlClrWinCnt( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemWrite32( REG_WIN_REGION+REG_WIN_WINCNT+REG_WIN_STRn_STEP*str+REG_WIN_WINn_STEP*win,
|
||||
0, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlGetWinLast( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemRead32( REG_WIN_REGION+REG_WIN_WINLAST+REG_WIN_STRn_STEP*str+REG_WIN_WINn_STEP*win,
|
||||
val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlGetTsLo( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemRead32( REG_WIN_REGION+REG_WIN_TSLO+REG_WIN_STRn_STEP*str+REG_WIN_WINn_STEP*win,
|
||||
val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
procedure HlGetTsHi( str : in integer;
|
||||
win : in integer;
|
||||
signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t;
|
||||
val : out integer) is
|
||||
variable v : integer;
|
||||
begin
|
||||
TmemRead32( REG_WIN_REGION+REG_WIN_TSHi+REG_WIN_STRn_STEP*str+REG_WIN_WINn_STEP*win,
|
||||
val, clk, rqst, rsp);
|
||||
end procedure;
|
||||
|
||||
|
||||
|
||||
end;
|
||||
@ -1,248 +0,0 @@
|
||||
------------------------------------------------------------
|
||||
-- Description
|
||||
------------------------------------------------------------
|
||||
-- Stream 0 works in ringbuffer mode (without overwrite). It
|
||||
-- produces 8-bit data (modulo counter). IRQs are located at samples
|
||||
-- containing data 30, 60 and 90. IRQs are suppressed until 15 us after
|
||||
-- simulation to see if IRQ enable works correctly.
|
||||
-- The IRQ handler also sets the window sample counter to zero to ensure
|
||||
-- more data can be recorded after the IRQ.
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
||||
package psi_ms_daq_tosca_tb_str0_pkg is
|
||||
|
||||
constant PrintStr0_c : boolean := PrintDefault_c;
|
||||
|
||||
-- Memory
|
||||
constant Str0BufStart_c : integer := 16#1000#;
|
||||
constant Str0WinSize_c : integer := 100;
|
||||
constant Str0Windows_c : integer := 3;
|
||||
alias Memory0 : t_aslv8(0 to Str0WinSize_c*Str0Windows_c) is Memory(Str0BufStart_c to Str0BufStart_c+Str0WinSize_c*Str0Windows_c);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Persistent State
|
||||
--------------------------------------------------------
|
||||
shared variable Str0NextWin : integer := 0;
|
||||
shared variable Str0WinCheck : integer := 0;
|
||||
shared variable Str0LastTs : integer;
|
||||
shared variable Str0IrqOn : boolean := false;
|
||||
shared variable Str0Disabled : boolean := false;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str0Sample( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(7 downto 0));
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str0Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str0Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str0Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_tosca_tb_str0_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str0Sample( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(7 downto 0)) is
|
||||
begin
|
||||
vld <= '1';
|
||||
if (now > 15 us) and (to_integer(unsigned(data)) = 0) then
|
||||
Str0IrqOn := true;
|
||||
end if;
|
||||
case to_integer(unsigned(data)) is
|
||||
when 30 | 60 | 90 =>
|
||||
if Str0IrqOn then
|
||||
trig <= '1';
|
||||
end if;
|
||||
when others => null;
|
||||
end case;
|
||||
wait until rising_edge(clk);
|
||||
vld <= '0';
|
||||
trig <= '0';
|
||||
data <= std_logic_vector(unsigned(data)+1);
|
||||
wait until rising_edge(clk);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str0Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
variable curwin : integer;
|
||||
variable wincnt : integer;
|
||||
variable winstart, winend : integer;
|
||||
variable winlast : integer;
|
||||
variable addr : integer;
|
||||
variable tslo : integer;
|
||||
variable firstLoop : boolean := true;
|
||||
variable HasTrigger : boolean;
|
||||
begin
|
||||
print("------------ Stream 0 Handler ------------", PrintStr0_c);
|
||||
HlGetMaxLvl(0, clk, rqst, rsp, v);
|
||||
print("MAXLVL: " & to_string(v), PrintStr0_c);
|
||||
HlGetCurWin(0, clk, rqst, rsp, curwin);
|
||||
print("CURWIN: " & to_string(curwin), PrintStr0_c);
|
||||
print("", PrintStr0_c);
|
||||
if Str0Disabled then
|
||||
print("Skipped, stream disabled", PrintStr0_c);
|
||||
print("", PrintStr0_c);
|
||||
else
|
||||
HlIsTrigWin(0, Str0NextWin, clk, rqst, rsp, HasTrigger);
|
||||
-- curwin = nextwin can occur if al lwindows are filled. In all cases we only interpret windows containing triggers.
|
||||
while ((Str0NextWin /= curwin) or firstLoop) and HasTrigger loop
|
||||
firstLoop := false;
|
||||
print("*** Window " & to_string(Str0NextWin) & " / Number: " & to_string(Str0WinCheck) & " ***", PrintStr0_c);
|
||||
HlGetWinCnt(0, Str0NextWin, clk, rqst, rsp, wincnt);
|
||||
print("WINCNT: " & to_string(wincnt), PrintStr0_c);
|
||||
HlClrWinCnt(0, Str0NextWin, clk, rqst, rsp);
|
||||
HlGetWinLast(0, Str0NextWin, clk, rqst, rsp, winlast);
|
||||
print("WINLAST: " & to_string(winlast), PrintStr0_c);
|
||||
HlGetTsLo(0, Str0NextWin, clk, rqst, rsp, tslo);
|
||||
print("WINTSLO: " & to_string(tslo), PrintStr0_c);
|
||||
HlGetTsHi(0, Str0NextWin, clk, rqst, rsp, v);
|
||||
print("WINTSHI: " & to_string(v), PrintStr0_c);
|
||||
winstart := Str0BufStart_c + Str0NextWin*Str0WinSize_c;
|
||||
winend := winstart + Str0WinSize_c - 1;
|
||||
case Str0WinCheck is
|
||||
when 0 =>
|
||||
-- Windows full because dat received for quite some time
|
||||
IntCompare(Str0WinSize_c, wincnt, "Stream0: WINCNT wrong");
|
||||
-- Check Values
|
||||
addr := winlast;
|
||||
|
||||
for i in 256+30+3-99 to 256+30+3 loop
|
||||
if addr = winend then
|
||||
addr := winstart;
|
||||
else
|
||||
addr := addr + 1;
|
||||
end if;
|
||||
StdlvCompareInt (i mod 256, Memory(addr), "Stream0: Wrong value at 0x" & to_hstring(to_unsigned(addr,32)), false);
|
||||
end loop;
|
||||
|
||||
when 1 =>
|
||||
-- Trigger following each other with 30 samples difference
|
||||
IntCompare(30, wincnt, "Stream0: WINCNT wrong");
|
||||
IntCompare(30*2, tslo-Str0LastTs, "Stream0: TS difference wrong");
|
||||
-- Check Values
|
||||
addr := winstart;
|
||||
for i in 34 to 63 loop
|
||||
StdlvCompareInt (i, Memory(addr), "Stream0: Wrong value", false);
|
||||
addr := addr + 1; -- does never wrap
|
||||
end loop;
|
||||
|
||||
when 2 =>
|
||||
-- Trigger following each other with 30 samples difference
|
||||
IntCompare(30, wincnt, "Stream0: WINCNT wrong");
|
||||
IntCompare(30*2, tslo-Str0LastTs, "Stream0: TS difference wrong");
|
||||
-- Check Values
|
||||
addr := winstart;
|
||||
for i in 64 to 93 loop
|
||||
StdlvCompareInt (i, Memory(addr), "Stream0: Wrong value", false);
|
||||
addr := addr + 1; -- does never wrap
|
||||
end loop;
|
||||
when 3 =>
|
||||
-- Full buffer recorded after emptying first buffer
|
||||
IntCompare(100, wincnt, "Stream0: WINCNT wrong");
|
||||
IntCompare((256-2*30)*2, tslo-Str0LastTs, "Stream0: TS difference wrong");
|
||||
-- Disable stream IRQ
|
||||
TmemRead32(REG_CONF_IRQENA_ADDR, v, clk, rqst, rsp);
|
||||
v := IntAnd(v, 16#0FE#);
|
||||
TmemWrite32(REG_CONF_IRQENA_ADDR, v, clk, rqst, rsp);
|
||||
TmemRead32(REG_CONF_STRENA_ADDR, v, clk, rqst, rsp);
|
||||
v := IntAnd(v, 16#0FE#);
|
||||
TmemWrite32(REG_CONF_STRENA_ADDR, v, clk, rqst, rsp);
|
||||
Str0Disabled := true;
|
||||
-- Check Values
|
||||
addr := winlast + 1;
|
||||
for i in 256+30+3-99 to 256+30+3 loop
|
||||
StdlvCompareInt (i mod 256, Memory(addr), "Stream0: Wrong value", false);
|
||||
if addr = winend then
|
||||
addr := winstart;
|
||||
else
|
||||
addr := addr + 1;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
print("", PrintStr0_c);
|
||||
Str0LastTs := tslo;
|
||||
Str0NextWin := (Str0NextWin + 1) mod 3;
|
||||
Str0WinCheck := Str0WinCheck + 1;
|
||||
end loop;
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str0Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
HlCheckMaxLvl(0, 0, clk, rqst, rsp);
|
||||
HlSetPostTrig(0, 3, clk, rqst, rsp);
|
||||
HlSetMode(0, VAL_MODE_RECM_CONT, clk, rqst, rsp);
|
||||
HlConfStream( str => 0, bufstart => Str0BufStart_c, ringbuf => true, overwrite => false, wincnt => Str0Windows_c, winsize => Str0WinSize_c,
|
||||
clk => clk, rqst => rqst, rsp => rsp);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str0Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
end;
|
||||
|
||||
end;
|
||||
@ -1,171 +0,0 @@
|
||||
------------------------------------------------------------
|
||||
-- Description
|
||||
------------------------------------------------------------
|
||||
-- Stream 1 works in manual recording mode. The data is arriving
|
||||
-- in bursts (samples back-to-back withing bursts) and does
|
||||
-- not contain any trigger events.
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
||||
package psi_ms_daq_tosca_tb_str1_pkg is
|
||||
|
||||
constant PrintStr1_c : boolean := PrintDefault_c;
|
||||
|
||||
-- Memory
|
||||
constant Str1BufStart_c : integer := 16#2000#;
|
||||
constant Str1WinSize_c : integer := 500;
|
||||
constant Str1Windows_c : integer := 1;
|
||||
alias Memory1 : t_aslv8(0 to Str1WinSize_c*Str1Windows_c) is Memory(Str1BufStart_c to Str1BufStart_c+Str1WinSize_c*Str1Windows_c);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Persistent State
|
||||
--------------------------------------------------------
|
||||
shared variable Str1WinCheck : integer := 0;
|
||||
shared variable Str1DataCnt : integer := 0;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str1Data( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(15 downto 0));
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str1Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str1Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str1Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_tosca_tb_str1_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str1Data( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(15 downto 0)) is
|
||||
begin
|
||||
while now < 10 us loop
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
for i in 0 to 19 loop
|
||||
vld <= '1';
|
||||
for k in 0 to 49 loop
|
||||
data <= std_logic_vector(to_unsigned(Str1DataCnt, 16));
|
||||
Str1DataCnt := Str1DataCnt + 1;
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
vld <= '0';
|
||||
wait for 1 us;
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str1Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
variable curwin : integer;
|
||||
variable wincnt : integer;
|
||||
variable winlast : integer;
|
||||
variable valRead : unsigned(15 downto 0);
|
||||
begin
|
||||
print("------------ Stream 1 Handler ------------", PrintStr1_c);
|
||||
HlGetMaxLvl(1, clk, rqst, rsp, v);
|
||||
print("MAXLVL: " & to_string(v), PrintStr1_c);
|
||||
HlGetPtr(1, clk, rqst, rsp, v);
|
||||
print("PTR: " & to_string(v), PrintStr1_c);
|
||||
HlGetCurWin(1, clk, rqst, rsp, curwin);
|
||||
print("CURWIN: " & to_string(curwin), PrintStr1_c);
|
||||
IntCompare(0, curwin, "Stream1: CURWIN wrong");
|
||||
-- Check window content
|
||||
HlGetWinCnt(1, 0, clk, rqst, rsp, wincnt);
|
||||
print("WINCNT: " & to_string(wincnt), PrintStr1_c);
|
||||
IntCompare(250, wincnt, "Stream1:WINCNT wrong");
|
||||
HlGetWinLast(1, 0, clk, rqst, rsp, winlast);
|
||||
print("WINLAST: " & to_string(winlast), PrintStr1_c);
|
||||
IntCompare(16#2000#+498, winlast, "Stream1:WINLAST wrong");
|
||||
for spl in 0 to 249 loop
|
||||
valRead(7 downto 0) := unsigned(Memory1(spl*2));
|
||||
valRead(15 downto 8) := unsigned(Memory1(spl*2+1));
|
||||
-- first 100 samples are before arming
|
||||
StdlvCompareInt (spl+100, std_logic_vector(valRead), "Stream1:Wrong value", false);
|
||||
end loop;
|
||||
print("", PrintStr1_c);
|
||||
Str1WinCheck := Str1WinCheck + 1;
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str1Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
HlCheckMaxLvl(1, 0, clk, rqst, rsp);
|
||||
HlSetPostTrig(1, 250, clk, rqst, rsp);
|
||||
HlSetMode(1, VAL_MODE_RECM_MANUAL, clk, rqst, rsp);
|
||||
HlConfStream( str => 1, bufstart => Str1BufStart_c, ringbuf => false, overwrite => false, wincnt => Str1Windows_c, winsize => Str1WinSize_c,
|
||||
clk => clk, rqst => rqst, rsp => rsp);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str1Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable Stream1Armed_v : boolean := false;
|
||||
begin
|
||||
-- ARM recorder at required point in time
|
||||
if Str1DataCnt = 99 and not Stream1Armed_v then
|
||||
Stream1Armed_v := true;
|
||||
HlSetMode(1, VAL_MODE_RECM_MANUAL + VAL_MODE_ARM, clk, rqst, rsp);
|
||||
end if;
|
||||
end;
|
||||
|
||||
end;
|
||||
@ -1,208 +0,0 @@
|
||||
------------------------------------------------------------
|
||||
-- Description
|
||||
------------------------------------------------------------
|
||||
-- Stream 2 works in siingle recording mode. The data is arriving
|
||||
-- in bursts (samples back-to-back withing bursts) and does
|
||||
-- contain trigger events at the really begining (sample 0).
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
||||
package psi_ms_daq_tosca_tb_str2_pkg is
|
||||
|
||||
constant PrintStr2_c : boolean := PrintDefault_c;
|
||||
|
||||
-- Memory
|
||||
constant Str2BufStart_c : integer := 16#3000#;
|
||||
constant Str2WinSize_c : integer := 256;
|
||||
constant Str2Windows_c : integer := 3;
|
||||
constant Str2PostTrig_c : integer := 127;
|
||||
alias Memory2 : t_aslv8(0 to Str2WinSize_c*Str2Windows_c) is Memory(Str2BufStart_c to Str2BufStart_c+Str2WinSize_c*Str2Windows_c);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Persistent State
|
||||
--------------------------------------------------------
|
||||
shared variable Str2FrameCnt : integer := 0;
|
||||
shared variable Str2SplCnt : integer := 0;
|
||||
shared variable Str2WinCheck : integer := 0;
|
||||
shared variable Str2ExpFrame : integer := 0;
|
||||
shared variable Stream2Armed_v : boolean := false;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str2Data( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(15 downto 0));
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str2Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str2Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str2Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_tosca_tb_str2_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str2Data( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(15 downto 0)) is
|
||||
begin
|
||||
while now < 8.5 us loop
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
for i in 0 to 19 loop
|
||||
vld <= '1';
|
||||
Str2SplCnt := 0;
|
||||
trig <= '1';
|
||||
for k in 0 to 199 loop
|
||||
data <= std_logic_vector(to_unsigned(Str2FrameCnt*256+Str2SplCnt, 16));
|
||||
Str2SplCnt := Str2SplCnt + 1;
|
||||
wait until rising_edge(clk);
|
||||
trig <= '0';
|
||||
end loop;
|
||||
Str2FrameCnt := Str2FrameCnt + 1;
|
||||
vld <= '0';
|
||||
wait for 1 us;
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str2Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
variable curwin : integer;
|
||||
variable lastwin : integer;
|
||||
variable wincnt : integer;
|
||||
variable spladdr : integer;
|
||||
variable splNr : integer;
|
||||
variable valRead : unsigned(15 downto 0);
|
||||
variable splInWin : integer;
|
||||
variable isTrig : boolean;
|
||||
begin
|
||||
print("------------ Stream 2 Handler ------------", PrintStr2_c);
|
||||
HlGetMaxLvl(2, clk, rqst, rsp, v);
|
||||
print("MAXLVL: " & to_string(v), PrintStr2_c);
|
||||
HlGetPtr(2, clk, rqst, rsp, v);
|
||||
print("PTR: " & to_string(v), PrintStr2_c);
|
||||
HlGetCurWin(2, clk, rqst, rsp, curwin);
|
||||
print("CURWIN: " & to_string(curwin), PrintStr2_c);
|
||||
-- Calculate window to read
|
||||
if curwin = 0 then
|
||||
curwin := Str2Windows_c-1;
|
||||
else
|
||||
curwin := curwin-1;
|
||||
end if;
|
||||
-- Read window data
|
||||
-- Check if recording is finished
|
||||
HlIsTrigWin(2, curwin, clk, rqst, rsp, isTrig);
|
||||
-- Check if window is fully written to memory
|
||||
HlGetLastWin(2, clk, rqst, rsp, lastwin);
|
||||
-- Execute
|
||||
if not isTrig then
|
||||
print("Skipped: not a trigger window", PrintStr2_c);
|
||||
elsif curwin /= lastwin then
|
||||
print("Skipped: not written to memory yet " & str(curwin) & " " & str(lastwin), PrintStr2_c);
|
||||
else
|
||||
-- Check Data (last 128 samples)
|
||||
splNr := Str2PostTrig_c;
|
||||
while splNr >= 0 loop
|
||||
print("check window " & to_string(curwin), PrintStr2_c);
|
||||
HlGetWinLast(2, curwin, clk, rqst, rsp, spladdr);
|
||||
print("WINLAST: " & to_string(spladdr), PrintStr2_c);
|
||||
while (splNr >= 0) and (spladdr >= Str2BufStart_c+curwin*Str2WinSize_c) loop
|
||||
StdlvCompareInt(splNr, Memory(spladdr), "Stream2: Sample " & to_string(Str2ExpFrame) & ":" & to_string(splNr) & " wrong CNT [addr=" & str(spladdr) & "]", false);
|
||||
StdlvCompareInt(Str2ExpFrame, Memory(spladdr+1), "Stream2: Sample " & to_string(Str2ExpFrame) & ":" & to_string(splNr) & " wrong FRAME [addr=" & str(spladdr) & "]", false);
|
||||
spladdr := spladdr - 2;
|
||||
splNr := splNr - 1;
|
||||
end loop;
|
||||
-- Next Window
|
||||
if curwin = 0 then
|
||||
curwin := Str2Windows_c-1;
|
||||
else
|
||||
curwin := curwin-1;
|
||||
end if;
|
||||
end loop;
|
||||
Str2WinCheck := Str2WinCheck + 1;
|
||||
end if;
|
||||
print("", PrintStr2_c);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str2Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
HlCheckMaxLvl(2, 0, clk, rqst, rsp);
|
||||
HlSetPostTrig(2, Str2PostTrig_c, clk, rqst, rsp);
|
||||
HlSetMode(2, VAL_MODE_RECM_SINGLE, clk, rqst, rsp);
|
||||
HlConfStream( str => 2, bufstart => Str2BufStart_c, ringbuf => false, overwrite => true, wincnt => Str2Windows_c, winsize => Str2WinSize_c,
|
||||
clk => clk, rqst => rqst, rsp => rsp);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str2Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
-- ARM Stream 2 after 3 bursts
|
||||
if ((Str2FrameCnt = 2) or (Str2FrameCnt = 12)) and
|
||||
(Str2SplCnt >= 80) and (Str2SplCnt <= 150) and not Stream2Armed_v then
|
||||
Stream2Armed_v := true;
|
||||
HlSetMode(2, VAL_MODE_RECM_SINGLE + VAL_MODE_ARM, clk, rqst, rsp);
|
||||
Str2ExpFrame := Str2FrameCnt + 1;
|
||||
elsif Str2FrameCnt = 11 then
|
||||
Stream2Armed_v := false;
|
||||
end if;
|
||||
end;
|
||||
|
||||
end;
|
||||
@ -1,213 +0,0 @@
|
||||
------------------------------------------------------------
|
||||
-- Description
|
||||
------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Libraries
|
||||
------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library work;
|
||||
use work.psi_common_math_pkg.all;
|
||||
use work.psi_common_array_pkg.all;
|
||||
use work.psi_ms_daq_pkg.all;
|
||||
|
||||
library work;
|
||||
use work.psi_tb_txt_util.all;
|
||||
use work.psi_tb_compare_pkg.all;
|
||||
use work.psi_ms_daq_tosca_tb_pkg.all;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Header
|
||||
------------------------------------------------------------
|
||||
package psi_ms_daq_tosca_tb_str3_pkg is
|
||||
|
||||
constant PrintStr3_c : boolean := PrintDefault_c;
|
||||
|
||||
-- Memory
|
||||
constant Str3BufStart_c : integer := 16#4000#;
|
||||
constant Str3WinSize_c : integer := 1024;
|
||||
constant Str3Windows_c : integer := 3;
|
||||
constant Str3PostTrig_c : integer := 9;
|
||||
constant Str3TrigPos_c : integer := 100;
|
||||
alias Memory3 : t_aslv8(0 to Str3WinSize_c*Str3Windows_c) is Memory(Str3BufStart_c to Str3BufStart_c+Str3WinSize_c*Str3Windows_c);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Persistent State
|
||||
--------------------------------------------------------
|
||||
shared variable Str3ExpFrame : integer := 0;
|
||||
shared variable Str3FrameCnt : integer := 0;
|
||||
shared variable Str3SplCnt : integer := 0;
|
||||
shared variable Str3WinCheck : integer := 0;
|
||||
shared variable Stream3Armed_v : boolean := false;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str3Data( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(31 downto 0));
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str3Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str3Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str3Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t);
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_tosca_tb_str3_pkg is
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Data Generation
|
||||
--------------------------------------------------------
|
||||
procedure Str3Data( signal clk : in std_logic;
|
||||
signal vld : out std_logic;
|
||||
signal trig : out std_logic;
|
||||
signal data : out std_logic_vector(31 downto 0)) is
|
||||
begin
|
||||
while now < 8 us loop
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
for i in 0 to 9 loop
|
||||
vld <= '1';
|
||||
Str3SplCnt := 0;
|
||||
for k in 0 to 999 loop
|
||||
data <= std_logic_vector(to_unsigned(Str3FrameCnt*2**16+Str3SplCnt, 32));
|
||||
if Str3SplCnt = Str3TrigPos_c then
|
||||
trig <= '1';
|
||||
else
|
||||
trig <= '0';
|
||||
end if;
|
||||
Str3SplCnt := Str3SplCnt + 1;
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
Str3FrameCnt := Str3FrameCnt + 1;
|
||||
vld <= '0';
|
||||
wait for 1 us;
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- IRQ Handler
|
||||
--------------------------------------------------------
|
||||
procedure Str3Handler( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
variable v : integer;
|
||||
variable curwin : integer;
|
||||
variable wincnt : integer;
|
||||
variable winlast : integer;
|
||||
variable spladdr : integer;
|
||||
variable splNr : integer;
|
||||
variable valRead : unsigned(15 downto 0);
|
||||
variable splInWin : integer;
|
||||
variable isRecording : boolean;
|
||||
begin
|
||||
print("------------ Stream 3 Handler ------------", PrintStr3_c);
|
||||
HlGetMaxLvl(3, clk, rqst, rsp, v);
|
||||
print("MAXLVL: " & to_string(v), PrintStr3_c);
|
||||
HlGetPtr(3, clk, rqst, rsp, v);
|
||||
print("PTR: " & to_string(v), PrintStr3_c);
|
||||
HlGetCurWin(3, clk, rqst, rsp, curwin);
|
||||
print("CURWIN: " & to_string(curwin), PrintStr3_c);
|
||||
-- Calculate window to read
|
||||
if curwin = 0 then
|
||||
curwin := Str3Windows_c-1;
|
||||
else
|
||||
curwin := curwin-1;
|
||||
end if;
|
||||
-- Check Data from this frame
|
||||
splNr := Str3TrigPos_c+Str3PostTrig_c;
|
||||
-- Read window data (Post-Trigger, from this window)
|
||||
print("check post-trigger", PrintStr3_c);
|
||||
HlGetWinLast(3, curwin, clk, rqst, rsp, winlast);
|
||||
print("WINLAST: " & to_string(winlast), PrintStr3_c);
|
||||
spladdr := winlast;
|
||||
while splNr >= 0 loop
|
||||
StdlvCompareInt(splNr, Memory(spladdr+1) & Memory(spladdr), "Stream3: Sample " & to_string(Str3ExpFrame) & ":" & to_string(splNr) & " wrong CNT", false);
|
||||
StdlvCompareInt(Str3ExpFrame, Memory(spladdr+3) & Memory(spladdr+2), "Stream3: Sample " & to_string(Str3ExpFrame) & ":" & to_string(splNr) & " wrong FRAME", false);
|
||||
-- Wraparound
|
||||
if spladdr = Str3BufStart_c+curwin*Str3WinSize_c then
|
||||
spladdr := Str3BufStart_c+(curwin+1)*Str3WinSize_c-4;
|
||||
-- Normal Counting
|
||||
else
|
||||
spladdr := spladdr - 4;
|
||||
end if;
|
||||
splNr := splNr - 1;
|
||||
end loop;
|
||||
-- Read window data (Pre-Trigger, from last window)
|
||||
print("check pre-trigger", PrintStr3_c);
|
||||
splNr := 999;
|
||||
while spladdr /= winlast loop
|
||||
StdlvCompareInt(splNr, Memory(spladdr+1) & Memory(spladdr), "Stream3: Sample " & to_string(Str3ExpFrame-1) & ":" & to_string(splNr) & " wrong CNT", false);
|
||||
StdlvCompareInt(Str3ExpFrame-1, Memory(spladdr+3) & Memory(spladdr+2), "Stream3: Sample " & to_string(Str3ExpFrame-1) & ":" & to_string(splNr) & " wrong FRAME", false);
|
||||
-- Wraparound
|
||||
if spladdr = Str3BufStart_c+curwin*Str3WinSize_c then
|
||||
spladdr := Str3BufStart_c+(curwin+1)*Str3WinSize_c-4;
|
||||
-- Normal Counting
|
||||
else
|
||||
spladdr := spladdr - 4;
|
||||
end if;
|
||||
splNr := splNr - 1;
|
||||
end loop;
|
||||
|
||||
Str3WinCheck := Str3WinCheck + 1;
|
||||
print("", PrintStr3_c);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Setup
|
||||
--------------------------------------------------------
|
||||
procedure Str3Setup( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
HlCheckMaxLvl(3, 0, clk, rqst, rsp);
|
||||
HlSetPostTrig(3, Str3PostTrig_c, clk, rqst, rsp);
|
||||
HlSetMode(3, VAL_MODE_RECM_TRIGMASK, clk, rqst, rsp);
|
||||
HlConfStream( str => 3, bufstart => Str3BufStart_c, ringbuf => true, overwrite => true, wincnt => Str3Windows_c, winsize => Str3WinSize_c,
|
||||
clk => clk, rqst => rqst, rsp => rsp);
|
||||
end procedure;
|
||||
|
||||
--------------------------------------------------------
|
||||
-- Update
|
||||
--------------------------------------------------------
|
||||
procedure Str3Update( signal clk : in std_logic;
|
||||
signal rqst : out TmemRqst_t;
|
||||
signal rsp : in TmemResp_t) is
|
||||
begin
|
||||
if ((Str3FrameCnt = 2) or (Str3FrameCnt = 7))
|
||||
and not Stream3Armed_v then
|
||||
HlSetMode(3, VAL_MODE_RECM_TRIGMASK + VAL_MODE_ARM, clk, rqst, rsp);
|
||||
Stream3Armed_v := true;
|
||||
Str3ExpFrame := Str3FrameCnt;
|
||||
elsif Str3FrameCnt = 6 then
|
||||
Stream3Armed_v := false;
|
||||
end if;
|
||||
end procedure;
|
||||
|
||||
end;
|
||||
Reference in New Issue
Block a user