FEATURE: Added "IS RECORDING" to status register

hdl/psi_ms_daq.vhd

@@ -106,6 +106,7 @@ architecture rtl of psi_ms_daq is
 	-- Status
 	signal Stat_StrIrq			: std_logic_vector(Streams_g-1 downto 0);
 	signal Stat_IsArmed			: std_logic_vector(Streams_g-1 downto 0);
+	signal Stat_IsRecording		: std_logic_vector(Streams_g-1 downto 0);
 	
 	-- Context Memory Connections
 	signal CtxStr_Cmd			: ToCtxStr_t;
@@ -153,6 +154,7 @@ begin
 			PostTrig	=> Cfg_PostTrig,
 			Arm			=> Cfg_Arm,
 			IsArmed		=> Stat_IsArmed,
+			IsRecording	=> Stat_IsRecording,
 			RecMode		=> Cfg_RecMode
 		);	
 
@@ -190,6 +192,7 @@ begin
 				Mode			=> Cfg_RecMode(str),
 				Arm				=> Cfg_Arm(str),
 				IsArmed			=> Stat_IsArmed(str),
+				IsRecording		=> Stat_IsRecording(str),
 				Daq_Vld			=> InpDma_Vld(str),
 				Daq_Rdy			=> InpDma_Rdy(str),
 				Daq_Data		=> InpDma_Data(str),

hdl/psi_ms_daq_input.vhd

@@ -45,6 +45,7 @@ entity psi_ms_daq_input is
 		Mode			: in	RecMode_t;									-- $$ proc=daq $$
 		Arm				: in	std_logic;									-- $$ proc=stream $$
 		IsArmed			: out	std_logic;									-- $$ proc=stream $$
+		IsRecording		: out	std_logic;									-- $$ proc=stream $$
 		
 		-- DAQ logic Connections
 		Daq_Vld			: out	std_logic;									-- $$ proc=daq $$
@@ -101,8 +102,8 @@ architecture rtl of psi_ms_daq_input is
 	
 	-- clock Crossing Signals
 	signal Str_Arm 		: std_logic;
-	signal StatusCcIn	: std_logic_vector(TlastCntWidth_c downto 0);
-	signal StatusCcOut	: std_logic_vector(TlastCntWidth_c downto 0);
+	signal StatusCcIn	: std_logic_vector(TlastCntWidth_c+1 downto 0);
+	signal StatusCcOut	: std_logic_vector(TlastCntWidth_c+1 downto 0);
 
 	-- Data FIFO signals
 	signal DataFifo_InRdy		: std_logic;
@@ -360,9 +361,10 @@ begin
 	-- Only the reset from Tosca is used since resetting the FIFO during a burst could lead to deadlocks. 
 	StatusCcIn(TlastCntWidth_c-1 downto 0)	<= r.TLastCnt;
 	StatusCcIn(TlastCntWidth_c)				<= r.IsArmed;
+	StatusCcIn(TlastCntWidth_c+1)			<= r.RecEna;
 	i_cc : entity work.psi_common_status_cc
 		generic map (
-			DataWidth_g		=> TlastCntWidth_c+1
+			DataWidth_g		=> TlastCntWidth_c+2
 		)
 		port map (
 			ClkA		=> Str_Clk,
@@ -375,6 +377,7 @@ begin
 		);
 	InTlastCnt 	<= StatusCcOut(TlastCntWidth_c-1 downto 0);
 	IsArmed		<= StatusCcOut(TlastCntWidth_c);
+	IsRecording	<= StatusCcOut(TlastCntWidth_c+1);
 	
 	-- Clock crossing for ARM pulse
 	i_cc_arm : entity work.psi_common_pulse_cc

hdl/psi_ms_daq_reg_tmem.vhd

@@ -43,6 +43,7 @@ entity psi_ms_daq_reg_tmem is
 		PostTrig 		: out	t_aslv32(Streams_g-1 downto 0);
 		Arm				: out 	std_logic_vector(Streams_g-1 downto 0);
 		IsArmed			: in 	std_logic_vector(Streams_g-1 downto 0);
+		IsRecording		: in 	std_logic_vector(Streams_g-1 downto 0);
 		RecMode			: out	t_aslv2(Streams_g-1 downto 0)
 	);	   
 end entity;
@@ -89,7 +90,7 @@ begin
 	--------------------------------------------
 	-- Combinatorial Process
 	--------------------------------------------
-	p_comb : process(	r, TmemRqst, StrIrq, InLevel, IsArmed, CtxStr_Rdval, CtxWin_Rdval)
+	p_comb : process(	r, TmemRqst, StrIrq, InLevel, IsArmed, IsRecording, CtxStr_Rdval, CtxWin_Rdval)
 		variable v 					: two_process_r;
 		variable Stream_v			: integer range 0 to Streams_g-1;
 	begin
@@ -178,6 +179,7 @@ begin
 					end if;
 					v.RegRdval(1 downto 0) 	:= r.Reg_Mode_Recm(Stream_v);
 					v.RegRdval(8) 			:= IsArmed(Stream_v);
+					v.RegRdval(16)			:= IsRecording(Stream_v);
 				end if;
 						
 			end if;