AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add register to control caching behavior on AXI link that performs the dma transfer

Browse Source
This commit is contained in:
schmid_e
2024-08-08 11:53:32 +02:00
parent 16f13e64d7
commit 01de9bd1a9
4 changed files with 57 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
doc/psi_multi_stream_daq.docx
View File

Binary file not shown.

BIN
doc/psi_multi_stream_daq.pdf
View File

Binary file not shown.

33
hdl/psi_ms_daq_axi.vhd
View File

@ -182,6 +182,10 @@ architecture rtl of psi_ms_daq_axi is
signal Cfg_RecMode : t_aslv2(Streams_g - 1 downto 0);
signal Cfg_ToDisable : std_logic_vector(Streams_g -1 downto 0);
signal Cfg_FrameTo : std_logic_vector(Streams_g -1 downto 0);
signal AWCache : t_aslv4(2 downto 0) := (others => (others => '0'));
signal AWProt : t_aslv3(2 downto 0) := (others => (others => '0'));
signal ARCache : t_aslv4(2 downto 0) := (others => (others => '0'));
signal ARProt : t_aslv3(2 downto 0) := (others => (others => '0'));
-- Status
signal Stat_StrIrq : std_logic_vector(Streams_g - 1 downto 0);
signal Stat_StrLastWin : WinType_a(Streams_g - 1 downto 0);
@ -204,6 +208,23 @@ begin
M_Axi_Areset <= not M_Axi_Aresetn;
S_Axi_Areset <= not S_Axi_Aresetn;
-- Sync quasi static vecctors
sync_apc_reg : process(M_Axi_Aclk)
begin
if rising_edge(M_Axi_Aclk) then
for i in 1 to 2 loop
AWProt(i) <= AWProt(i-1);
AWCache(i) <= AWCache(i-1);
ARProt(i) <= ARProt(i-1);
ARCache(i) <= ARCache(i-1);
end loop;
end if;
end process;
M_Axi_AwCache <= AWCache(2);
M_Axi_AwProt <= AWProt(2);
M_Axi_ArCache <= ARCache(2);
M_Axi_ArProt <= ARProt(2);
--------------------------------------------
-- Register Interface
--------------------------------------------
@ -252,6 +273,10 @@ begin
S_Axi_BValid => S_Axi_BValid,
S_Axi_BReady => S_Axi_BReady,
IrqOut => Irq,
AWCache => AWCache(0),
AWProt => AWProt(0),
ARCache => ARCache(0),
ARProt => ARProt(0),
PostTrig => Cfg_PostTrig,
Arm => Cfg_Arm,
IsArmed => Stat_IsArmed,
@ -423,8 +448,8 @@ begin
M_Axi_AwSize => M_Axi_AwSize,
M_Axi_AwBurst => M_Axi_AwBurst,
M_Axi_AwLock => M_Axi_AwLock,
M_Axi_AwCache => M_Axi_AwCache,
M_Axi_AwProt => M_Axi_AwProt,
M_Axi_AwCache => open, --M_Axi_AwCache
M_Axi_AwProt => open, --M_Axi_AwProt
M_Axi_AwValid => M_Axi_AwValid,
M_Axi_AwReady => M_Axi_AwReady,
M_Axi_WData => M_Axi_WData,
@ -440,8 +465,8 @@ begin
M_Axi_ArSize => M_Axi_ArSize,
M_Axi_ArBurst => M_Axi_ArBurst,
M_Axi_ArLock => M_Axi_ArLock,
M_Axi_ArCache => M_Axi_ArCache,
M_Axi_ArProt => M_Axi_ArProt,
M_Axi_ArCache => open, --M_Axi_ArCache
M_Axi_ArProt => open, --M_Axi_ArProt
M_Axi_ArValid => M_Axi_ArValid,
M_Axi_ArReady => M_Axi_ArReady,
M_Axi_RData => M_Axi_RData,

28
hdl/psi_ms_daq_reg_axi.vhd
View File

@ -79,6 +79,10 @@ entity psi_ms_daq_reg_axi is
ToDisable : out std_logic_vector(Streams_g - 1 downto 0);
FrameTo : out std_logic_vector(Streams_g - 1 downto 0);
IrqOut : out std_logic;
AWCache : out std_logic_vector(3 downto 0);
AWProt : out std_logic_vector(2 downto 0);
ARCache : out std_logic_vector(3 downto 0);
ARProt : out std_logic_vector(2 downto 0);
-- Memory Interfae Clock domain control singals
ClkMem : in std_logic;
RstMem : in std_logic;
@ -104,6 +108,10 @@ architecture rtl of psi_ms_daq_reg_axi is
Reg_IrqVec : std_logic_vector(Streams_g - 1 downto 0);
Reg_IrqEna : std_logic_vector(Streams_g - 1 downto 0);
Reg_StrEna : std_logic_vector(Streams_g - 1 downto 0);
Reg_AcpCfg_ARProt : std_logic_vector(2 downto 0);
Reg_AcpCfg_ARCache : std_logic_vector(3 downto 0);
Reg_AcpCfg_AWProt : std_logic_vector(2 downto 0);
Reg_AcpCfg_AWCache : std_logic_vector(3 downto 0);
Reg_PostTrig : t_aslv32(Streams_g - 1 downto 0);
Reg_Mode_Recm : t_aslv2(Streams_g - 1 downto 0);
Reg_Mode_Arm : std_logic_vector(Streams_g - 1 downto 0);
@ -201,6 +209,18 @@ begin
end if;
RegRdVal(16#20# / 4)(Streams_g - 1 downto 0) <= r.Reg_StrEna;
-- STRENA
if RegWr(16#24# / 4) = '1' then
v.Reg_AcpCfg_ARProt := RegWrVal(16#24# / 4)( 2 downto 0);
v.Reg_AcpCfg_ARCache := RegWrVal(16#24# / 4)( 7 downto 4);
v.Reg_AcpCfg_AWProt := RegWrVal(16#24# / 4)(10 downto 8);
v.Reg_AcpCfg_AWCache := RegWrVal(16#24# / 4)(15 downto 12);
end if;
RegRdVal(16#24# / 4)( 2 downto 0) <= r.Reg_AcpCfg_ARProt;
RegRdVal(16#24# / 4)( 7 downto 4) <= r.Reg_AcpCfg_ARCache;
RegRdVal(16#24# / 4)(10 downto 8) <= r.Reg_AcpCfg_AWProt;
RegRdVal(16#24# / 4)(15 downto 12) <= r.Reg_AcpCfg_AWCache;
-- *** Stream Register Accesses ***
v.RegRdval := (others => '0');
v.Reg_Mode_Arm := (others => '0');
@ -296,6 +316,10 @@ begin
RecMode <= r.Reg_Mode_Recm;
ToDisable <= r.Reg_Mode_ToDisable;
FrameTo <= r.Reg_Mode_FrameTo;
ARProt <= r.Reg_AcpCfg_ARProt;
ARCache <= r.Reg_AcpCfg_ARCache;
AWProt <= r.Reg_AcpCfg_AWProt;
AWCache <= r.Reg_AcpCfg_AWCache;
--------------------------------------------
-- Sequential Process
@ -310,6 +334,10 @@ begin
r.Reg_IrqVec <= (others => '0');
r.Reg_IrqEna <= (others => '0');
r.Reg_StrEna <= (others => '0');
r.Reg_AcpCfg_ARProt <= (others => '0');
r.Reg_AcpCfg_ARCache <= (others => '0');
r.Reg_AcpCfg_AWProt <= (others => '0');
r.Reg_AcpCfg_AWCache <= (others => '0');
r.Irq <= '0';
r.Reg_PostTrig <= (others => (others => '0'));
r.Reg_Mode_Recm <= (others => (others => '0'));