AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Implemented test for timestamp handling

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This commit is contained in:
Oliver Bruendler
2018-07-11 11:52:34 +02:00
parent 4c26626d43
commit 53f1b15bd8
6 changed files with 284 additions and 21 deletions
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2
hdl/psi_ms_daq_daq_sm.vhd
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@ -24,7 +24,7 @@ library work;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
-- $$ testcases=single_simple,priorities,single_window,multi_window,enable,irq $$
-- $$ testcases=single_simple,priorities,single_window,multi_window,enable,irq,timestamp $$
-- $$ processes=control,dma_cmd,dma_resp,ctx $$
-- $$ tbpkg=work.psi_tb_txt_util,work.psi_tb_compare_pkg $$
entity psi_ms_daq_daq_sm is

1
sim/config.tcl
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@ -53,6 +53,7 @@ add_sources "../tb" {
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_multi_window.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_enable.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_irq.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_timestamp.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd \
} -tag tb

28
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb.vhd
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@ -29,6 +29,7 @@ library work;
use work.psi_ms_daq_daq_sm_tb_case_multi_window.all;
use work.psi_ms_daq_daq_sm_tb_case_enable.all;
use work.psi_ms_daq_daq_sm_tb_case_irq.all;
use work.psi_ms_daq_daq_sm_tb_case_timestamp.all;
------------------------------------------------------------
-- Entity Declaration
@ -146,6 +147,9 @@ begin
-- irq
NextCase <= 5;
wait until ProcessDone = AllProcessesDone_c;
-- timestamp
NextCase <= 6;
wait until ProcessDone = AllProcessesDone_c;
TbRunning <= false;
wait;
end process;
@ -210,6 +214,12 @@ begin
work.psi_ms_daq_daq_sm_tb_case_irq.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
-- timestamp
wait until NextCase = 6;
ProcessDone(TbProcNr_control_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_timestamp.control(Clk, Rst, GlbEna, StrEna, StrIrq, Inp_HasLast, Inp_Level, Ts_Vld, Ts_Rdy, Ts_Data, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_control_c) <= '1';
wait;
end process;
@ -252,6 +262,12 @@ begin
work.psi_ms_daq_daq_sm_tb_case_irq.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
-- timestamp
wait until NextCase = 6;
ProcessDone(TbProcNr_dma_cmd_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_timestamp.dma_cmd(Clk, StrIrq, Dma_Cmd, Dma_Cmd_Vld, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_cmd_c) <= '1';
wait;
end process;
@ -294,6 +310,12 @@ begin
work.psi_ms_daq_daq_sm_tb_case_irq.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
-- timestamp
wait until NextCase = 6;
ProcessDone(TbProcNr_dma_resp_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_timestamp.dma_resp(Clk, StrIrq, Dma_Resp, Dma_Resp_Vld, Dma_Resp_Rdy, TfDone, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_dma_resp_c) <= '1';
wait;
end process;
@ -336,6 +358,12 @@ begin
work.psi_ms_daq_daq_sm_tb_case_irq.ctx(Clk, CtxStr_Cmd, CtxStr_Resp, CtxWin_Cmd, CtxWin_Resp, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_ctx_c) <= '1';
-- timestamp
wait until NextCase = 6;
ProcessDone(TbProcNr_ctx_c) <= '0';
work.psi_ms_daq_daq_sm_tb_case_timestamp.ctx(Clk, CtxStr_Cmd, CtxStr_Resp, CtxWin_Cmd, CtxWin_Resp, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_ctx_c) <= '1';
wait;
end process;

6
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_enable.vhd
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@ -133,7 +133,7 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
ControlWaitCompl(Clk);
-- Start with Sample 0, Window 0 after enable (global)
print("Start with Sample 0, Window 0 after enable (global)");
print(">> Start with Sample 0, Window 0 after enable (global)");
InitTestCase(Clk, Rst);
TestCase := 3;
for i in 0 to 2 loop
@ -157,7 +157,7 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
-- Start with Sample 0, Window 0 after enable (per stream)
-- only reset stream 0
print("Start with Sample 0, Window 0 after enable (per stream)");
print(">> Start with Sample 0, Window 0 after enable (per stream)");
InitTestCase(Clk, Rst);
TestCase := 4;
for i in 0 to 2 loop
@ -180,7 +180,7 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
ControlWaitCompl(Clk);
-- 4k Boundary (is 4k boundary reset correctly for the first sample)
print("4k Boundary");
print(">> 4k Boundary");
InitTestCase(Clk, Rst);
TestCase := 5;
Inp_Level(0) <= LvlThreshold_c;

229
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_timestamp.vhd Normal file
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@ -0,0 +1,229 @@
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_common_logic_pkg.all;
use work.psi_common_array_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_daq_sm_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_daq_sm_tb_case_timestamp is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
signal Ts_Rdy : in std_logic_vector;
signal Ts_Data : inout t_aslv64;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t);
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t);
procedure ctx (
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : inout FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_daq_sm_tb_case_timestamp is
procedure control (
signal Clk : in std_logic;
signal Rst : inout std_logic;
signal GlbEna : inout std_logic;
signal StrEna : inout std_logic_vector;
signal StrIrq : in std_logic_vector;
signal Inp_HasLast : inout std_logic_vector;
signal Inp_Level : inout t_aslv16;
signal Ts_Vld : inout std_logic_vector;
signal Ts_Rdy : in std_logic_vector;
signal Ts_Data : inout t_aslv64;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
print(">> -- timestamp --");
-- Timestamp handling
print(">> Timestamp handling");
InitTestCase(Clk, Rst);
TestCase := 0;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(2) <= LvlThreshold_c;
for i in 0 to 4 loop
Ts_Data <= (0 to 3 => (others => '0'));
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
if i = 2 or i = 4 then
Ts_Vld(2) <= '1';
Ts_Data(2) <= std_logic_vector(to_unsigned(i*256, 64));
wait until rising_edge(Clk) and Ts_Rdy(2) = '1';
CheckLastActivity(Ts_Rdy(0), 10 us, 0);
CheckLastActivity(Ts_Rdy(1), 10 us, 0);
CheckLastActivity(Ts_Rdy(3), 10 us, 0);
Ts_Data(2) <= (others => '0');
end if;
end loop;
Ts_Vld(2) <= '0';
Inp_Level(2) <= (others => '0');
ControlWaitCompl(Clk);
-- timestamp on different stream has no effect
print(">> timestamp on different stream has no effect");
InitTestCase(Clk, Rst);
TestCase := 1;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(2) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Ts_Vld(0) <= '1';
Ts_Data(2) <= std_logic_vector(to_unsigned(256, 64));
Ts_Data(0) <= std_logic_vector(to_unsigned(256, 64));
wait for 1 us;
Ts_Data(2) <= std_logic_vector(to_unsigned(0, 64));
Ts_Data(0) <= std_logic_vector(to_unsigned(0, 64));
Ts_Vld(0) <= '0';
Inp_Level(2) <= (others => '0');
ControlWaitCompl(Clk);
end procedure;
procedure dma_cmd (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Cmd : in DaqSm2DaqDma_Cmd_t;
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Timestamp handling
WaitForCase(0, Clk);
-- First window without trigger
ExpectDmaCmdAuto( Stream => 2, MaxSize => 4096, Msg => "Wr0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 2, MaxSize => 4096, Msg => "Wr0.1", NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- second window trigger in first access
ExpectDmaCmdAuto( Stream => 2, MaxSize => 4096, ExeSize=> 512, Msg => "Wr1.0", NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
-- third window trigger in second access
ExpectDmaCmdAuto( Stream => 2, MaxSize => 4096, Msg => "Wr2.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 2, MaxSize => 4096, ExeSize=> 512, Msg => "Wr2.1", NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- timestamp on different stream has no effect
WaitForCase(1, Clk);
ExpectDmaCmdAuto( Stream => 2, MaxSize => 4096, ExeSize=> 512, NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
end procedure;
procedure dma_resp (
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector;
signal Dma_Resp : inout DaqDma2DaqSm_Resp_t;
signal Dma_Resp_Vld : inout std_logic;
signal Dma_Resp_Rdy : in std_logic;
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
begin
-- Timestamp handling
WaitForCase(0, Clk);
-- First window without trigger
ApplyDmaRespAuto( Stream => 2, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaRespAuto( Stream => 2, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
-- second window trigger in first access
ApplyDmaRespAuto( Stream => 2, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
-- third window trigger in second access
ApplyDmaRespAuto( Stream => 2, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ApplyDmaRespAuto( Stream => 2, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ProcDone(1) := '1';
-- timestamp on different stream has no effect
WaitForCase(1, Clk);
ApplyDmaRespAuto( Stream => 2, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
ProcDone(1) := '1';
end procedure;
procedure ctx (
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
signal CtxStr_Resp : inout FromCtx_t;
signal CtxWin_Cmd : in ToCtxWin_t;
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t) is
begin
-- Timestamp handling
WaitForCase(0, Clk);
-- First window without trigger
ExpCtxFullBurstAuto( Stream => 2, Msg => "Wr0.0", WriteTs => CheckNotWritten,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxFullBurstAuto( Stream => 2, Msg => "Wr0.1", NextWin => true, WriteTs => CheckWritten, Timstamp => X"FFFFFFFFFFFFFFFF", -- without trigger, no timestamp is sampled
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- second window trigger in first access
ExpCtxFullBurstAuto( Stream => 2, Msg => "Wr1.0", NextWin => true, WriteTs => CheckWritten, Timstamp => X"0000000000000200",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
-- third window trigger in second access
ExpCtxFullBurstAuto( Stream => 2, Msg => "Wr2.0", WriteTs => CheckNotWritten,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxFullBurstAuto( Stream => 2, Msg => "Wr2.1", NextWin => true, WriteTs => CheckWritten, Timstamp => X"0000000000000400",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- timestamp on different stream has no effect
WaitForCase(1, Clk);
ExpCtxFullBurstAuto( Stream => 2, Msg => "Wr0.1", NextWin => true, WriteTs => CheckWritten, Timstamp => X"FFFFFFFFFFFFFFFF", -- No Timestamp available
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
end procedure;
end;

39
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_pkg.vhd
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@ -63,6 +63,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
-- Low Level Test Functions
------------------------------------------------------------
shared variable DmaCmdOpen : integer := 0;
type CheckTs_t is (CheckWritten, CheckNotWritten, DontCheck);
procedure ExpCtxRead( Stream : in integer;
BufStart : in integer := 16#01230000#;
@ -92,7 +93,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
WinNext : in integer := -1;
SamplesWin : in integer;
WinLast : in integer;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -110,7 +111,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
Wincnt : in integer := 2;
Wincur : in integer := 0;
SamplesWinBefore : in integer;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
variable PtrAfter : out integer;
signal Clk : in std_logic;
@ -131,7 +132,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
Wincnt : in integer := 2;
Wincur : in integer := 0;
SamplesWinBefore : in integer;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
variable PtrAfter : out integer;
signal Clk : in std_logic;
@ -196,7 +197,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
procedure ExpCtxUpdateAuto( Stream : in integer;
NextWin : in boolean := false;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -207,7 +208,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
procedure ExpCtxFullBurstAuto( Stream : in integer;
NextWin : in boolean := false;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -363,7 +364,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
WinNext : in integer := -1;
SamplesWin : in integer;
WinLast : in integer;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -395,22 +396,26 @@ package body psi_ms_daq_daq_sm_tb_pkg is
StdlvCompareInt(SamplesWin, CtxWin_Cmd.WdatLo, "ExpectContext.Str: Wrong WIN_WINCNT - " & Msg);
StdlvCompareInt(WinLast, CtxWin_Cmd.WdatHi, "ExpectContext.Str: Wrong WIN_WINLAST - " & Msg);
wait until rising_edge(Clk) and CtxStr_Cmd.WenHi = '1';
-- Stream
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 1 - " & Msg);
StdlvCompareStdlv(CtxStr_Sel_WinsizePtr_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 1) - " & Msg);
StdlCompare(0, CtxStr_Cmd.WenLo, "ExpectContext.Str: WenLo asserted in second cycle (WinSize overwritten) - " & Msg);
StdlvCompareInt(Ptr, CtxStr_Cmd.WdatHi, "ExpectContext.Str: Wrong PTR - " & Msg);
wait until rising_edge(Clk) and CtxStr_Cmd.WenLo = '1';
if WriteTs then
StdlvCompareInt(Ptr, CtxStr_Cmd.WdatHi, "ExpectContext.Str: Wrong PTR - " & Msg);
-- Window
if WriteTs = CheckWritten then
IntCompare(Stream, CtxWin_Cmd.Stream, "ExpectContext.Win: Wrong stream number 1 - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo not asserted in second cycle - " & Msg);
IntCompare(Wincur, CtxWin_Cmd.Window, "ExpectContext.Win: Wrong Window number 1 - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo not asserted in scond cycle - " & Msg);
StdlCompare(1, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi not asserted in second cycle - " & Msg);
StdlvCompareStdlv(Timstamp(31 downto 0), CtxWin_Cmd.WdatLo, "ExpectContext.Str: Wrong TS-LO - " & Msg);
StdlvCompareStdlv(Timstamp(63 downto 32), CtxWin_Cmd.WdatHi, "ExpectContext.Str: Wrong TS-HI - " & Msg);
else
StdlCompare(0, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo asserted in second cycle (without TS) - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi asserted in second cycle (without TS) - " & Msg);
elsif WriteTs = CheckNotWritten then
StdlCompare(0, CtxWin_Cmd.WenLo, "ExpectContext.Win: WenLo asserted in scond cycle (without TS) - " & Msg);
StdlCompare(0, CtxWin_Cmd.WenHi, "ExpectContext.Win: WenHi asserted in scond cycle (without TS) - " & Msg);
end if;
wait until rising_edge(Clk) and CtxStr_Cmd.WenLo = '1';
-- Stream
IntCompare(Stream, CtxStr_Cmd.Stream, "ExpectContext.Str: Wrong stream number 2 - " & Msg);
StdlvCompareStdlv(CtxStr_Sel_Winend_c, CtxStr_Cmd.Sel, "ExpectContext.Str: Wrong Sel (unexpected sequence 2) - " & Msg);
@ -429,7 +434,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
Wincnt : in integer := 2;
Wincur : in integer := 0;
SamplesWinBefore : in integer;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
variable PtrAfter : out integer;
signal Clk : in std_logic;
@ -517,7 +522,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
Wincnt : in integer := 2;
Wincur : in integer := 0;
SamplesWinBefore : in integer;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
variable PtrAfter : out integer;
signal Clk : in std_logic;
@ -666,7 +671,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
procedure ExpCtxUpdateAuto( Stream : in integer;
NextWin : in boolean := false;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;
@ -720,7 +725,7 @@ package body psi_ms_daq_daq_sm_tb_pkg is
procedure ExpCtxFullBurstAuto( Stream : in integer;
NextWin : in boolean := false;
WriteTs : in boolean := false;
WriteTs : in CheckTs_t := DontCheck;
Timstamp : in std_logic_vector(63 downto 0) := (others => 'X');
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;