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DEVEL: Tested IRQ functionality

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This commit is contained in:
Oliver Bruendler
2018-07-11 10:58:02 +02:00
parent cca1c36361
commit 4c26626d43
2 changed files with 310 additions and 5 deletions
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275
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_irq.vhd
View File

@ -83,7 +83,81 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure CONTROL: No Content added yet!" severity warning;
print(">> -- irq --");
-- Normal Order
print(">> Normal Order");
InitTestCase(Clk, Rst);
TestCase := 0;
ConfigureAuto( WinSize => 4096, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
ControlWaitCompl(Clk);
-- Flipped Order
print(">> Flipped Order");
InitTestCase(Clk, Rst);
TestCase := 1;
ConfigureAuto( WinSize => 4096, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
ControlWaitCompl(Clk);
-- IRQ FIFO full
-- ... FIFO is full after Streams (4) x 3 = 12 open transfers
print(">> IRQ FIFO full");
InitTestCase(Clk, Rst);
TestCase := 2;
ConfigureAuto( WinSize => 4096, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(0) <= LvlThreshold_c;
-- Fill FIFO
for i in 0 to 11 loop
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
end loop;
-- Checked transfer
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
ControlWaitCompl(Clk);
-- Multi-Stream
print(">> Multi-Stream");
InitTestCase(Clk, Rst);
TestCase := 3;
ConfigureAuto( WinSize => 4096, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
for i in 3 downto 0 loop
Inp_Level(i) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(i) <= (others => '0');
wait for 200 ns;
end loop;
ControlWaitCompl(Clk);
-- Win-Change without trigger
print(">> Win-Change without trigger");
InitTestCase(Clk, Rst);
TestCase := 4;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
ControlWaitCompl(Clk);
-- No IRQ on Ringbuf Wrap
print(">> No IRQ on Ringbuf Wrap");
InitTestCase(Clk, Rst);
TestCase := 5;
ConfigureAuto( WinSize => 4096*2, Ringbuf => '1', Overwrite => '1', Wincnt => 2, Wincur => 0);
Inp_Level(0) <= LvlThreshold_c;
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
wait until rising_edge(Clk) and Dma_Cmd_Vld = '1';
Inp_Level(0) <= (others => '0');
ControlWaitCompl(Clk);
end procedure;
procedure dma_cmd (
@ -93,7 +167,59 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
signal Dma_Cmd_Vld : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure DMA_CMD: No Content added yet!" severity warning;
-- Normal Order
WaitForCase(0, Clk);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, ExeSize=> 512, Msg => "Wr0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- Flipped Order
WaitForCase(1, Clk);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, ExeSize=> 512, Msg => "Wr0.0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- IRQ FIFO full
WaitForCase(2, Clk);
-- Fill FIFO
for i in 0 to 11 loop
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, ExeSize=> 512, Msg => "Wr" & to_string(i), NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
end loop;
-- Checked transfer
CheckNoActivity(Dma_Cmd_Vld, 1 us, 0, "Full");
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, ExeSize=> 512, Msg => "Wr12", NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- Multi-Stream
WaitForCase(3, Clk);
for i in 3 downto 0 loop
ExpectDmaCmdAuto( Stream => i, MaxSize => 4096, ExeSize=> 512*i, Msg => "Wr" & to_string(i), NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
end loop;
ProcDone(2) := '1';
-- Win-Change without trigger
WaitForCase(4, Clk);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, Msg => "Wr0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, Msg => "Wr0", NextWin => true,
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, Msg => "Wr0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
-- No IRQ on Ringbuf Wrap
WaitForCase(5, Clk);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, Msg => "Wr0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, Msg => "Wr0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ExpectDmaCmdAuto( Stream => 0, MaxSize => 4096, Msg => "Wr0",
Clk => Clk, Dma_Cmd => Dma_Cmd, Dma_Vld => Dma_Cmd_Vld);
ProcDone(2) := '1';
end procedure;
procedure dma_resp (
@ -105,7 +231,99 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
signal TfDone : inout std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure DMA_RESP: No Content added yet!" severity warning;
-- Normal Order
WaitForCase(0, Clk);
ApplyDmaRespAuto( Stream => 0, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
wait for 200 ns;
StdlvCompareStdlv ("0000", StrIrq, "IRQs asserted unexpectedly");
assert StrIrq'last_event > 200 ns report "###ERROR###: IRQs not idle" severity error;
AssertTfDone(Clk, TfDone);
CheckIrq(MaxWait => (1 us), Stream => 0, Clk => Clk, StrIrq => StrIrq);
ProcDone(1) := '1';
-- Flipped Order
WaitForCase(1, Clk);
AssertTfDone(Clk, TfDone);
wait for 200 ns;
StdlvCompareStdlv ("0000", StrIrq, "IRQs asserted unexpectedly");
assert StrIrq'last_event > 200 ns report "###ERROR###: IRQs not idle" severity error;
ApplyDmaRespAuto( Stream => 0, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
CheckIrq(MaxWait => (1 us), Stream => 0, Clk => Clk, StrIrq => StrIrq);
ProcDone(1) := '1';
-- IRQ FIFO full
WaitForCase(2, Clk);
-- Fill FIFO
for i in 0 to 11 loop
ApplyDmaRespAuto( Stream => 0, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
-- Wait
wait for 1.1 us;
-- Send IRQs
for i in 0 to 11 loop
AssertTfDone(Clk, TfDone);
CheckIrq(MaxWait => (1 us), Stream => 0, Clk => Clk, StrIrq => StrIrq);
end loop;
-- Last transfer
ApplyDmaRespAuto( Stream => 0, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckIrq(MaxWait => (1 us), Stream => 0, Clk => Clk, StrIrq => StrIrq);
ProcDone(1) := '1';
-- Multi-Stream
WaitForCase(3, Clk);
for i in 3 downto 0 loop
ApplyDmaRespAuto( Stream => i, Trigger => '1',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
end loop;
for i in 3 downto 0 loop
AssertTfDone(Clk, TfDone);
CheckIrq(MaxWait => (1 us), Stream => i, Clk => Clk, StrIrq => StrIrq);
end loop;
ProcDone(1) := '1';
-- Win-Change without trigger
WaitForCase(4, Clk);
wait for 100 ns;
ApplyDmaRespAuto( Stream => 0, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckNoActivityStlv(StrIrq, 100 ns, 0, "Before Window Change");
wait for 100 ns;
ApplyDmaRespAuto( Stream => 0, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckIrq(MaxWait => (1 us), Stream => 0, Clk => Clk, StrIrq => StrIrq);
wait for 100 ns;
ApplyDmaRespAuto( Stream => 0, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckNoActivityStlv(StrIrq, 100 ns, 0, "After Window Change");
ProcDone(1) := '1';
-- No IRQ on Ringbuf Wrap
WaitForCase(5, Clk);
wait for 100 ns;
ApplyDmaRespAuto( Stream => 0, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckNoActivityStlv(StrIrq, 100 ns, 0, "Before Wrap");
wait for 100 ns;
ApplyDmaRespAuto( Stream => 0, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckNoActivityStlv(StrIrq, 100 ns, 0, "Wrap");
wait for 100 ns;
ApplyDmaRespAuto( Stream => 0, Trigger => '0',
Clk => Clk, Dma_Resp => Dma_Resp, Dma_Resp_Vld => Dma_Resp_Vld, Dma_Resp_Rdy => Dma_Resp_Rdy);
AssertTfDone(Clk, TfDone);
CheckNoActivityStlv(StrIrq, 100 ns, 0, "After Wrap");
ProcDone(1) := '1';
end procedure;
procedure ctx (
@ -116,7 +334,56 @@ package body psi_ms_daq_daq_sm_tb_case_irq is
signal CtxWin_Resp : inout FromCtx_t;
constant Generics_c : Generics_t) is
begin
assert false report "Case IRQ Procedure CTX: No Content added yet!" severity warning;
-- Normal Order
WaitForCase(0, Clk);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.0", NextWin => true,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- Flipped Order
WaitForCase(1, Clk);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.0", NextWin => true,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- IRQ FIFO full
WaitForCase(2, Clk);
for i in 0 to 11 loop
ExpCtxFullBurstAuto( Stream => 0, NextWin => true,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
end loop;
ExpCtxFullBurstAuto( Stream => 0, NextWin => true,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- Multi-Stream
WaitForCase(3, Clk);
for i in 3 downto 0 loop
ExpCtxFullBurstAuto( Stream => i, NextWin => true,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
end loop;
ProcDone(0) := '1';
-- Win-Change without trigger
WaitForCase(4, Clk);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.1", NextWin => true,
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr1.0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
-- No IRQ on Ringbuf Wrap
WaitForCase(5, Clk);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.0",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.1",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ExpCtxFullBurstAuto( Stream => 0, Msg => "Wr0.2",
Clk => Clk, CtxStr_Cmd => CtxStr_Cmd, CtxStr_Resp => CtxStr_Resp, CtxWin_Cmd => CtxWin_Cmd, CtxWin_Resp => CtxWin_Resp);
ProcDone(0) := '1';
end procedure;
end;

40
tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_pkg.vhd
View File

@ -58,7 +58,7 @@ package psi_ms_daq_daq_sm_tb_pkg is
procedure WaitForCase( SubCase : in integer;
signal Clk : in std_logic);
------------------------------------------------------------
-- Low Level Test Functions
------------------------------------------------------------
@ -159,6 +159,16 @@ package psi_ms_daq_daq_sm_tb_pkg is
signal Dma_Resp_Vld : out std_logic;
signal Dma_Resp_Rdy : in std_logic;
Msg : in string := "");
procedure AssertTfDone( signal Clk : in std_logic;
signal TfDone : out std_logic);
procedure CheckIrq( MaxWait : in time := 1 us; -- Maximum time to wait for the IRQ
Stream : in integer;
Msg : in string := "";
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector(3 downto 0));
------------------------------------------------------------
-- High Level (Auto) Functions
@ -601,6 +611,34 @@ package body psi_ms_daq_daq_sm_tb_pkg is
DmaCmdOpen := DmaCmdOpen - 1;
end procedure;
procedure AssertTfDone( signal Clk : in std_logic;
signal TfDone : out std_logic) is
begin
wait until rising_edge(Clk);
TfDone <= '1';
wait until rising_edge(Clk);
TfDone <= '0';
end procedure;
procedure CheckIrq( MaxWait : in time := 1 us; -- Maximum time to wait for the IRQ
Stream : in integer;
Msg : in string := "";
signal Clk : in std_logic;
signal StrIrq : in std_logic_vector(3 downto 0)) is
variable IrqMask_v : std_logic_vector(StrIrq'range);
variable IdleTimePrior_v : time;
variable ProcStartTime_v : time;
begin
ProcStartTime_v := now;
IrqMask_v := (others => '0');
IrqMask_v(Stream) := '1';
wait until rising_edge(Clk);
wait until (StrIrq = IrqMask_v) and rising_edge(Clk) for MaxWait;
StdlvCompareStdlv (IrqMask_v, StrIrq, "IRQ was not asserted - " & Msg);
wait until rising_edge(Clk);
StdlvCompareInt (0, StrIrq, "IRQ was not deasserted - " & Msg);
end procedure;
procedure ExpCtxReadAuto( Stream : in integer;
signal Clk : in std_logic;
signal CtxStr_Cmd : in ToCtxStr_t;