AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Implemented different input modes

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This commit is contained in:
Oliver Bruendler
2018-07-12 11:45:14 +02:00
parent 8f553f3601
commit 140d5c17e1
5 changed files with 146 additions and 23 deletions
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doc/psi_multi_stream_daq.docx
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65
hdl/psi_ms_daq_input.vhd
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@ -71,6 +71,7 @@ architecture rtl of psi_ms_daq_input is
-- Constants
constant TimeoutLimit_c : integer := integer(StreamClkFreq_g*StreamTimeout_g)-1;
constant WconvFactor_c : positive := 64/StreamWidth_g;
constant TlastCntWidth_c : positive := log2ceil(StreamBuffer_g) + 1;
-- Two process method
type two_process_r is record
@ -86,7 +87,7 @@ architecture rtl of psi_ms_daq_input is
TimeoutCnt : integer range 0 to TimeoutLimit_c;
Timeout : std_logic;
PostTrigCnt : unsigned(31 downto 0);
TLastCnt : std_logic_vector(log2ceil(StreamBuffer_g) downto 0);
TLastCnt : std_logic_vector(TlastCntWidth_c-1 downto 0);
TsLatch : std_logic_vector(63 downto 0);
TsOverflow : std_logic;
HasTlastSync : std_logic_vector(0 to 1);
@ -97,6 +98,11 @@ architecture rtl of psi_ms_daq_input is
-- General Instantiation signals
signal Str_Rst : std_logic;
-- clock Crossing Signals
signal Str_Arm : std_logic;
signal StatusCcIn : std_logic_vector(TlastCntWidth_c downto 0);
signal StatusCcOut : std_logic_vector(TlastCntWidth_c downto 0);
-- Data FIFO signals
signal DataFifo_InRdy : std_logic;
@ -110,8 +116,8 @@ architecture rtl of psi_ms_daq_input is
signal Ts_Vld_I : std_logic;
-- Signal output side TLAST handling
signal OutTlastCnt : std_logic_vector(log2ceil(StreamBuffer_g) downto 0);
signal InTlastCnt : std_logic_vector(log2ceil(StreamBuffer_g) downto 0);
signal OutTlastCnt : std_logic_vector(TlastCntWidth_c-1 downto 0);
signal InTlastCnt : std_logic_vector(TlastCntWidth_c-1 downto 0);
-- Timestamp FIFO signals
signal TsFifo_InRdy : std_logic;
@ -125,7 +131,7 @@ begin
-- Combinatorial Process
--------------------------------------------
p_comb : process( r,
Str_Vld, Str_Data, Str_Trig, Str_Ts, PostTrigSpls, Daq_Rdy, Ts_Rdy, Mode, Arm,
Str_Vld, Str_Data, Str_Trig, Str_Ts, PostTrigSpls, Daq_Rdy, Ts_Rdy, Mode, Str_Arm,
DataFifo_InRdy, DataFifo_InData, DataFifo_OutData, Daq_Vld_I, Daq_Data_I, Daq_HasLast_I, Ts_Vld_I, OutTlastCnt, TsFifo_AlmFull, TsFifo_Empty,
InTlastCnt, TsFifo_InRdy, TsFifo_RdData)
variable v : two_process_r;
@ -145,7 +151,7 @@ begin
v.DataFifoIsTo := '0';
v.DataFifoIsTrig := '0';
v.ModeReg := Mode;
v.ArmReg := Arm;
v.ArmReg := Str_Arm;
-- Masking trigger according to recording mode
case r.ModeReg is
@ -190,22 +196,23 @@ begin
v.TsLatch := Str_Ts;
end if;
end if;
end if;
end if;
-- Trigger handling and post trigger counter
if ProcessSample_v then
if ProcessSample_v and r.RecEna = '1' then
if r.PostTrigCnt /= 0 then
v.PostTrigCnt := r.PostTrigCnt - 1;
if r.PostTrigCnt = 1 then
v.DataFifoIsTrig := '1';
v.DataFifoVld := '1';
v.DataFifoVld := r.DataFifoVld or r.RecEna;
v.RecEna := '0'; -- stop recording after frame
end if;
elsif (r.TrigLatch = '1') or (TrigMasked_v = '1') then
-- Handle incoming trigger sample
if unsigned(PostTrigSpls) = 0 then
v.DataFifoIsTrig := '1';
v.DataFifoVld := '1';
v.DataFifoVld := r.DataFifoVld or r.RecEna;
v.RecEna := '0'; -- stop recording after frame
else
v.PostTrigCnt := unsigned(PostTrigSpls);
end if;
@ -231,16 +238,16 @@ begin
-- Write because timeout occured (only if data is stuck in conversion)
if r.Timeout = '1' then
v.DataFifoVld := '1';
v.DataFifoVld := r.DataFifoVld or r.RecEna;
v.DataFifoIsTo := '1';
v.Timeout := '0'; -- reser timeout after data was flushed to the FIFO
end if;
-- Process input data
if ProcessSample_v then
if ProcessSample_v and r.RecEna = '1' then
v.WordCnt := r.WordCnt + 1;
-- Write because 64-bits are ready
if r.WordCnt = WconvFactor_c-1 then
v.DataFifoVld := '1';
v.DataFifoVld := r.DataFifoVld or r.RecEna;
end if;
v.DataSftReg(to_integer(r.WordCnt+1)*StreamWidth_g-1 downto to_integer(r.WordCnt)*StreamWidth_g) := Str_Data;
end if;
@ -282,20 +289,20 @@ begin
when RecMode_SingleShot_c |
RecMode_ManuelMode_c =>
-- enable on arming (disable happens after recording)
if v.IsArmed = '1' then
if v.ArmReg = '1' then
v.RecEna := '1';
end if;
when others => null;
end case;
if r.ModeReg /= Mode then
v.RecEna := '0';
end if;
-- *** Assign to signal ***
r_next <= v;
end process;
-- *** Registered Outputs ***
IsArmed <= r.IsArmed;
--------------------------------------------
-- Sequential Process
--------------------------------------------
@ -351,18 +358,36 @@ begin
--------------------------------------------
-- Clock crossing for reset and TLAST counter
-- Only the reset from Tosca is used since resetting the FIFO during a burst could lead to deadlocks.
StatusCcIn(TlastCntWidth_c-1 downto 0) <= r.TLastCnt;
StatusCcIn(TlastCntWidth_c) <= r.IsArmed;
i_cc : entity work.psi_common_status_cc
generic map (
DataWidth_g => log2ceil(StreamBuffer_g) + 1
DataWidth_g => TlastCntWidth_c+1
)
port map (
ClkA => Str_Clk,
RstInA => '0',
RstOutA => Str_Rst,
DataA => r.TLastCnt,
DataA => StatusCcIn,
ClkB => Clk,
RstInB => Rst,
DataB => InTlastCnt
DataB => StatusCcOut
);
InTlastCnt <= StatusCcOut(TlastCntWidth_c-1 downto 0);
IsArmed <= StatusCcOut(TlastCntWidth_c);
-- Clock crossing for ARM pulse
i_cc_arm : entity work.psi_common_pulse_cc
generic map (
NumPulses_g => 1
)
port map (
ClkA => Clk,
RstInA => Rst,
PulseA(0) => Arm,
ClkB => Str_Clk,
RstInB => Str_Rst,
PulseB(0) => Str_Arm
);
-- Data FIFO

1
sim/config.tcl
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@ -15,6 +15,7 @@ run_suppress 8684,3479,3813,8009,3812
add_sources $LibPath {
psi_tb/hdl/psi_tb_txt_util.vhd \
psi_tb/hdl/psi_tb_compare_pkg.vhd \
psi_tb/hdl/psi_tb_activity_pkg.vhd \
psi_common/hdl/psi_common_array_pkg.vhd \
psi_common/hdl/psi_common_math_pkg.vhd \
psi_common/hdl/psi_common_logic_pkg.vhd \

101
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_modes.vhd
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@ -14,6 +14,8 @@ library work;
library work;
use work.psi_tb_txt_util.all;
use work.psi_tb_compare_pkg.all;
use work.psi_tb_activity_pkg.all;
------------------------------------------------------------
-- Package Header
@ -46,6 +48,9 @@ package psi_ms_daq_input_tb_case_modes is
signal Ts_Data : in std_logic_vector;
constant Generics_c : Generics_t);
shared variable TestCase : integer := -1;
shared variable StrDone : boolean := false;
end package;
------------------------------------------------------------
@ -64,7 +69,54 @@ package body psi_ms_daq_input_tb_case_modes is
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case MODES Procedure STREAM: No Content added yet!" severity warning;
-- Trigger Mask Mode
while TestCase /= 0 loop
wait until rising_edge(Str_Clk);
end loop;
wait for 100 ns;
-- Recorded but trigger lost
ApplyStrData(5, 1, 1, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts);
-- Received
PulseSig(Arm, Clk);
wait for 100 ns;
ApplyStrData(4, 0, 2, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, 5);
-- Lost
ApplyStrData(7, 3, 3, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts);
StrDone := true;
-- Single Shot Mode
while TestCase /= 1 loop
wait until rising_edge(Str_Clk);
end loop;
wait for 100 ns;
-- Lost
ApplyStrData(5, 1, 1, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts);
-- Received
PulseSig(Arm, Clk);
wait for 100 ns;
ApplyStrData(6, 2, 2, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, 5);
-- Lost
ApplyStrData(7, 3, 3, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, 5+6);
StrDone := true;
-- Manual Mode
while TestCase /= 2 loop
wait until rising_edge(Str_Clk);
end loop;
wait for 100 ns;
-- Lost
ApplyStrData(5, 1, 1, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts);
-- Received (partially)
Str_Ts <= std_logic_vector(to_unsigned(10, 64));
PulseSig(Arm, Clk);
wait for 100 ns;
Str_Ts <= std_logic_vector(to_unsigned(0, 64));
ApplyStrData(100, 80, 2, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, 5);
-- Lost
ApplyStrData(7, 3, 3, Generics_c, Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, 5+6);
StrDone := true;
end procedure;
procedure daq (
@ -81,7 +133,52 @@ package body psi_ms_daq_input_tb_case_modes is
signal Ts_Data : in std_logic_vector;
constant Generics_c : Generics_t) is
begin
assert false report "Case MODES Procedure DAQ: No Content added yet!" severity warning;
-- Config
PostTrigSpls <= std_logic_vector(to_unsigned(3, 32));
Daq_Rdy <= '0';
-- Trigger Mask Mode
print(">> Trigger Mask Mode");
StrDone := false;
Mode <= RecMode_TriggerMask_c;
TestCase := 0;
CheckAcqData (5+4, 2, Generics_c, FrameType_Trigger_c, Clk, Daq_Vld, Daq_Rdy, Daq_Data, Ts_Vld, Ts_Rdy, Ts_Data);
wait for 100 ns;
CheckAcqData (7, 3, Generics_c, FrameType_Timeout_c, Clk, Daq_Vld, Daq_Rdy, Daq_Data, Ts_Vld, Ts_Rdy, Ts_Data);
while not StrDone loop
wait until rising_edge(Clk);
end loop;
wait until rising_edge(Clk);
StdlCompare(0, Daq_Vld, "Unexpected data is available");
-- Single Shot Mode
print(">> Single Shot Mode");
StrDone := false;
Mode <= RecMode_SingleShot_c;
TestCase := 1;
CheckAcqData (6, 2, Generics_c, FrameType_Trigger_c, Clk, Daq_Vld, Daq_Rdy, Daq_Data, Ts_Vld, Ts_Rdy, Ts_Data, false, 5);
while not StrDone loop
wait until rising_edge(Clk);
end loop;
wait until rising_edge(Clk);
StdlCompare(0, Daq_Vld, "Unexpected data is available");
-- Manual Mode
report "Test Here" severity note;
PostTrigSpls <= std_logic_vector(to_unsigned(6, 32));
print(">> Manual Mode");
StrDone := false;
Mode <= RecMode_ManuelMode_c;
TestCase := 2;
CheckAcqData (7, 10, Generics_c, FrameType_Trigger_c, Clk, Daq_Vld, Daq_Rdy, Daq_Data, Ts_Vld, Ts_Rdy, Ts_Data, false, 5);
while not StrDone loop
wait until rising_edge(Clk);
end loop;
wait until rising_edge(Clk);
StdlCompare(0, Daq_Vld, "Unexpected data is available");
end procedure;
end;

2
tb/psi_ms_daq_input/psi_ms_daq_input_tb_pkg.vhd
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@ -187,7 +187,7 @@ package body psi_ms_daq_input_tb_pkg is
if not IsBadTs then
StdlCompare(1, Ts_Vld, "Ts_Vld not asserted");
end if;
StdlvCompareInt(Timestamp, Ts_Data, "delayed TLAST must have zero data bytes", true);
StdlvCompareInt(Timestamp, Ts_Data, "Received wrong timestamp", true);
Ts_Rdy <= '1';
wait until rising_edge(Clk);
Ts_Rdy <= '0';