AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Set up everything for implementing recorder modes

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This commit is contained in:
Oliver Bruendler
2018-07-12 09:57:19 +02:00
parent f90e2adff0
commit 8f553f3601
12 changed files with 243 additions and 21 deletions
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64
hdl/psi_ms_daq_input.vhd
View File

@ -17,7 +17,7 @@ library work;
------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------
-- $$ testcases=single_frame,multi_frame,timeout,ts_overflow,trig_in_posttrig,always_trig,backpressure $$
-- $$ testcases=single_frame,multi_frame,timeout,ts_overflow,trig_in_posttrig,always_trig,backpressure,modes $$
-- $$ processes=stream,daq $$
-- $$ tbpkg=work.psi_tb_txt_util $$
entity psi_ms_daq_input is
@ -39,9 +39,12 @@ entity psi_ms_daq_input is
Str_Ts : in std_logic_vector(63 downto 0); -- $$ proc=stream $$
-- DAQ control signals
Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=daq $$
Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=daq,stream $$
Rst : in std_logic; -- $$ type=rst; clk=Clk $$
PostTrigSpls : in std_logic_vector(31 downto 0); -- $$ proc=daq $$
Mode : in RecMode_t; -- $$ proc=daq $$
Arm : in std_logic; -- $$ proc=stream $$
IsArmed : out std_logic; -- $$ proc=stream $$
-- DAQ logic Connections
Daq_Vld : out std_logic; -- $$ proc=daq $$
@ -71,6 +74,8 @@ architecture rtl of psi_ms_daq_input is
-- Two process method
type two_process_r is record
ModeReg : RecMode_t;
ArmReg : std_logic;
DataSftReg : std_logic_vector(63 downto 0);
WordCnt : unsigned(log2ceil(WconvFactor_c) downto 0);
DataFifoBytes : unsigned(3 downto 0);
@ -85,6 +90,8 @@ architecture rtl of psi_ms_daq_input is
TsLatch : std_logic_vector(63 downto 0);
TsOverflow : std_logic;
HasTlastSync : std_logic_vector(0 to 1);
IsArmed : std_logic;
RecEna : std_logic;
end record;
signal r, r_next : two_process_r;
@ -118,13 +125,14 @@ begin
-- Combinatorial Process
--------------------------------------------
p_comb : process( r,
Str_Vld, Str_Data, Str_Trig, Str_Ts, PostTrigSpls, Daq_Rdy, Ts_Rdy,
Str_Vld, Str_Data, Str_Trig, Str_Ts, PostTrigSpls, Daq_Rdy, Ts_Rdy, Mode, Arm,
DataFifo_InRdy, DataFifo_InData, DataFifo_OutData, Daq_Vld_I, Daq_Data_I, Daq_HasLast_I, Ts_Vld_I, OutTlastCnt, TsFifo_AlmFull, TsFifo_Empty,
InTlastCnt, TsFifo_InRdy, TsFifo_RdData)
variable v : two_process_r;
variable ProcessSample_v : boolean;
variable TriggerSample_v : boolean;
variable AddSamples_v : integer range 0 to 1;
variable TrigMasked_v : std_logic;
begin
-- *** Hold variables stable ***
v := r;
@ -136,6 +144,21 @@ begin
-- Default values
v.DataFifoIsTo := '0';
v.DataFifoIsTrig := '0';
v.ModeReg := Mode;
v.ArmReg := Arm;
-- Masking trigger according to recording mode
case r.ModeReg is
when RecMode_Continuous_c =>
TrigMasked_v := Str_Trig;
when RecMode_TriggerMask_c |
RecMode_SingleShot_c =>
TrigMasked_v := Str_Trig and r.IsArmed;
when RecMode_ManuelMode_c =>
TrigMasked_v := r.ArmReg;
when others => null;
end case;
-- Keep FifoVld high until data is written
v.DataFifoVld := r.DataFifoVld and not DataFifo_InRdy;
@ -144,7 +167,7 @@ begin
if ProcessSample_v then
v.TrigLatch := '0';
else
v.TrigLatch := r.TrigLatch or Str_Trig;
v.TrigLatch := r.TrigLatch or TrigMasked_v;
end if;
-- Detect timestamp FIFO overflows
@ -160,7 +183,7 @@ begin
-- Timestamp latching
if StreamUseTs_g then
if (Str_Trig = '1') and (unsigned(r.PostTrigCnt) = 0) then
if (TrigMasked_v = '1') and (unsigned(r.PostTrigCnt) = 0) then
if (TsFifo_AlmFull = '1') or (r.TsOverflow = '1') then
v.TsLatch := (others => '1');
else
@ -178,7 +201,7 @@ begin
v.DataFifoIsTrig := '1';
v.DataFifoVld := '1';
end if;
elsif (r.TrigLatch = '1') or (Str_Trig = '1') then
elsif (r.TrigLatch = '1') or (TrigMasked_v = '1') then
-- Handle incoming trigger sample
if unsigned(PostTrigSpls) = 0 then
v.DataFifoIsTrig := '1';
@ -241,13 +264,37 @@ begin
when others => null;
end case;
-- Handle Arming Logic
if (r.ModeReg /= Mode) or (r.ModeReg = RecMode_Continuous_c) or (r.ModeReg = RecMode_ManuelMode_c) then -- reset on mode change!
v.IsArmed := '0';
elsif r.ArmReg = '1' then
v.IsArmed := '1';
elsif TrigMasked_v = '1' then
v.IsArmed := '0';
end if;
-- Enable Recording Logic
case r.ModeReg is
when RecMode_Continuous_c |
RecMode_TriggerMask_c =>
-- always enabled
v.RecEna := '1';
when RecMode_SingleShot_c |
RecMode_ManuelMode_c =>
-- enable on arming (disable happens after recording)
if v.IsArmed = '1' then
v.RecEna := '1';
end if;
when others => null;
end case;
-- *** Assign to signal ***
r_next <= v;
end process;
-- *** Registered Outputs ***
IsArmed <= r.IsArmed;
--------------------------------------------
-- Sequential Process
@ -265,6 +312,9 @@ begin
r.TLastCnt <= (others => '0');
r.TsOverflow <= '0';
r.HasTlastSync <= (others => '0');
r.IsArmed <= '0';
r.RecEna <= '0';
r.ArmReg <= '0';
end if;
end if;
end process;

6
hdl/psi_ms_daq_pkg.vhd
View File

@ -13,6 +13,12 @@ package psi_ms_daq_pkg is
constant MaxStreams_c : integer := 32;
constant MaxWindows_c : integer := 32;
subtype RecMode_t is std_logic_vector(1 downto 0);
constant RecMode_Continuous_c : RecMode_t := std_logic_vector(to_unsigned(0, RecMode_t'length));
constant RecMode_TriggerMask_c : RecMode_t := std_logic_vector(to_unsigned(1, RecMode_t'length));
constant RecMode_SingleShot_c : RecMode_t := std_logic_vector(to_unsigned(2, RecMode_t'length));
constant RecMode_ManuelMode_c : RecMode_t := std_logic_vector(to_unsigned(3, RecMode_t'length));
type Input2Daq_Data_t is record
Last : std_logic;
Data : std_logic_vector(63 downto 0);

1
sim/config.tcl
View File

@ -44,6 +44,7 @@ add_sources "../tb" {
psi_ms_daq_input/psi_ms_daq_input_tb_case_trig_in_posttrig.vhd \
psi_ms_daq_input/psi_ms_daq_input_tb_case_backpressure.vhd \
psi_ms_daq_input/psi_ms_daq_input_tb_case_always_trig.vhd \
psi_ms_daq_input/psi_ms_daq_input_tb_case_modes.vhd \
psi_ms_daq_input/psi_ms_daq_input_tb.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_pkg.vhd \
psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_single_window.vhd \

50
tb/psi_ms_daq_input/psi_ms_daq_input_tb.vhd
View File

@ -28,6 +28,7 @@ library work;
use work.psi_ms_daq_input_tb_case_trig_in_posttrig.all;
use work.psi_ms_daq_input_tb_case_always_trig.all;
use work.psi_ms_daq_input_tb_case_backpressure.all;
use work.psi_ms_daq_input_tb_case_modes.all;
------------------------------------------------------------
-- Entity Declaration
@ -75,6 +76,9 @@ architecture sim of psi_ms_daq_input_tb is
signal Clk : std_logic := '1';
signal Rst : std_logic := '1';
signal PostTrigSpls : std_logic_vector(31 downto 0) := (others => '0');
signal Mode : RecMode_t := (others => '0');
signal Arm : std_logic := '0';
signal IsArmed : std_logic := '0';
signal Daq_Vld : std_logic := '0';
signal Daq_Rdy : std_logic := '0';
signal Daq_Data : Input2Daq_Data_t;
@ -107,6 +111,9 @@ begin
Clk => Clk,
Rst => Rst,
PostTrigSpls => PostTrigSpls,
Mode => Mode,
Arm => Arm,
IsArmed => IsArmed,
Daq_Vld => Daq_Vld,
Daq_Rdy => Daq_Rdy,
Daq_Data => Daq_Data,
@ -144,6 +151,9 @@ begin
-- backpressure
NextCase <= 6;
wait until ProcessDone = AllProcessesDone_c;
-- modes
NextCase <= 7;
wait until ProcessDone = AllProcessesDone_c;
TbRunning <= false;
wait;
end process;
@ -195,43 +205,49 @@ begin
-- single_frame
wait until NextCase = 0;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_single_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_single_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- multi_frame
wait until NextCase = 1;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_multi_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_multi_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- timeout
wait until NextCase = 2;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_timeout.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_timeout.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- ts_overflow
wait until NextCase = 3;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_ts_overflow.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_ts_overflow.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- trig_in_posttrig
wait until NextCase = 4;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_trig_in_posttrig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_trig_in_posttrig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- always_trig
wait until NextCase = 5;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_always_trig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_always_trig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- backpressure
wait until NextCase = 6;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_backpressure.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Generics_c);
work.psi_ms_daq_input_tb_case_backpressure.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
-- modes
wait until NextCase = 7;
ProcessDone(TbProcNr_stream_c) <= '0';
work.psi_ms_daq_input_tb_case_modes.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_stream_c) <= '1';
wait;
@ -243,43 +259,49 @@ begin
-- single_frame
wait until NextCase = 0;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_single_frame.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_single_frame.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- multi_frame
wait until NextCase = 1;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_multi_frame.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_multi_frame.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- timeout
wait until NextCase = 2;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_timeout.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_timeout.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- ts_overflow
wait until NextCase = 3;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_ts_overflow.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_ts_overflow.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- trig_in_posttrig
wait until NextCase = 4;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_trig_in_posttrig.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_trig_in_posttrig.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- always_trig
wait until NextCase = 5;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_always_trig.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_always_trig.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- backpressure
wait until NextCase = 6;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_backpressure.daq(Clk, PostTrigSpls, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
work.psi_ms_daq_input_tb_case_backpressure.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
-- modes
wait until NextCase = 7;
ProcessDone(TbProcNr_daq_c) <= '0';
work.psi_ms_daq_input_tb_case_modes.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
wait for 1 ps;
ProcessDone(TbProcNr_daq_c) <= '1';
wait;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_always_trig.vhd
View File

@ -27,11 +27,15 @@ package psi_ms_daq_input_tb_case_always_trig is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -55,6 +59,9 @@ package body psi_ms_daq_input_tb_case_always_trig is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -87,6 +94,7 @@ package body psi_ms_daq_input_tb_case_always_trig is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_backpressure.vhd
View File

@ -27,11 +27,15 @@ package psi_ms_daq_input_tb_case_backpressure is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -60,6 +64,9 @@ package body psi_ms_daq_input_tb_case_backpressure is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -128,6 +135,7 @@ package body psi_ms_daq_input_tb_case_backpressure is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;

87
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_modes.vhd Normal file
View File

@ -0,0 +1,87 @@
------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.psi_common_math_pkg.all;
use work.psi_ms_daq_pkg.all;
library work;
use work.psi_ms_daq_input_tb_pkg.all;
library work;
use work.psi_tb_txt_util.all;
------------------------------------------------------------
-- Package Header
------------------------------------------------------------
package psi_ms_daq_input_tb_case_modes is
procedure stream (
signal Str_Clk : in std_logic;
signal Str_Vld : inout std_logic;
signal Str_Rdy : in std_logic;
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
signal Daq_Level : in std_logic_vector;
signal Daq_HasLast : in std_logic;
signal Ts_Vld : in std_logic;
signal Ts_Rdy : inout std_logic;
signal Ts_Data : in std_logic_vector;
constant Generics_c : Generics_t);
end package;
------------------------------------------------------------
-- Package Body
------------------------------------------------------------
package body psi_ms_daq_input_tb_case_modes is
procedure stream (
signal Str_Clk : in std_logic;
signal Str_Vld : inout std_logic;
signal Str_Rdy : in std_logic;
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
assert false report "Case MODES Procedure STREAM: No Content added yet!" severity warning;
end procedure;
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
signal Daq_Level : in std_logic_vector;
signal Daq_HasLast : in std_logic;
signal Ts_Vld : in std_logic;
signal Ts_Rdy : inout std_logic;
signal Ts_Data : in std_logic_vector;
constant Generics_c : Generics_t) is
begin
assert false report "Case MODES Procedure DAQ: No Content added yet!" severity warning;
end procedure;
end;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_multi_frame.vhd
View File

@ -27,11 +27,15 @@ package psi_ms_daq_input_tb_case_multi_frame is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -57,6 +61,9 @@ package body psi_ms_daq_input_tb_case_multi_frame is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -76,6 +83,7 @@ package body psi_ms_daq_input_tb_case_multi_frame is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_single_frame.vhd
View File

@ -27,11 +27,15 @@ package psi_ms_daq_input_tb_case_single_frame is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -58,6 +62,9 @@ package body psi_ms_daq_input_tb_case_single_frame is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -118,6 +125,7 @@ package body psi_ms_daq_input_tb_case_single_frame is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_timeout.vhd
View File

@ -28,11 +28,15 @@ package psi_ms_daq_input_tb_case_timeout is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -58,6 +62,9 @@ package body psi_ms_daq_input_tb_case_timeout is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -88,6 +95,7 @@ package body psi_ms_daq_input_tb_case_timeout is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_trig_in_posttrig.vhd
View File

@ -28,11 +28,15 @@ package psi_ms_daq_input_tb_case_trig_in_posttrig is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -58,6 +62,9 @@ package body psi_ms_daq_input_tb_case_trig_in_posttrig is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -84,6 +91,7 @@ package body psi_ms_daq_input_tb_case_trig_in_posttrig is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;

8
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_ts_overflow.vhd
View File

@ -27,11 +27,15 @@ package psi_ms_daq_input_tb_case_ts_overflow is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t);
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;
@ -58,6 +62,9 @@ package body psi_ms_daq_input_tb_case_ts_overflow is
signal Str_Data : inout std_logic_vector;
signal Str_Trig : inout std_logic;
signal Str_Ts : inout std_logic_vector;
signal Clk : in std_logic;
signal Arm : inout std_logic;
signal IsArmed : in std_logic;
constant Generics_c : Generics_t) is
begin
-- Wait for config to be applied
@ -94,6 +101,7 @@ package body psi_ms_daq_input_tb_case_ts_overflow is
procedure daq (
signal Clk : in std_logic;
signal PostTrigSpls : inout std_logic_vector;
signal Mode : inout RecMode_t;
signal Daq_Vld : in std_logic;
signal Daq_Rdy : inout std_logic;
signal Daq_Data : in Input2Daq_Data_t;