AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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UPDATE: Update to new library versions after open sourcing

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This commit is contained in:
Oliver Bruendler
2018-10-17 09:13:45 +02:00
parent 415c743f14
commit 0a791bcb05
5 changed files with 41 additions and 24 deletions
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4
Changelog.md
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@ -1,3 +1,5 @@
## 0.1.0
## 0.2.0
* Updated according to new library versions after open sourcing
## 0.1.0
* Ready for first tests on HW

17
README.md
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@ -18,13 +18,20 @@ See [Changelog](Changelog.md)
# Dependencies
## Library
* Libraries/TCL/PsiSim
* Libraries/Vhdl/psi\_common
* Libraries/Vhdl/psi\_tb
* Libraries/BoardSupport/IFC1210/smem\_master
Directory structure as given below
* BoardSupport
* IFC1210
* [smem\_master](https://git.psi.ch/GFA/Libraries/BoardSupport/IFC1210/smem_master) (not released yet)
* Firmware
* TCL
* [PsiSim](https://github.com/paulscherrerinstitute/PsiSim) (2.0.0 or higher, for development only)
* VHDL
* [psi\_common](https://github.com/paulscherrerinstitute/psi_common) (2.0.0 or higher)
* [psi\_tb](https://github.com/paulscherrerinstitute/psi_tb) (2.0.0 or higher, for development only)
* [**psi\_multi\_stream\_daq**](https://git.psi.ch/GFA/Libraries/Firmware/VHDL/psi_multi_stream_daq)
## External
None
None

20
hdl/psi_ms_daq_daq_dma.vhd
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@ -295,7 +295,8 @@ begin
generic map (
Width_g => DaqSm2DaqDma_Cmd_Size_c,
Depth_g => Streams_g,
RamStyle_g => "distributed"
RamStyle_g => "distributed",
RamBehavior_g => "RBW"
)
port map (
Clk => Clk,
@ -316,7 +317,8 @@ begin
generic map (
Width_g => DaqDma2DaqSm_Resp_Size_c,
Depth_g => Streams_g,
RamStyle_g => "distributed"
RamStyle_g => "distributed",
RamBehavior_g => "RBW"
)
port map (
Clk => Clk,
@ -340,7 +342,8 @@ begin
Depth_g => BufferFifoDepth_c,
AlmFullOn_g => true,
AlmFullLevel_g => BufferFifoDepth_c/2,
RamStyle_g => "distributed"
RamStyle_g => "distributed",
RamBehavior_g => "RBW"
)
port map (
Clk => Clk,
@ -355,12 +358,13 @@ begin
);
-- *** Remaining Data RAM ***
i_remram : entity work.psi_common_sdp_ram_rbw
i_remram : entity work.psi_common_sdp_ram
generic map (
Depth_g => Streams_g,
Width_g => 1+1+3+64,
IsAsync_g => false,
RamStyle_g => "distributed"
Depth_g => Streams_g,
Width_g => 1+1+3+64,
IsAsync_g => false,
RamStyle_g => "distributed",
Behavior_g => "RBW"
)
port map (
Clk => Clk,

20
hdl/psi_ms_daq_reg_tmem.vhd
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@ -334,10 +334,11 @@ begin
CtxStr_AddrB <= std_logic_vector(to_unsigned(CtxStr_Cmd.Stream, log2ceil(Streams_g))) & CtxStr_Cmd.Sel;
-- Low DWORD memory
i_mem_ctx_lo : entity work.psi_common_tdp_ram_rbw
i_mem_ctx_lo : entity work.psi_common_tdp_ram
generic map (
Depth_g => DepthCtxStr_c,
Width_g => 32
Width_g => 32,
Behavior_g => "RBW"
)
port map (
ClkA => ClkTmem,
@ -353,10 +354,11 @@ begin
);
-- High DWORD memory
i_mem_ctx_hi : entity work.psi_common_tdp_ram_rbw
i_mem_ctx_hi : entity work.psi_common_tdp_ram
generic map (
Depth_g => DepthCtxStr_c,
Width_g => 32
Width_g => 32,
Behavior_g => "RBW"
)
port map (
ClkA => ClkTmem,
@ -381,10 +383,11 @@ begin
CtxWin_Cmd.Sel;
-- Low DWORD memory
i_mem_win_lo : entity work.psi_common_tdp_ram_rbw
i_mem_win_lo : entity work.psi_common_tdp_ram
generic map (
Depth_g => DepthCtxWin_c,
Width_g => 32
Width_g => 32,
Behavior_g => "RBW"
)
port map (
ClkA => ClkTmem,
@ -400,10 +403,11 @@ begin
);
-- High DWORD memory
i_mem_win_hi : entity work.psi_common_tdp_ram_rbw
i_mem_win_hi : entity work.psi_common_tdp_ram
generic map (
Depth_g => DepthCtxWin_c,
Width_g => 32
Width_g => 32,
Behavior_g => "RBW"
)
port map (
ClkA => ClkTmem,

4
sim/config.tcl
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@ -19,7 +19,7 @@ add_sources $LibPath {
psi_common/hdl/psi_common_array_pkg.vhd \
psi_common/hdl/psi_common_math_pkg.vhd \
psi_common/hdl/psi_common_logic_pkg.vhd \
psi_common/hdl/psi_common_sdp_ram_rbw.vhd \
psi_common/hdl/psi_common_sdp_ram.vhd \
psi_common/hdl/psi_common_pulse_cc.vhd \
psi_common/hdl/psi_common_bit_cc.vhd \
psi_common/hdl/psi_common_simple_cc.vhd \
@ -27,7 +27,7 @@ add_sources $LibPath {
psi_common/hdl/psi_common_async_fifo.vhd \
psi_common/hdl/psi_common_arb_priority.vhd \
psi_common/hdl/psi_common_sync_fifo.vhd \
psi_common/hdl/psi_common_tdp_ram_rbw.vhd \
psi_common/hdl/psi_common_tdp_ram.vhd \
../../BoardSupport/IFC1210/smem_master/hdl/smem_master_types_pkg.vhd \
../../BoardSupport/IFC1210/smem_master/hdl/smem_master_write.vhd \
} -tag lib