AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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DEVEL: Made IP Vivado Compatible

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- Add ID Ports to axi slave interface
- Simplified some expressions in psi_ms_daq_daq_sm.vhd
This commit is contained in:
Oliver Bruendler
2019-06-14 07:52:10 +02:00
parent 1a75cd16a5
commit 4399e89830
5 changed files with 45 additions and 15 deletions
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17
hdl/psi_ms_daq_axi.vhd
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@ -33,7 +33,9 @@ entity psi_ms_daq_axi is
AxiDataWidth_g : natural range 64 to 1024 := 64;
AxiMaxBurstBeats_g : integer range 1 to 256 := 256;
AxiMaxOpenTrasactions_g : natural range 1 to 8 := 8;
AxiFifoDepth_g : natural := 1024
AxiFifoDepth_g : natural := 1024;
-- Axi Slave
AxiSlaveIdWidth_g : integer := 0
);
port (
-- Data Stream Input
@ -50,6 +52,7 @@ entity psi_ms_daq_axi is
-- AXI Slave Interface for Register Access
S_Axi_Aclk : in std_logic;
S_Axi_Aresetn : in std_logic;
S_Axi_ArId : in std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_ArAddr : in std_logic_vector(15 downto 0);
S_Axi_Arlen : in std_logic_vector(7 downto 0);
S_Axi_ArSize : in std_logic_vector(2 downto 0);
@ -59,11 +62,13 @@ entity psi_ms_daq_axi is
S_Axi_ArProt : in std_logic_vector(2 downto 0);
S_Axi_ArValid : in std_logic;
S_Axi_ArReady : out std_logic;
S_Axi_RId : out std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_RData : out std_logic_vector(31 downto 0);
S_Axi_RResp : out std_logic_vector(1 downto 0);
S_Axi_RLast : out std_logic;
S_Axi_RValid : out std_logic;
S_Axi_RReady : in std_logic;
S_Axi_AwId : in std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_AwAddr : in std_logic_vector(15 downto 0);
S_Axi_AwLen : in std_logic_vector(7 downto 0);
S_Axi_AwSize : in std_logic_vector(2 downto 0);
@ -78,6 +83,7 @@ entity psi_ms_daq_axi is
S_Axi_WLast : in std_logic;
S_Axi_WValid : in std_logic;
S_Axi_WReady : out std_logic;
S_Axi_BId : out std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_BResp : out std_logic_vector(1 downto 0);
S_Axi_BValid : out std_logic;
S_Axi_BReady : in std_logic;
@ -191,11 +197,13 @@ begin
i_reg : entity work.psi_ms_daq_reg_axi
generic map (
Streams_g => Streams_g,
MaxWindows_g => MaxWindows_g
MaxWindows_g => MaxWindows_g,
AxiSlaveIdWidth_g => AxiSlaveIdWidth_g
)
port map (
S_Axi_Aclk => S_Axi_Aclk,
S_Axi_Aresetn => S_Axi_Aresetn,
S_Axi_ArId => S_Axi_ArId,
S_Axi_ArAddr => S_Axi_ArAddr,
S_Axi_Arlen => S_Axi_Arlen,
S_Axi_ArSize => S_Axi_ArSize,
@ -204,12 +212,14 @@ begin
S_Axi_ArCache => S_Axi_ArCache,
S_Axi_ArProt => S_Axi_ArProt,
S_Axi_ArValid => S_Axi_ArValid,
S_Axi_ArReady => S_Axi_ArReady,
S_Axi_ArReady => S_Axi_ArReady,
S_Axi_RId => S_Axi_RId,
S_Axi_RData => S_Axi_RData,
S_Axi_RResp => S_Axi_RResp,
S_Axi_RLast => S_Axi_RLast,
S_Axi_RValid => S_Axi_RValid,
S_Axi_RReady => S_Axi_RReady,
S_Axi_AwId => S_Axi_AwId,
S_Axi_AwAddr => S_Axi_AwAddr,
S_Axi_AwLen => S_Axi_AwLen,
S_Axi_AwSize => S_Axi_AwSize,
@ -224,6 +234,7 @@ begin
S_Axi_WLast => S_Axi_WLast,
S_Axi_WValid => S_Axi_WValid,
S_Axi_WReady => S_Axi_WReady,
S_Axi_BId => S_Axi_BId,
S_Axi_BResp => S_Axi_BResp,
S_Axi_BValid => S_Axi_BValid,
S_Axi_BReady => S_Axi_BReady,

16
hdl/psi_ms_daq_daq_sm.vhd
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@ -103,15 +103,17 @@ architecture rtl of psi_ms_daq_daq_sm is
end function;
-- Vivado Workarounds (Synthesis fail)
function CalcLog2Bytes return t_ainteger is
variable arr : t_ainteger(0 to Streams_g-1);
subtype Log2Bytes_t is integer range 0 to log2(MaxStreamWidth_c/8);
type Log2Bytes_a is array (natural range <>) of Log2Bytes_t;
function CalcLog2Bytes return Log2Bytes_a is
variable arr : Log2Bytes_a(0 to Streams_g-1);
begin
for i in 0 to Streams_g-1 loop
arr(i) := log2(StreamWidth_g(i)/8);
end loop;
return arr;
end function;
constant Log2StrBytes_c : t_ainteger(0 to Streams_g-1) := CalcLog2Bytes;
constant Log2StrBytes_c : Log2Bytes_a(0 to Streams_g-1) := CalcLog2Bytes;
-- Component Connection Signals
signal AvailPrio1 : std_logic_vector(count(StreamPrio_g, 1)-1 downto 0);
@ -402,7 +404,13 @@ begin
-- Response handling
case r.HndlCtxCnt is
when 2 => v.HndlWinBytes := '0' & ShiftLeft(CtxWin_Resp.RdatLo, Log2StrBytes_c(r.HndlStream)); -- guard bit required for calculations
when 2 =>
-- Workaround for Vivado (Range expression was resolved incorrectly)
for i in 0 to Streams_g-1 loop
if i = r.HndlStream then
v.HndlWinBytes := '0' & ShiftLeft(CtxWin_Resp.RdatLo, Log2StrBytes_c(i)); -- guard bit required for calculations
end if;
end loop;
when others => null;
end case;

1
hdl/psi_ms_daq_pkg.vhd
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@ -17,6 +17,7 @@ package psi_ms_daq_pkg is
constant MaxWindows_c : integer := 32;
constant MaxStreamsBits_c : integer := log2ceil(MaxStreams_c);
constant MaxWindowsBits_c : integer := log2ceil(MaxWindows_c);
constant MaxStreamWidth_c : integer := 64;
subtype RecMode_t is std_logic_vector(1 downto 0);
constant RecMode_Continuous_c : RecMode_t := std_logic_vector(to_unsigned(0, RecMode_t'length));

19
hdl/psi_ms_daq_reg_axi.vhd
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@ -17,14 +17,16 @@ library work;
------------------------------------------------------------------------------
entity psi_ms_daq_reg_axi is
generic (
Streams_g : in integer range 1 to 32;
MaxWindows_g : in integer range 1 to 32
Streams_g : integer range 1 to 32;
MaxWindows_g : integer range 1 to 32;
AxiSlaveIdWidth_g : integer
);
port (
-- AXI Control Signals
S_Axi_Aclk : in std_logic;
S_Axi_Aresetn : in std_logic;
-- AXI Read address channel
S_Axi_ArId : in std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_ArAddr : in std_logic_vector(15 downto 0);
S_Axi_Arlen : in std_logic_vector(7 downto 0);
S_Axi_ArSize : in std_logic_vector(2 downto 0);
@ -35,12 +37,14 @@ entity psi_ms_daq_reg_axi is
S_Axi_ArValid : in std_logic;
S_Axi_ArReady : out std_logic;
-- AXI Read data channel
S_Axi_RId : out std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_RData : out std_logic_vector(31 downto 0);
S_Axi_RResp : out std_logic_vector(1 downto 0);
S_Axi_RLast : out std_logic;
S_Axi_RValid : out std_logic;
S_Axi_RReady : in std_logic;
-- AXI Write address channel
S_Axi_AwId : in std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_AwAddr : in std_logic_vector(15 downto 0);
S_Axi_AwLen : in std_logic_vector(7 downto 0);
S_Axi_AwSize : in std_logic_vector(2 downto 0);
@ -57,6 +61,7 @@ entity psi_ms_daq_reg_axi is
S_Axi_WValid : in std_logic;
S_Axi_WReady : out std_logic;
-- AXI Write response channel
S_Axi_BId : out std_logic_vector(AxiSlaveIdWidth_g-1 downto 0);
S_Axi_BResp : out std_logic_vector(1 downto 0);
S_Axi_BValid : out std_logic;
S_Axi_BReady : in std_logic;
@ -336,7 +341,7 @@ begin
4 => (others => '0'), 5 => (others => '0'), 6 => (others => '0'), 7 => (others => '0'),
8 => (others => '0'), 9 => (others => '0'), 10 => (others => '0'), 11 => (others => '0'),
12 => (others => '0'), 13 => (others => '0'), 14 => (others => '0'), 15 => (others => '0')),
C_S_AXI_ID_WIDTH => 0,
C_S_AXI_ID_WIDTH => AxiSlaveIdWidth_g,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_ARUSER_WIDTH => 0,
@ -348,7 +353,7 @@ begin
port map (
s_axi_aclk => S_Axi_Aclk,
s_axi_aresetn => S_Axi_Aresetn,
s_axi_arid => (others => '0'),
s_axi_arid => S_Axi_ArId,
s_axi_araddr => S_Axi_ArAddr,
s_axi_arlen => S_Axi_Arlen,
s_axi_arsize => S_Axi_ArSize,
@ -361,14 +366,14 @@ begin
s_axi_aruser => (others => '0'),
s_axi_arvalid => S_Axi_ArValid,
s_axi_arready => S_Axi_ArReady,
s_axi_rid => open,
s_axi_rid => S_Axi_RId,
s_axi_rdata => S_Axi_RData,
s_axi_rresp => S_Axi_RResp,
s_axi_rlast => S_Axi_RLast,
s_axi_ruser => open,
s_axi_rvalid => S_Axi_RValid,
s_axi_rready => S_Axi_RReady,
s_axi_awid => (others => '0'),
s_axi_awid => S_Axi_AwId,
s_axi_awaddr => S_Axi_AwAddr,
s_axi_awlen => S_Axi_AwLen,
s_axi_awsize => S_Axi_AwSize,
@ -387,7 +392,7 @@ begin
s_axi_wuser => (others => '0'),
s_axi_wvalid => S_Axi_WValid,
s_axi_wready => S_Axi_WReady,
s_axi_bid => open,
s_axi_bid => S_Axi_BId,
s_axi_bresp => S_Axi_BResp,
s_axi_buser => open,
s_axi_bvalid => S_Axi_BValid,

7
tb/psi_ms_daq_axi/psi_ms_daq_axi_tb.vhd
View File

@ -160,7 +160,8 @@ begin
MaxWindows_g => work.psi_ms_daq_axi_tb_pkg.MaxWindows_c,
MinBurstSize_g => 16,
MaxBurstSize_g => 128,
AxiFifoDepth_g => 512
AxiFifoDepth_g => 512,
AxiSlaveIdWidth_g => 1
)
port map (
Str_Clk => Str_Clk,
@ -179,6 +180,7 @@ begin
Irq => Irq,
S_Axi_Aclk => S_Axi_Aclk,
S_Axi_Aresetn => S_Axi_Aresetn,
S_Axi_ArId => reg_axi_ms.arid,
S_Axi_ArAddr => reg_axi_ms.araddr,
S_Axi_Arlen => reg_axi_ms.arlen,
S_Axi_ArSize => reg_axi_ms.arsize,
@ -188,12 +190,14 @@ begin
S_Axi_ArProt => reg_axi_ms.arprot,
S_Axi_ArValid => reg_axi_ms.arvalid,
S_Axi_ArReady => reg_axi_sm.arready,
S_Axi_RId => reg_axi_sm.rid,
S_Axi_RData => reg_axi_sm.rdata,
S_Axi_RResp => reg_axi_sm.rresp,
S_Axi_RLast => reg_axi_sm.rlast,
S_Axi_RValid => reg_axi_sm.rvalid,
S_Axi_RReady => reg_axi_ms.rready,
S_Axi_AwAddr => reg_axi_ms.awaddr,
S_AXi_AwId => reg_axi_ms.awid,
S_Axi_AwLen => reg_axi_ms.awlen,
S_Axi_AwSize => reg_axi_ms.awsize,
S_Axi_AwBurst => reg_axi_ms.awburst,
@ -207,6 +211,7 @@ begin
S_Axi_WLast => reg_axi_ms.wlast,
S_Axi_WValid => reg_axi_ms.wvalid,
S_Axi_WReady => reg_axi_sm.wready,
S_Axi_BId => reg_axi_sm.bid,
S_Axi_BResp => reg_axi_sm.bresp,
S_Axi_BValid => reg_axi_sm.bvalid,
S_Axi_BReady => reg_axi_ms.bready,