BUGFIX: Added various simplifications to make code synthesizable by Vivado

hdl/psi_ms_daq_axi.vhd

@@ -31,7 +31,7 @@ entity psi_ms_daq_axi is
 		MaxBurstSize_g			: integer range 1 to 512		:= 512;
 		-- Axi
 		AxiDataWidth_g			: natural range 64 to 1024		:= 64;
-		AxMaxBustBeats_g		: integer range 1 to 256		:= 256;
+		AxiMaxBurstBeats_g		: integer range 1 to 256		:= 256;
 		AxiMaxOpenTrasactions_g	: natural range 1 to 8			:= 8;
 		AxiFifoDepth_g			: natural						:= 1024
 	);
@@ -370,7 +370,7 @@ begin
 	i_memif : entity work.psi_ms_daq_axi_if
 		generic map (
 			AxiDataWidth_g			=> AxiDataWidth_g,
-			AxiMaxBeats_g			=> AxMaxBustBeats_g,
+			AxiMaxBeats_g			=> AxiMaxBurstBeats_g,
 			AxiMaxOpenTrasactions_g	=> AxiMaxOpenTrasactions_g,
 			MaxOpenCommands_g		=> Streams_g,
 			DataFifoDepth_g			=> 1024,

hdl/psi_ms_daq_daq_sm.vhd

@@ -74,7 +74,7 @@ architecture rtl of psi_ms_daq_daq_sm is
 	function GetBitsOfStreamPrio(	InputVector	: std_logic_vector;
 									Prio		: integer) 
 									return std_logic_vector is
-		variable Result_v : std_logic_vector(count(StreamPrio_g, Prio)-1 downto 0);
+		variable Result_v : std_logic_vector(count(StreamPrio_g, Prio)-1 downto 0)	:= (others => '0');
 		variable OutIdx_v : integer := 0;
 	begin
 		for idx in InputVector'low to InputVector'high loop
@@ -102,6 +102,17 @@ architecture rtl of psi_ms_daq_daq_sm is
 		return 0;
 	end function;
 	
+	-- Vivado Workarounds (Synthesis fail)
+	function CalcLog2Bytes return t_ainteger is
+		variable arr : t_ainteger(0 to Streams_g-1);
+	begin
+		for i in 0 to Streams_g-1 loop
+			arr(i)	:= log2(StreamWidth_g(i)/8);
+		end loop;
+		return arr;
+	end function;
+	constant Log2StrBytes_c	: t_ainteger(0 to Streams_g-1) := CalcLog2Bytes;
+	
 	-- Component Connection Signals
 	signal AvailPrio1		: std_logic_vector(count(StreamPrio_g, 1)-1 downto 0);
 	signal AvailPrio2		: std_logic_vector(count(StreamPrio_g, 2)-1 downto 0);
@@ -391,7 +402,7 @@ begin
 
 				-- Response handling
 				case r.HndlCtxCnt is
-					when 2 =>	v.HndlWinBytes	:= '0' & ShiftLeft(CtxWin_Resp.RdatLo, log2(StreamWidth_g(r.HndlStream)/8)); -- guard bit required for calculations
+					when 2 =>	v.HndlWinBytes	:= '0' & ShiftLeft(CtxWin_Resp.RdatLo, Log2StrBytes_c(r.HndlStream)); -- guard bit required for calculations
 					when others => null;
 				end case;				
 				
@@ -505,7 +516,7 @@ begin
 						v.CtxWin_Cmd.Sel	:= CtxWin_Sel_WincntWinlast_c;
 						v.CtxWin_Cmd.WenLo	:= '1';
 						v.CtxWin_Cmd.WenHi	:= '1';
-						v.CtxWin_Cmd.WdatLo	:= ShiftRight(r.HndlWinBytes(31 downto 0), log2(StreamWidth_g(r.HndlStream)/8));	-- cut-off guard bit and convert bytes to samples
+						v.CtxWin_Cmd.WdatLo	:= ShiftRight(r.HndlWinBytes(31 downto 0), Log2StrBytes_c(r.HndlStream));	-- cut-off guard bit and convert bytes to samples
 						v.CtxWin_Cmd.WdatLo(31) := r.EndByTrig;
 						v.CtxWin_Cmd.WdatHi	:= r.HndlWinLast;						
 					when 1 =>	

hdl/psi_ms_daq_input.vhd

@@ -256,7 +256,7 @@ begin
 			if r.WordCnt = WconvFactor_c-1 then	
 				v.DataFifoVld	:= r.DataFifoVld or r.RecEna;
 			end if;
-			v.DataSftReg(to_integer(r.WordCnt+1)*StreamWidth_g-1 downto to_integer(r.WordCnt)*StreamWidth_g) := Str_Data;
+			v.DataSftReg((to_integer(r.WordCnt)+1)*StreamWidth_g-1 downto to_integer(r.WordCnt)*StreamWidth_g) := Str_Data;
 		end if;
 		-- Reset counter if data is being written to FIFO
 		if v.DataFifoVld = '1' then