DEVEL: Work on DAQ DMA TB
This commit is contained in:
Oliver Bruendler
@ -61,7 +61,6 @@ add_sources "../tb" {
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_unaligned.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_trigger.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_timetout.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_odd_size.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_no_data_read.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_input_empty.vhd \
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psi_ms_daq_daq_dma/psi_ms_daq_daq_dma_tb_case_empty_timeout.vhd \
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@ -27,7 +27,6 @@ library work;
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library work;
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use work.psi_ms_daq_daq_dma_tb_case_aligned.all;
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use work.psi_ms_daq_daq_dma_tb_case_unaligned.all;
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use work.psi_ms_daq_daq_dma_tb_case_odd_size.all;
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use work.psi_ms_daq_daq_dma_tb_case_no_data_read.all;
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use work.psi_ms_daq_daq_dma_tb_case_input_empty.all;
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use work.psi_ms_daq_daq_dma_tb_case_timetout.all;
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@ -123,29 +122,26 @@ begin
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-- unaligned
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NextCase <= 1;
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wait until ProcessDone = AllProcessesDone_c;
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-- odd_size
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-- no_data_read
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NextCase <= 2;
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wait until ProcessDone = AllProcessesDone_c;
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-- no_data_read
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-- input_empty
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NextCase <= 3;
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wait until ProcessDone = AllProcessesDone_c;
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-- input_empty
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-- timetout
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NextCase <= 4;
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wait until ProcessDone = AllProcessesDone_c;
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-- timetout
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-- empty_timeout
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NextCase <= 5;
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wait until ProcessDone = AllProcessesDone_c;
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-- empty_timeout
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-- trigger
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NextCase <= 6;
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wait until ProcessDone = AllProcessesDone_c;
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-- trigger
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-- cmd_full
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NextCase <= 7;
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wait until ProcessDone = AllProcessesDone_c;
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-- cmd_full
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NextCase <= 8;
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wait until ProcessDone = AllProcessesDone_c;
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-- data_full
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NextCase <= 9;
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NextCase <= 8;
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wait until ProcessDone = AllProcessesDone_c;
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TbRunning <= false;
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wait;
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@ -196,50 +192,44 @@ begin
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work.psi_ms_daq_daq_dma_tb_case_unaligned.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- odd_size
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wait until NextCase = 2;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_odd_size.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- no_data_read
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wait until NextCase = 3;
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wait until NextCase = 2;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_no_data_read.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- input_empty
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wait until NextCase = 4;
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wait until NextCase = 3;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_input_empty.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- timetout
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wait until NextCase = 5;
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wait until NextCase = 4;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_timetout.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- empty_timeout
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wait until NextCase = 6;
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wait until NextCase = 5;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_empty_timeout.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- trigger
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wait until NextCase = 7;
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wait until NextCase = 6;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_trigger.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- cmd_full
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wait until NextCase = 8;
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wait until NextCase = 7;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_cmd_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_control_c) <= '1';
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-- data_full
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wait until NextCase = 9;
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wait until NextCase = 8;
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ProcessDone(TbProcNr_control_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_data_full.control(Clk, Rst, DaqSm_Cmd, DaqSm_Cmd_Vld, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Generics_c);
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wait for 1 ps;
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@ -262,50 +252,44 @@ begin
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work.psi_ms_daq_daq_dma_tb_case_unaligned.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- odd_size
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wait until NextCase = 2;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_odd_size.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- no_data_read
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wait until NextCase = 3;
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wait until NextCase = 2;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_no_data_read.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- input_empty
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wait until NextCase = 4;
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wait until NextCase = 3;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_input_empty.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- timetout
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wait until NextCase = 5;
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wait until NextCase = 4;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_timetout.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- empty_timeout
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wait until NextCase = 6;
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wait until NextCase = 5;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_empty_timeout.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- trigger
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wait until NextCase = 7;
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wait until NextCase = 6;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_trigger.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- cmd_full
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wait until NextCase = 8;
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wait until NextCase = 7;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_cmd_full.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_input_c) <= '1';
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-- data_full
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wait until NextCase = 9;
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wait until NextCase = 8;
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ProcessDone(TbProcNr_input_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_data_full.input(Clk, Inp_Vld, Inp_Rdy, Inp_Data, Generics_c);
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wait for 1 ps;
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@ -328,50 +312,44 @@ begin
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work.psi_ms_daq_daq_dma_tb_case_unaligned.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- odd_size
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wait until NextCase = 2;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_odd_size.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- no_data_read
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wait until NextCase = 3;
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wait until NextCase = 2;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_no_data_read.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- input_empty
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wait until NextCase = 4;
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wait until NextCase = 3;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_input_empty.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- timetout
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wait until NextCase = 5;
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wait until NextCase = 4;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_timetout.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- empty_timeout
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wait until NextCase = 6;
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wait until NextCase = 5;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_empty_timeout.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- trigger
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wait until NextCase = 7;
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wait until NextCase = 6;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_trigger.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- cmd_full
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wait until NextCase = 8;
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wait until NextCase = 7;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_cmd_full.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_cmd_c) <= '1';
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-- data_full
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wait until NextCase = 9;
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wait until NextCase = 8;
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ProcessDone(TbProcNr_mem_cmd_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_data_full.mem_cmd(Clk, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Generics_c);
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wait for 1 ps;
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@ -394,50 +372,44 @@ begin
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work.psi_ms_daq_daq_dma_tb_case_unaligned.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- odd_size
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wait until NextCase = 2;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_odd_size.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- no_data_read
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wait until NextCase = 3;
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wait until NextCase = 2;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_no_data_read.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- input_empty
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wait until NextCase = 4;
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wait until NextCase = 3;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_input_empty.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- timetout
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wait until NextCase = 5;
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wait until NextCase = 4;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_timetout.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- empty_timeout
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wait until NextCase = 6;
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wait until NextCase = 5;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_empty_timeout.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- trigger
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wait until NextCase = 7;
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wait until NextCase = 6;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_trigger.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- cmd_full
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wait until NextCase = 8;
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wait until NextCase = 7;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_cmd_full.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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ProcessDone(TbProcNr_mem_dat_c) <= '1';
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-- data_full
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wait until NextCase = 9;
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wait until NextCase = 8;
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ProcessDone(TbProcNr_mem_dat_c) <= '0';
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work.psi_ms_daq_daq_dma_tb_case_data_full.mem_dat(Clk, Mem_DatData, Mem_DatVld, Mem_DatRdy, Generics_c);
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wait for 1 ps;
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@ -1,109 +0,0 @@
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------------------------------------------------------------
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-- Libraries
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------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.psi_common_math_pkg.all;
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use work.psi_common_logic_pkg.all;
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use work.psi_common_array_pkg.all;
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use work.psi_ms_daq_pkg.all;
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library work;
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use work.psi_ms_daq_daq_dma_tb_pkg.all;
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library work;
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use work.psi_tb_txt_util.all;
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use work.psi_tb_compare_pkg.all;
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use work.psi_tb_activity_pkg.all;
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------------------------------------------------------------
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-- Package Header
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------------------------------------------------------------
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package psi_ms_daq_daq_dma_tb_case_odd_size is
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procedure control (
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signal Clk : in std_logic;
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signal Rst : inout std_logic;
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signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
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signal DaqSm_Cmd_Vld : inout std_logic;
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signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
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signal DaqSm_Resp_Vld : in std_logic;
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signal DaqSm_Resp_Rdy : inout std_logic;
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constant Generics_c : Generics_t);
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procedure input (
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signal Clk : in std_logic;
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signal Inp_Vld : inout std_logic_vector;
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signal Inp_Rdy : in std_logic_vector;
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signal Inp_Data : inout Input2Daq_Data_a;
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constant Generics_c : Generics_t);
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procedure mem_cmd (
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signal Clk : in std_logic;
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signal Mem_CmdAddr : in std_logic_vector;
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signal Mem_CmdSize : in std_logic_vector;
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signal Mem_CmdVld : in std_logic;
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signal Mem_CmdRdy : inout std_logic;
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constant Generics_c : Generics_t);
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procedure mem_dat (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_DatData : in std_logic_vector;
|
||||
signal Mem_DatVld : in std_logic;
|
||||
signal Mem_DatRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t);
|
||||
|
||||
end package;
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Package Body
|
||||
------------------------------------------------------------
|
||||
package body psi_ms_daq_daq_dma_tb_case_odd_size is
|
||||
procedure control (
|
||||
signal Clk : in std_logic;
|
||||
signal Rst : inout std_logic;
|
||||
signal DaqSm_Cmd : inout DaqSm2DaqDma_Cmd_t;
|
||||
signal DaqSm_Cmd_Vld : inout std_logic;
|
||||
signal DaqSm_Resp : in DaqDma2DaqSm_Resp_t;
|
||||
signal DaqSm_Resp_Vld : in std_logic;
|
||||
signal DaqSm_Resp_Rdy : inout std_logic;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
assert false report "Case ODD_SIZE Procedure CONTROL: No Content added yet!" severity warning;
|
||||
end procedure;
|
||||
|
||||
procedure input (
|
||||
signal Clk : in std_logic;
|
||||
signal Inp_Vld : inout std_logic_vector;
|
||||
signal Inp_Rdy : in std_logic_vector;
|
||||
signal Inp_Data : inout Input2Daq_Data_a;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
assert false report "Case ODD_SIZE Procedure INPUT: No Content added yet!" severity warning;
|
||||
end procedure;
|
||||
|
||||
procedure mem_cmd (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_CmdAddr : in std_logic_vector;
|
||||
signal Mem_CmdSize : in std_logic_vector;
|
||||
signal Mem_CmdVld : in std_logic;
|
||||
signal Mem_CmdRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
assert false report "Case ODD_SIZE Procedure MEM_CMD: No Content added yet!" severity warning;
|
||||
end procedure;
|
||||
|
||||
procedure mem_dat (
|
||||
signal Clk : in std_logic;
|
||||
signal Mem_DatData : in std_logic_vector;
|
||||
signal Mem_DatVld : in std_logic;
|
||||
signal Mem_DatRdy : inout std_logic;
|
||||
constant Generics_c : Generics_t) is
|
||||
begin
|
||||
assert false report "Case ODD_SIZE Procedure MEM_DAT: No Content added yet!" severity warning;
|
||||
end procedure;
|
||||
|
||||
end;
|
||||
@ -75,6 +75,10 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
InitCase(Clk, Rst);
|
||||
print(">> -- Unaligned --");
|
||||
|
||||
print("TODO: Handle empty timeout sample");
|
||||
print("TODO: Very short TFs (no read from FIFO)");
|
||||
print("TODO: Handle end of transfer because no more data");
|
||||
|
||||
-- End Unaligned
|
||||
print(">> End Unaligned");
|
||||
InitCase(Clk, Rst);
|
||||
@ -88,7 +92,7 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- QWord Split
|
||||
wait for 10 us;
|
||||
wait for 1 us;
|
||||
print(">> QWord Split");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(1);
|
||||
@ -101,7 +105,7 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- QWord Split, Rdy Toggling
|
||||
wait for 10 us;
|
||||
wait for 1 us;
|
||||
print(">> QWord Split, Rdy Toggling");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(2);
|
||||
@ -114,7 +118,7 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- mixed streams
|
||||
wait for 10 us;
|
||||
wait for 1 us;
|
||||
print(">> mixed streams");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(3);
|
||||
@ -132,11 +136,57 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
CheckResp(2, 11, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- End Aligned
|
||||
-- End Aligned
|
||||
wait for 1 us;
|
||||
print(">> End Aligned");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(4);
|
||||
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01231000#, 34, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 34, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- Unaligned end by trigger (leads to flush)
|
||||
-- Unaligned end by trigger (with rem-word)
|
||||
wait for 1 us;
|
||||
print(">> Unaligned end by trigger (with rem-word)");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(5);
|
||||
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01231000#, 64, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 29, Trigger_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- Unaligned end by trigger (without rem-word)
|
||||
wait for 1 us;
|
||||
print(">> Unaligned end by trigger (without rem-word)");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(6);
|
||||
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01231000#, 64, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 25, Trigger_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
-- Unaligned end by timeout (leads to flush)
|
||||
-- Unaligned end by timeout
|
||||
wait for 1 us;
|
||||
print(">> Unaligned end by timeout");
|
||||
InitCase(Clk, Rst);
|
||||
InitSubCase(7);
|
||||
ApplyCmd(2, 16#01230000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01231000#, 64, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 29, Timeout_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
ApplyCmd(2, 16#01232000#, 30, DaqSm_Cmd, DaqSm_Cmd_Vld, Clk);
|
||||
CheckResp(2, 30, NoEnd_s, DaqSm_Resp, DaqSm_Resp_Vld, DaqSm_Resp_Rdy, Clk);
|
||||
WaitAllProc(Clk);
|
||||
|
||||
end procedure;
|
||||
|
||||
@ -172,7 +222,31 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
ApplyData(1, 20, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 24);
|
||||
ApplyData(1, 12, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 20+24);
|
||||
ApplyData(2, 12, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 32+32);
|
||||
ProcDone_V(0) := '1';
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
-- End Aligned
|
||||
WaitForCase(4, Clk);
|
||||
ApplyData(2, 30+34+30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk);
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
-- Unaligned end by trigger (with rem-word)
|
||||
WaitForCase(5, Clk);
|
||||
ApplyData(2, 30+29, Trigger_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 0);
|
||||
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 30+29);
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
-- Unaligned end by trigger (without rem-word)
|
||||
WaitForCase(6, Clk);
|
||||
ApplyData(2, 30+25, Trigger_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 0);
|
||||
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 30+25);
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
-- Unaligned end by timeout
|
||||
WaitForCase(7, Clk);
|
||||
ApplyData(2, 30+29, Timeout_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 0);
|
||||
ApplyData(2, 30, NoEnd_s, Inp_Vld, Inp_Rdy, Inp_Data, Clk, 30+29);
|
||||
ProcDone_V(0) := '1';
|
||||
|
||||
end procedure;
|
||||
|
||||
procedure mem_cmd (
|
||||
@ -206,13 +280,41 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
|
||||
-- mixed streams
|
||||
WaitForCase(3, Clk);
|
||||
CheckMemCmd( 16#02000000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01000000#, 23, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#02000001#, 33, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01000001#, 21, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01000002#, 11, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#02000002#, 11, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
CheckMemCmd( 16#02000000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk, "2.0");
|
||||
CheckMemCmd( 16#01000000#, 23, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk, "1.0");
|
||||
CheckMemCmd( 16#02000001#, 33, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk, "2.1");
|
||||
CheckMemCmd( 16#01000001#, 21, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk, "1.1");
|
||||
CheckMemCmd( 16#01000002#, 11, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk, "1.2");
|
||||
CheckMemCmd( 16#02000002#, 11, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk, "2.2");
|
||||
ProcDone_V(1) := '1';
|
||||
|
||||
-- End Aligned
|
||||
WaitForCase(4, Clk);
|
||||
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01231000#, 34, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
|
||||
-- Unaligned end by trigger (with rem-word)
|
||||
WaitForCase(5, Clk);
|
||||
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01231000#, 29, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
|
||||
-- Unaligned end by trigger (without rem-word)
|
||||
WaitForCase(6, Clk);
|
||||
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01231000#, 25, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
|
||||
-- Unaligned end by timeout
|
||||
WaitForCase(7, Clk);
|
||||
CheckMemCmd( 16#01230000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01231000#, 29, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
CheckMemCmd( 16#01232000#, 30, 0, Mem_CmdAddr, Mem_CmdSize, Mem_CmdVld, Mem_CmdRdy, Clk);
|
||||
ProcDone_V(1) := '1';
|
||||
end procedure;
|
||||
|
||||
procedure mem_dat (
|
||||
@ -252,7 +354,34 @@ package body psi_ms_daq_daq_dma_tb_case_unaligned is
|
||||
CheckMemData(11, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 23+21, "1.2");
|
||||
CheckMemData(11, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+33, "2.2");
|
||||
ProcDone_V(2) := '1';
|
||||
|
||||
-- End Unaligned
|
||||
WaitForCase(4, Clk);
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
|
||||
CheckMemData(34, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+34, "1.2");
|
||||
ProcDone_V(2) := '1';
|
||||
|
||||
-- Unaligned end by trigger (with rem-word)
|
||||
WaitForCase(5, Clk);
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
|
||||
CheckMemData(29, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29, "1.2");
|
||||
ProcDone_V(2) := '1';
|
||||
|
||||
-- Unaligned end by trigger (without rem-word)
|
||||
WaitForCase(6, Clk);
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
|
||||
CheckMemData(25, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+25, "1.2");
|
||||
ProcDone_V(2) := '1';
|
||||
|
||||
-- Unaligned end by timeout
|
||||
WaitForCase(7, Clk);
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 0, "1.0");
|
||||
CheckMemData(29, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30, "1.1");
|
||||
CheckMemData(30, 0, Mem_DatData, Mem_DatVld, Mem_DatRdy, Clk, 30+29, "1.2");
|
||||
ProcDone_V(2) := '1';
|
||||
end procedure;
|
||||
|
||||
end;
|
||||
|
||||
@ -75,7 +75,8 @@ package psi_ms_daq_daq_dma_tb_pkg is
|
||||
signal Mem_CmdSize : in std_logic_vector;
|
||||
signal Mem_CmdVld : in std_logic;
|
||||
signal Mem_CmdRdy : out std_logic;
|
||||
signal Clk : in std_logic);
|
||||
signal Clk : in std_logic;
|
||||
Msg : in string := "");
|
||||
|
||||
shared variable TestCase_v : integer := -1;
|
||||
shared variable ProcDone_V : std_logic_vector(0 to 2);
|
||||
@ -124,14 +125,14 @@ package body psi_ms_daq_daq_dma_tb_pkg is
|
||||
DaqSm_Resp_Rdy <= '1';
|
||||
wait until rising_edge(Clk) and DaqSm_Resp_Vld = '1';
|
||||
if Trigger_s = EndType then
|
||||
StdlCompare(1, DaqSm_Resp.Trigger, "Response has not set TRIGGER");
|
||||
StdlCompare(1, DaqSm_Resp.Trigger, "CHEK_RESP: Response has not set TRIGGER");
|
||||
else
|
||||
StdlCompare(0, DaqSm_Resp.Trigger, "Response has not cleared TRIGGER");
|
||||
StdlCompare(0, DaqSm_Resp.Trigger, "CHEK_RESP: Response has not cleared TRIGGER");
|
||||
end if;
|
||||
StdlvCompareInt(Size, DaqSm_Resp.Size, "Wrong size in response");
|
||||
IntCompare(Stream, DaqSm_Resp.Stream, "Wrong stream number in response");
|
||||
StdlvCompareInt(Size, DaqSm_Resp.Size, "CHEK_RESP: Wrong size in response");
|
||||
IntCompare(Stream, DaqSm_Resp.Stream, "CHEK_RESP: Wrong stream number in response");
|
||||
wait until rising_edge(Clk);
|
||||
StdlCompare(0, DaqSm_Resp_Vld, "Response valid did not go low");
|
||||
StdlCompare(0, DaqSm_Resp_Vld, "CHEK_RESP: Response valid did not go low");
|
||||
end procedure;
|
||||
|
||||
procedure ApplyData( Stream : in integer;
|
||||
@ -144,7 +145,8 @@ package body psi_ms_daq_daq_dma_tb_pkg is
|
||||
Offset : in integer := 0) is
|
||||
variable DataCnt_v : unsigned(7 downto 0) := to_unsigned(Offset, 8);
|
||||
begin
|
||||
assert EndType = NoEnd_s report "###ERROR###: EndType not yet implemented" severity error;
|
||||
assert EndType = NoEnd_s or EndType = Trigger_s or EndType = Timeout_s
|
||||
report "###ERROR###: APPLY_DATA: EndType not yet implemented" severity error;
|
||||
Inp_Vld(Stream) <= '1';
|
||||
for dw in 0 to (Bytes+7)/8-1 loop
|
||||
for byte in 0 to 7 loop
|
||||
@ -157,7 +159,17 @@ package body psi_ms_daq_daq_dma_tb_pkg is
|
||||
end loop;
|
||||
Inp_Data(Stream).Last <= '0';
|
||||
Inp_Data(Stream).IsTo <= '0';
|
||||
Inp_Data(Stream).IsTrig <= '0';
|
||||
Inp_Data(Stream).IsTrig <= '0';
|
||||
if dw = (Bytes+7)/8-1 then
|
||||
if EndType = Trigger_s then
|
||||
Inp_Data(Stream).Last <= '1';
|
||||
Inp_Data(Stream).IsTrig <= '1';
|
||||
elsif EndType = Timeout_s then
|
||||
Inp_Data(Stream).Last <= '1';
|
||||
Inp_Data(Stream).IsTo <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if Bytes-dw*8 > 8 then
|
||||
Inp_Data(Stream).Bytes <= std_logic_vector(to_unsigned(8, 4));
|
||||
else
|
||||
@ -192,7 +204,7 @@ package body psi_ms_daq_daq_dma_tb_pkg is
|
||||
if dw*8+byte >= Bytes then
|
||||
-- nothing to compare
|
||||
else
|
||||
StdlvCompareInt (DataCnt_v, Mem_DatData(8*(byte+1)-1 downto 8*byte), "Wrong Data QW[" & to_string(dw) & "] Byte [" & to_string(byte) & "] - " & Msg, false);
|
||||
StdlvCompareInt (DataCnt_v, Mem_DatData(8*(byte+1)-1 downto 8*byte), "MEM_DATA: Wrong Data QW[" & to_string(dw) & "] Byte [" & to_string(byte) & "] - " & Msg, false);
|
||||
DataCnt_v := (DataCnt_v + 1) mod 256;
|
||||
end if;
|
||||
end loop;
|
||||
@ -202,11 +214,12 @@ package body psi_ms_daq_daq_dma_tb_pkg is
|
||||
procedure CheckMemCmd( Address : in integer;
|
||||
Bytes : in integer;
|
||||
RdyDelay : in integer := 0;
|
||||
signal Mem_CmdAddr : in std_logic_vector;
|
||||
signal Mem_CmdSize : in std_logic_vector;
|
||||
signal Mem_CmdVld : in std_logic;
|
||||
signal Mem_CmdRdy : out std_logic;
|
||||
signal Clk : in std_logic) is
|
||||
signal Mem_CmdAddr : in std_logic_vector;
|
||||
signal Mem_CmdSize : in std_logic_vector;
|
||||
signal Mem_CmdVld : in std_logic;
|
||||
signal Mem_CmdRdy : out std_logic;
|
||||
signal Clk : in std_logic;
|
||||
Msg : in string := "") is
|
||||
begin
|
||||
if RdyDelay > 0 then
|
||||
Mem_CmdRdy <= '0';
|
||||
@ -220,13 +233,13 @@ package body psi_ms_daq_daq_dma_tb_pkg is
|
||||
end loop;
|
||||
end if;
|
||||
Mem_CmdRdy <= '1';
|
||||
StdlCompare(1, Mem_CmdVld, "Mem_CmdVld did not stay high");
|
||||
StdlvCompareInt(Address, Mem_CmdAddr, "Wrong Address", false);
|
||||
StdlvCompareInt(Bytes, Mem_CmdSize, "Wrong Size", false);
|
||||
StdlCompare(1, Mem_CmdVld, "MEM CMD: Mem_CmdVld did not stay high - " & Msg);
|
||||
StdlvCompareInt(Address, Mem_CmdAddr, "MEM_CMD: Wrong Address - " & Msg, false);
|
||||
StdlvCompareInt(Bytes, Mem_CmdSize, "MEM_CMD: Wrong Size - " & Msg, false);
|
||||
wait until rising_edge(Clk);
|
||||
wait for 1 ns;
|
||||
Mem_CmdRdy <= '0';
|
||||
StdlCompare(0, Mem_CmdVld, "Mem_CmdVld did not go low");
|
||||
StdlCompare(0, Mem_CmdVld, "MEM_CMD: Mem_CmdVld did not go low - " & Msg);
|
||||
end procedure;
|
||||
|
||||
procedure InitCase( signal Clk : in std_logic;
|
||||
|
||||
Reference in New Issue
Block a user