AEK_8220_Libraries/firmware_vhdl_psi_multi_stream_daq
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BUGFIX: Bugfixes from bringup

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This commit is contained in:
Oliver Bruendler
2019-06-18 13:45:09 +02:00
parent 4399e89830
commit 828759a5a6
6 changed files with 39 additions and 23 deletions
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doc/psi_multi_stream_daq.docx
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27
hdl/psi_ms_daq_axi.vhd
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@ -130,6 +130,15 @@ end entity;
------------------------------------------------------------------------------
architecture rtl of psi_ms_daq_axi is
-- Config Arrays with correct size
constant StreamWidth_c : t_ainteger(0 to Streams_g-1) := StreamWidth_g(0 to Streams_g-1);
constant StreamPrio_c : t_ainteger(0 to Streams_g-1) := StreamPrio_g(0 to Streams_g-1);
constant StreamBuffer_c : t_ainteger(0 to Streams_g-1) := StreamBuffer_g(0 to Streams_g-1);
constant StreamTimeout_c : t_areal(0 to Streams_g-1) := StreamTimeout_g(0 to Streams_g-1);
constant StreamClkFreq_c : t_areal(0 to Streams_g-1) := StreamClkFreq_g(0 to Streams_g-1);
constant StreamTsFifoDepth_c : t_ainteger(0 to Streams_g-1) := StreamTsFifoDepth_g(0 to Streams_g-1);
constant StreamUseTs_c : t_abool(0 to Streams_g-1) := StreamUseTs_g(0 to Streams_g-1);
-- Input/Statemachine Signals
signal InpSm_HasTlast : std_logic_vector(Streams_g-1 downto 0);
signal InpSm_TsVld : std_logic_vector(Streams_g-1 downto 0);
@ -262,7 +271,7 @@ begin
--------------------------------------------
g_input : for str in 0 to Streams_g-1 generate
signal InRst : std_logic;
signal StrInput : std_logic_vector(StreamWidth_g(str)-1 downto 0);
signal StrInput : std_logic_vector(StreamWidth_c(str)-1 downto 0);
begin
-- Reset if stream is disabled
InRst <= M_Axi_Areset or not Cfg_StrEna(str) or not Cfg_GlbEna;
@ -271,12 +280,12 @@ begin
-- Instantiation
i_input : entity work.psi_ms_daq_input
generic map (
StreamWidth_g => StreamWidth_g(str),
StreamBuffer_g => StreamBuffer_g(str),
StreamTimeout_g => StreamTimeout_g(str),
StreamClkFreq_g => StreamClkFreq_g(str),
StreamTsFifoDepth_g => StreamTsFifoDepth_g(str),
StreamUseTs_g => StreamUseTs_g(str)
StreamWidth_g => StreamWidth_c(str),
StreamBuffer_g => StreamBuffer_c(str),
StreamTimeout_g => StreamTimeout_c(str),
StreamClkFreq_g => StreamClkFreq_c(str),
StreamTsFifoDepth_g => StreamTsFifoDepth_c(str),
StreamUseTs_g => StreamUseTs_c(str)
)
port map (
Str_Clk => Str_Clk(str),
@ -315,8 +324,8 @@ begin
i_statemachine : entity work.psi_ms_daq_daq_sm
generic map (
Streams_g => Streams_g,
StreamPrio_g => StreamPrio_g,
StreamWidth_g => StreamWidth_g,
StreamPrio_g => StreamPrio_c,
StreamWidth_g => StreamWidth_c,
Windows_g => MaxWindows_g,
MinBurstSize_g => MinBurstSize_g,
MaxBurstSize_g => MaxBurstSize_g

9
hdl/psi_ms_daq_daq_sm.vhd
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@ -190,6 +190,9 @@ architecture rtl of psi_ms_daq_daq_sm is
end record;
signal r, r_next : two_process_r;
attribute mark_debug : string;
attribute mark_debug of r : signal is "true";
-- Todo: mask streams that already have a transfer open at the input
begin
@ -272,7 +275,7 @@ begin
v.State := ReadCtxStr_s;
v.HndlStream := GetStreamNrFromGrant(r.GrantPrio1Reg, 1);
-- If data is still pending, check for responses to schedule next transfer
elsif unsigned(GetBitsOfStreamPrio(r.DataPending, 1)) /= 0 then
elsif (unsigned(GetBitsOfStreamPrio(r.DataPending, 1)) /= 0) and (count(StreamPrio_g, 1) /= 0) then -- the term after the AND is required because unsigned(null-range) is not guaranteed to be zero in Vivado
v.State := CheckResp_s;
-- Otherwise check lower priority streams
else
@ -285,7 +288,7 @@ begin
v.State := ReadCtxStr_s;
v.HndlStream := GetStreamNrFromGrant(r.GrantPrio2Reg, 2);
-- If data is still pending, check for responses to schedule next transfer
elsif unsigned(GetBitsOfStreamPrio(r.DataPending, 2)) /= 0 then
elsif (unsigned(GetBitsOfStreamPrio(r.DataPending, 2)) /= 0) and (count(StreamPrio_g, 2) /= 0) then -- the term after the AND is required because unsigned(null-range) is not guaranteed to be zero in Vivado
v.State := CheckResp_s;
-- Otherwise check lower priority streams
else
@ -479,7 +482,7 @@ begin
end if;
end if;
-- wraparound for ringbuffer case
if (r.HndlPtr1 = r.HndlWinEnd) and (r.HndlRingbuf = '1') then
if (r.HndlPtr1 = r.HndlWinEnd) and (r.HndlRingbuf = '1') and (Dma_Resp.Trigger = '0') then
v.HndlPtr2 := std_logic_vector(unsigned(r.HndlPtr1) - unsigned(r.HndlWinSize));
end if;
-- Update window information step 2 (limit to maximum value)

12
sim/config.tcl
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@ -88,12 +88,12 @@ add_sources "../tb" {
#TB Runs
create_tb_run "psi_ms_daq_input_tb"
tb_run_add_arguments \
"-gStreamWidth_g=8 -gVldPulsed=false" \
"-gStreamWidth_g=8 -gVldPulsed=true" \
"-gStreamWidth_g=16 -gVldPulsed=false" \
"-gStreamWidth_g=32 -gVldPulsed=false" \
"-gStreamWidth_g=64 -gVldPulsed=false" \
"-gStreamWidth_g=64 -gVldPulsed=true"
"-gStreamWidth_g=8 -gVldPulsed_g=false" \
"-gStreamWidth_g=8 -gVldPulsed_g=true" \
"-gStreamWidth_g=16 -gVldPulsed_g=false" \
"-gStreamWidth_g=32 -gVldPulsed_g=false" \
"-gStreamWidth_g=64 -gVldPulsed_g=false" \
"-gStreamWidth_g=64 -gVldPulsed_g=true"
add_tb_run
create_tb_run "psi_ms_daq_daq_sm_tb"

5
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_always_trig.vhd
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@ -79,8 +79,11 @@ package body psi_ms_daq_input_tb_case_always_trig is
Str_Data <= std_logic_vector(to_unsigned(SplCnt, Generics_c.StreamWidth_g));
wait until rising_edge(Str_Clk);
if Generics_c.VldPulsed_g then
Str_Trig <= '0';
Str_Vld <= '0';
-- Remove trigger after last sample of test, otherwise it stays latched and affects the next testcase
if SplCnt = 17 then
Str_Trig <= '0';
end if;
Str_Ts <= std_logic_vector(to_unsigned(0, Str_Ts'length));
Str_Data <= std_logic_vector(to_unsigned(0, Generics_c.StreamWidth_g));
wait until rising_edge(Str_Clk);

9
tb/psi_ms_daq_input/psi_ms_daq_input_tb_case_backpressure.vhd
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@ -88,6 +88,10 @@ package body psi_ms_daq_input_tb_case_backpressure is
Str_Vld <= '0';
Str_Data <= std_logic_vector(to_unsigned(0, Generics_c.StreamWidth_g));
wait until rising_edge(Str_Clk);
-- Fix in case of sample not being accepted
if Str_Rdy = '0' then
Samples_v := Samples_v - 1;
end if;
end if;
end loop;
@ -125,10 +129,7 @@ package body psi_ms_daq_input_tb_case_backpressure is
wait until rising_edge(Str_Clk) and Str_Rdy = '1';
Samples_v := Samples_v + 1;
end loop;
Str_Vld <= '0';
Str_Vld <= '0';
end procedure;