DEVEL: Allow different clocks for TMEM and SMEM
This commit is contained in:
Oliver Bruendler
@ -38,21 +38,20 @@ entity psi_ms_daq is
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Str_Rdy : out std_logic_vector(Streams_g-1 downto 0);
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Str_Trig : in std_logic_vector(Streams_g-1 downto 0);
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-- Tosca Control Signals
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Tosca_Clk : in std_logic; -- 200 MHz tosca clock
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Tmem_Rst : in std_logic;
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Smem_Rst : in std_logic;
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-- TMEM Interface
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Tmem_Clk : in std_logic;
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Tmem_Rst : in std_logic;
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TmemAcq : in TmemRqst_t;
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AcqTmem : out TmemResp_t;
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-- SMEM Interface
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Smem_Clk : in std_logic;
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Smem_Rst : in std_logic;
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AcqSmem : out ToSmemWr_t;
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SmemAcq : in FromSmemWr_t;
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-- Miscellaneous
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Irq : out std_logic
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Irq : out std_logic -- TMEM clock domain
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);
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end entity;
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@ -119,16 +118,6 @@ architecture rtl of psi_ms_daq is
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begin
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--------------------------------------------
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-- Reset
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--------------------------------------------
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p_rst : process(Tosca_Clk)
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begin
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if rising_edge(Tosca_Clk) then
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Rst <= Tmem_Rst or Smem_Rst;
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end if;
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end process;
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--------------------------------------------
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-- TMEM Interface
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--------------------------------------------
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@ -138,24 +127,26 @@ begin
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MaxWindows_g => MaxWindows_g
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)
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port map (
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ToscaClk => Tosca_Clk,
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Rst => Rst,
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ClkTmem => Tmem_Clk,
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RstTmem => Tmem_Rst,
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TmemRqst => TmemAcq,
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TmemResp => AcqTmem,
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CtxStr_Cmd => CtxStr_Cmd,
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CtxStr_Resp => CtxStr_Resp,
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CtxWin_Cmd => CtxWin_Cmd,
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CtxWin_Resp => CtxWin_Resp,
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StrIrq => Stat_StrIrq,
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StrEna => Cfg_StrEna,
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GlbEna => Cfg_GlbEna,
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IrqOut => Irq,
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InLevel => InpSm_Level,
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IrqOut => Irq,
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PostTrig => Cfg_PostTrig,
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Arm => Cfg_Arm,
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IsArmed => Stat_IsArmed,
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IsRecording => Stat_IsRecording,
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RecMode => Cfg_RecMode
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RecMode => Cfg_RecMode,
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ClkSmem => Smem_Clk,
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RstSmem => Smem_Rst,
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CtxStr_Cmd => CtxStr_Cmd,
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CtxStr_Resp => CtxStr_Resp,
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CtxWin_Cmd => CtxWin_Cmd,
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CtxWin_Resp => CtxWin_Resp,
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InLevel => InpSm_Level,
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StrIrq => Stat_StrIrq,
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StrEna => Cfg_StrEna,
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GlbEna => Cfg_GlbEna
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);
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--------------------------------------------
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@ -166,7 +157,7 @@ begin
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signal StrInput : std_logic_vector(StreamWidth_g(str)-1 downto 0);
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begin
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-- Reset if stream is disabled
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InRst <= Rst or not Cfg_StrEna(str) or not Cfg_GlbEna;
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InRst <= Smem_Rst or not Cfg_StrEna(str) or not Cfg_GlbEna;
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StrInput <= Str_Data(str)(StrInput'range);
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-- Instantiation
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@ -186,13 +177,15 @@ begin
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Str_Data => StrInput,
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Str_Trig => Str_Trig(str),
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Str_Ts => Str_Ts(str),
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Clk => Tosca_Clk,
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Rst => InRst,
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ClkTmem => Tmem_Clk,
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RstTmem => Tmem_Rst,
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PostTrigSpls => Cfg_PostTrig(str),
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Mode => Cfg_RecMode(str),
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Arm => Cfg_Arm(str),
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IsArmed => Stat_IsArmed(str),
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IsRecording => Stat_IsRecording(str),
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ClkSmem => Smem_Clk,
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RstSmem => InRst,
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Daq_Vld => InpDma_Vld(str),
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Daq_Rdy => InpDma_Rdy(str),
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Daq_Data => InpDma_Data(str),
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@ -221,8 +214,8 @@ begin
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MaxBurstSize_g => MaxBurstSize_g
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)
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port map (
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Clk => Tosca_Clk,
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Rst => Rst,
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Clk => Smem_Clk,
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Rst => Smem_Rst,
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GlbEna => Cfg_GlbEna,
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StrEna => Cfg_StrEna,
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StrIrq => Stat_StrIrq,
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@ -253,8 +246,8 @@ begin
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Streams_g => Streams_g
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)
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port map (
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Clk => Tosca_Clk,
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Rst => Rst,
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Clk => Smem_Clk,
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Rst => Smem_Rst,
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DaqSm_Cmd => SmDma_Cmd,
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DaqSm_Cmd_Vld => SmDma_CmdVld,
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DaqSm_Resp => DmaSm_Resp,
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@ -284,8 +277,8 @@ begin
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MaxOpenTransactions_g => Streams_g
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)
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port map (
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Clk => Tosca_Clk,
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Rst => Rst,
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Clk => Smem_Clk,
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Rst => Smem_Rst,
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Cmd_Addr => DmaMem_CmdAddr,
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Cmd_Size => DmaMem_CmdSize,
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Cmd_Vld => DmaMem_CmdVld,
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@ -38,14 +38,18 @@ entity psi_ms_daq_input is
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Str_Trig : in std_logic; -- $$ proc=stream $$
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Str_Ts : in std_logic_vector(63 downto 0); -- $$ proc=stream $$
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-- DAQ control signals
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Clk : in std_logic; -- $$ type=clk; freq=200e6; proc=daq,stream $$
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Rst : in std_logic; -- $$ type=rst; clk=Clk $$
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-- Configuration Signals
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ClkTmem : in std_logic;
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RstTmem : in std_logic;
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PostTrigSpls : in std_logic_vector(31 downto 0); -- $$ proc=daq $$
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Mode : in RecMode_t; -- $$ proc=daq $$
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Arm : in std_logic; -- $$ proc=stream $$
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IsArmed : out std_logic; -- $$ proc=stream $$
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IsRecording : out std_logic; -- $$ proc=stream $$
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IsRecording : out std_logic; -- $$ proc=stream $$
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-- DAQ control signals
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ClkSmem : in std_logic; -- $$ type=clk; freq=200e6; proc=daq,stream $$
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RstSmem : in std_logic; -- $$ type=rst; clk=Clk $$
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-- DAQ logic Connections
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Daq_Vld : out std_logic; -- $$ proc=daq $$
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@ -99,11 +103,6 @@ architecture rtl of psi_ms_daq_input is
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-- General Instantiation signals
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signal Str_Rst : std_logic;
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-- clock Crossing Signals
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signal Str_Arm : std_logic;
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signal StatusCcIn : std_logic_vector(TlastCntWidth_c+1 downto 0);
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signal StatusCcOut : std_logic_vector(TlastCntWidth_c+1 downto 0);
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-- Data FIFO signals
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signal DataFifo_InRdy : std_logic;
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@ -127,12 +126,19 @@ architecture rtl of psi_ms_daq_input is
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signal TsFifo_AlmFull : std_logic;
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signal TsFifo_Empty : std_logic;
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-- Clock Crossing Signals
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signal PostTrigSpls_Sync : std_logic_vector(PostTrigSpls'range);
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signal Mode_Sync : RecMode_t;
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signal Arm_Sync : std_logic;
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signal RstTmem_Sync : std_logic;
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signal RstAcq_Sync : std_logic;
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begin
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--------------------------------------------
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-- Combinatorial Process
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--------------------------------------------
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p_comb : process( r,
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Str_Vld, Str_Data, Str_Trig, Str_Ts, PostTrigSpls, Daq_Rdy, Ts_Rdy, Mode, Str_Arm,
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Str_Vld, Str_Data, Str_Trig, Str_Ts, PostTrigSpls_Sync, Daq_Rdy, Ts_Rdy, Mode_Sync, Arm_Sync,
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DataFifo_InRdy, DataFifo_InData, DataFifo_OutData, Daq_Vld_I, Daq_Data_I, Daq_HasLast_I, Ts_Vld_I, OutTlastCnt, TsFifo_AlmFull, TsFifo_Empty,
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InTlastCnt, TsFifo_InRdy, TsFifo_RdData)
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variable v : two_process_r;
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@ -151,8 +157,8 @@ begin
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-- Default values
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v.DataFifoIsTo := '0';
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v.DataFifoIsTrig := '0';
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v.ModeReg := Mode;
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v.ArmReg := Str_Arm;
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v.ModeReg := Mode_Sync;
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v.ArmReg := Arm_Sync;
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-- Masking trigger according to recording mode
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case r.ModeReg is
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@ -210,12 +216,12 @@ begin
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end if;
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elsif (r.TrigLatch = '1') or (TrigMasked_v = '1') then
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-- Handle incoming trigger sample
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if unsigned(PostTrigSpls) = 0 then
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if unsigned(PostTrigSpls_Sync) = 0 then
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v.DataFifoIsTrig := '1';
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v.DataFifoVld := r.DataFifoVld or r.RecEna;
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v.RecEna := '0'; -- stop recording after frame
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else
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v.PostTrigCnt := unsigned(PostTrigSpls);
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v.PostTrigCnt := unsigned(PostTrigSpls_Sync);
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end if;
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end if;
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end if;
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@ -273,7 +279,7 @@ begin
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end case;
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-- Handle Arming Logic
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if (r.ModeReg /= Mode) or (r.ModeReg = RecMode_Continuous_c) or (r.ModeReg = RecMode_ManuelMode_c) then -- reset on mode change!
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if (r.ModeReg /= Mode_Sync) or (r.ModeReg = RecMode_Continuous_c) or (r.ModeReg = RecMode_ManuelMode_c) then -- reset on mode change!
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v.IsArmed := '0';
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elsif r.ArmReg = '1' then
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v.IsArmed := '1';
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@ -295,7 +301,7 @@ begin
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end if;
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when others => null;
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end case;
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if r.ModeReg /= Mode then
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if r.ModeReg /= Mode_Sync then
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v.RecEna := '0';
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end if;
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@ -330,9 +336,9 @@ begin
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--------------------------------------------
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-- Output Side TLAST handling
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--------------------------------------------
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p_outlast : process(Clk)
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p_outlast : process(ClkSmem)
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begin
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if rising_edge(Clk) then
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if rising_edge(ClkSmem) then
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-- Default Value
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Daq_HasLast_I <= '0';
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@ -347,7 +353,7 @@ begin
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end if;
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-- Reset
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if Rst = '1' then
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if RstSmem = '1' then
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OutTlastCnt <= (others => '0');
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end if;
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end if;
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@ -357,41 +363,88 @@ begin
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--------------------------------------------
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-- Component Instantiation
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--------------------------------------------
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-- Clock crossing for reset and TLAST counter
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-- Only the reset from Tosca is used since resetting the FIFO during a burst could lead to deadlocks.
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StatusCcIn(TlastCntWidth_c-1 downto 0) <= r.TLastCnt;
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StatusCcIn(TlastCntWidth_c) <= r.IsArmed;
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StatusCcIn(TlastCntWidth_c+1) <= r.RecEna;
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i_cc : entity work.psi_common_status_cc
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-- *** TMEM clock crossings ***
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i_cc_tmem_status : entity work.psi_common_status_cc
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generic map (
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DataWidth_g => TlastCntWidth_c+2
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DataWidth_g => 34
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)
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port map (
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ClkA => Str_Clk,
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RstInA => '0',
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RstOutA => Str_Rst,
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DataA => StatusCcIn,
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ClkB => Clk,
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RstInB => Rst,
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DataB => StatusCcOut
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ClkA => ClkTmem,
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RstInA => '0',
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DataA(31 downto 0) => PostTrigSpls,
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DataA(33 downto 32) => Mode,
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ClkB => Str_Clk,
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RstInB => Str_Rst,
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DataB(31 downto 0) => PostTrigSpls_Sync,
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DataB(33 downto 32) => Mode_Sync
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);
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InTlastCnt <= StatusCcOut(TlastCntWidth_c-1 downto 0);
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IsArmed <= StatusCcOut(TlastCntWidth_c);
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IsRecording <= StatusCcOut(TlastCntWidth_c+1);
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-- Clock crossing for ARM pulse
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i_cc_arm : entity work.psi_common_pulse_cc
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i_cc_status : entity work.psi_common_bit_cc
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generic map (
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NumBits_g => 2
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)
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port map (
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BitsA(0) => r.IsArmed,
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BitsA(1) => r.RecEna,
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ClkB => ClkTmem,
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BitsB(0) => IsArmed,
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BitsB(1) => IsRecording
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);
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i_cc_tmem_pulse : entity work.psi_common_pulse_cc
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generic map (
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NumPulses_g => 1
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)
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port map (
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ClkA => Clk,
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RstInA => Rst,
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ClkA => ClkTmem,
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RstInA => '0',
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PulseA(0) => Arm,
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ClkB => Str_Clk,
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RstInB => Str_Rst,
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PulseB(0) => Str_Arm
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RstOutB => open,
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PulseB(0) => Arm_Sync
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);
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-- *** Reset Handling ***
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icc_tmem_rst : entity work.psi_common_bit_cc
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generic map (
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NumBits_g => 1
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)
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port map (
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BitsA(0) => RstTmem,
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ClkB => Str_Clk,
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BitsB(0) => RstTmem_Sync
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);
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icc_smem_rst : entity work.psi_common_bit_cc
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generic map (
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NumBits_g => 1
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)
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port map (
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BitsA(0) => RstSmem,
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ClkB => Str_Clk,
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BitsB(0) => RstAcq_Sync
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);
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Str_Rst <= RstTmem_Sync or RstAcq_Sync;
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-- *** Acquisition Clock Crossing ***
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-- Clock crossing for reset and TLAST counter
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i_cc : entity work.psi_common_status_cc
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generic map (
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DataWidth_g => TlastCntWidth_c
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)
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port map (
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ClkA => Str_Clk,
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RstInA => Str_Rst,
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RstOutA => open,
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DataA => r.TLastCnt,
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ClkB => ClkSmem,
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RstInB => '0',
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DataB => InTlastCnt
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);
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-- Data FIFO
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DataFifo_InData(63 downto 0) <= r.DataSftReg;
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@ -409,9 +462,9 @@ begin
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)
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port map (
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InClk => Str_Clk,
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InRst => '0',
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OutClk => Clk,
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OutRst => Rst,
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InRst => Str_Rst,
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OutClk => ClkSmem,
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OutRst => '0',
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InData => DataFifo_InData,
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InVld => r.DataFifoVld,
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InRdy => DataFifo_InRdy,
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@ -447,9 +500,9 @@ begin
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)
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port map (
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InClk => Str_Clk,
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InRst => '0',
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OutClk => Clk,
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OutRst => Rst,
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InRst => Str_Rst,
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OutClk => ClkSmem,
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OutRst => '0',
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InData => r.TsLatch,
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InVld => TsFifo_InVld,
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InRdy => TsFifo_InRdy,
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@ -473,9 +526,9 @@ begin
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--------------------------------------------
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-- Assertions
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--------------------------------------------
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p_assert : process(Clk)
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p_assert : process(ClkSmem)
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begin
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if rising_edge(Clk) then
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if rising_edge(ClkSmem) then
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assert StreamWidth_g = 8 or StreamWidth_g = 16 or StreamWidth_g = 32 or StreamWidth_g = 64 report "###ERROR###: psi_ms_daq_input: StreamWidth_g must be 8, 16, 32 or 64" severity error;
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end if;
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end process;
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@ -20,31 +20,35 @@ entity psi_ms_daq_reg_tmem is
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MaxWindows_g : in integer range 1 to 32
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);
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port (
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-- control Ports
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ToscaClk : in std_logic;
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Rst : in std_logic;
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-- TMEM Interface
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ClkTmem : in std_logic;
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RstTmem : in std_logic;
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TmemRqst : in TmemRqst_t;
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TmemResp : out TmemResp_t;
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-- Context Memory Interface
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-- Control Signals (TMEM Clk)
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Arm : out std_logic_vector(Streams_g-1 downto 0);
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IsArmed : in std_logic_vector(Streams_g-1 downto 0);
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IsRecording : in std_logic_vector(Streams_g-1 downto 0);
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PostTrig : out t_aslv32(Streams_g-1 downto 0);
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RecMode : out t_aslv2(Streams_g-1 downto 0);
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IrqOut : out std_logic;
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-- SMEM Clock domain control singals
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ClkSmem : in std_logic;
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RstSmem : in std_logic;
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-- Context Memory Interface (SMEM Clk)
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CtxStr_Cmd : in ToCtxStr_t;
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CtxStr_Resp : out FromCtx_t;
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CtxWin_Cmd : in ToCtxWin_t;
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CtxWin_Resp : out FromCtx_t;
|
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|
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-- Logic Interface
|
||||
|
||||
-- Logic Interface (SMEM Clk)
|
||||
StrIrq : in std_logic_vector(Streams_g-1 downto 0);
|
||||
StrEna : out std_logic_vector(Streams_g-1 downto 0);
|
||||
GlbEna : out std_logic;
|
||||
IrqOut : out std_logic;
|
||||
InLevel : in t_aslv16(Streams_g-1 downto 0);
|
||||
PostTrig : out t_aslv32(Streams_g-1 downto 0);
|
||||
Arm : out std_logic_vector(Streams_g-1 downto 0);
|
||||
IsArmed : in std_logic_vector(Streams_g-1 downto 0);
|
||||
IsRecording : in std_logic_vector(Streams_g-1 downto 0);
|
||||
RecMode : out t_aslv2(Streams_g-1 downto 0)
|
||||
StrEna : out std_logic_vector(Streams_g-1 downto 0);
|
||||
GlbEna : out std_logic;
|
||||
InLevel : in t_aslv16(Streams_g-1 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
@ -55,8 +59,7 @@ architecture rtl of psi_ms_daq_reg_tmem is
|
||||
Reg_Gcfg_IrqEna : std_logic;
|
||||
Reg_IrqVec : std_logic_vector(Streams_g-1 downto 0);
|
||||
Reg_IrqEna : std_logic_vector(Streams_g-1 downto 0);
|
||||
Reg_StrEna : std_logic_vector(Streams_g-1 downto 0);
|
||||
Reg_MaxLvl : t_aslv16(Streams_g-1 downto 0);
|
||||
Reg_StrEna : std_logic_vector(Streams_g-1 downto 0);
|
||||
Reg_PostTrig : t_aslv32(Streams_g-1 downto 0);
|
||||
Reg_Mode_Recm : t_aslv2(Streams_g-1 downto 0);
|
||||
Reg_Mode_Arm : std_logic_vector(Streams_g-1 downto 0);
|
||||
@ -64,6 +67,7 @@ architecture rtl of psi_ms_daq_reg_tmem is
|
||||
RegRdval : std_logic_vector(63 downto 0);
|
||||
RdVal : std_logic_vector(63 downto 0);
|
||||
AddrReg : std_logic_vector(23 downto 0);
|
||||
MaxLvlClr : std_logic_vector(Streams_g-1 downto 0);
|
||||
end record;
|
||||
signal r, r_next : two_process_r;
|
||||
|
||||
@ -86,25 +90,25 @@ architecture rtl of psi_ms_daq_reg_tmem is
|
||||
signal CtxWin_Rdval : std_logic_vector(63 downto 0);
|
||||
signal CtxWin_AddrB : std_logic_vector(log2ceil(DepthCtxWin_c)-1 downto 0);
|
||||
signal AddrCtxWin : boolean;
|
||||
|
||||
-- Maximum Level Latching
|
||||
signal MaxLevel : t_aslv16(Streams_g-1 downto 0);
|
||||
|
||||
-- Clock Crossing Signals
|
||||
signal StrIrq_Sync : std_logic_vector(Streams_g-1 downto 0);
|
||||
signal MaxLevel_Sync : t_aslv16(Streams_g-1 downto 0);
|
||||
signal MaxLevelClr_Sync : std_logic_vector(Streams_g-1 downto 0);
|
||||
begin
|
||||
--------------------------------------------
|
||||
-- Combinatorial Process
|
||||
--------------------------------------------
|
||||
p_comb : process( r, TmemRqst, StrIrq, InLevel, IsArmed, IsRecording, CtxStr_Rdval, CtxWin_Rdval)
|
||||
p_comb : process( r, TmemRqst, StrIrq_Sync, IsArmed, IsRecording, CtxStr_Rdval, CtxWin_Rdval, MaxLevel)
|
||||
variable v : two_process_r;
|
||||
variable Stream_v : integer range 0 to Streams_g-1;
|
||||
begin
|
||||
-- *** Hold variables stable ***
|
||||
v := r;
|
||||
|
||||
-- *** Update Maximum Level
|
||||
for i in 0 to Streams_g-1 loop
|
||||
if unsigned(InLevel(i)) > unsigned(r.Reg_MaxLvl(i)) then
|
||||
v.Reg_MaxLvl(i) := InLevel(i);
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
|
||||
-- *** General Register Accesses ***
|
||||
v.RegRdval := (others => '0');
|
||||
if TmemRqst.ENA = '1' then
|
||||
@ -150,6 +154,7 @@ begin
|
||||
|
||||
-- *** Stream Register Accesses ***
|
||||
v.Reg_Mode_Arm := (others => '0');
|
||||
v.MaxLvlClr := (others => '0');
|
||||
if TmemRqst.ENA = '1' then
|
||||
if TmemRqst.ADD(23 downto 9) = X"000" & "001" then
|
||||
Stream_v := to_integer(unsigned(TmemRqst.ADD(8 downto 4)));
|
||||
@ -158,9 +163,9 @@ begin
|
||||
if TmemRqst.ADD(3 downto 0) = X"0" then
|
||||
-- MAXLVLn
|
||||
if TmemRqst.WE(WeLow_c) = DwWrite_c then
|
||||
v.Reg_MaxLvl(Stream_v) := (others => '0');
|
||||
v.MaxLvlClr(Stream_v) := '1';
|
||||
end if;
|
||||
v.RegRdval(15 downto 0) := r.Reg_MaxLvl(Stream_v);
|
||||
v.RegRdval(15 downto 0) := MaxLevel(Stream_v);
|
||||
-- POSTTRIGn
|
||||
if TmemRqst.WE(WeHigh_c) = DwWrite_c then
|
||||
v.Reg_PostTrig(Stream_v) := TmemRqst.DATW(63 downto 32);
|
||||
@ -198,7 +203,7 @@ begin
|
||||
|
||||
-- *** IRQ Handling ***
|
||||
for i in 0 to Streams_g-1 loop
|
||||
if (StrIrq(i) = '1') and (r.Reg_StrEna(i) = '1') then
|
||||
if (StrIrq_Sync(i) = '1') and (r.Reg_StrEna(i) = '1') then
|
||||
v.Reg_IrqVec(i) := '1';
|
||||
end if;
|
||||
end loop;
|
||||
@ -220,8 +225,6 @@ begin
|
||||
TmemResp.BUSY <= '0';
|
||||
TmemResp.DATR <= r.RdVal;
|
||||
IrqOut <= r.Irq;
|
||||
StrEna <= r.Reg_StrEna;
|
||||
GlbEna <= r.Reg_Gcfg_Ena;
|
||||
PostTrig <= r.Reg_PostTrig;
|
||||
Arm <= r.Reg_Mode_Arm;
|
||||
RecMode <= r.Reg_Mode_Recm;
|
||||
@ -229,29 +232,100 @@ begin
|
||||
--------------------------------------------
|
||||
-- Sequential Process
|
||||
--------------------------------------------
|
||||
p_seq : process(ToscaClk)
|
||||
p_seq : process(ClkTmem)
|
||||
begin
|
||||
if rising_edge(ToscaClk) then
|
||||
if rising_edge(ClkTmem) then
|
||||
r <= r_next;
|
||||
if Rst = '1' then
|
||||
if RstTmem = '1' then
|
||||
r.Reg_Gcfg_Ena <= '0';
|
||||
r.Reg_Gcfg_IrqEna <= '0';
|
||||
r.Reg_IrqVec <= (others => '0');
|
||||
r.Reg_IrqEna <= (others => '0');
|
||||
r.Reg_StrEna <= (others => '0');
|
||||
r.Irq <= '0';
|
||||
r.Reg_MaxLvl <= (others => (others => '0'));
|
||||
r.Reg_PostTrig <= (others => (others => '0'));
|
||||
r.Reg_Mode_Recm <= (others => (others => '0'));
|
||||
r.Reg_Mode_Arm <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------
|
||||
-- Maximum Level Latching (SmemClk)
|
||||
--------------------------------------------
|
||||
p_maxlvl : process(ClkSmem)
|
||||
begin
|
||||
if rising_edge(ClkSmem) then
|
||||
if RstSmem = '1' then
|
||||
MaxLevel <= (others => (others => '0'));
|
||||
else
|
||||
-- Latch maximum level
|
||||
for i in 0 to Streams_g-1 loop
|
||||
if MaxLevelClr_Sync(i) = '1' then
|
||||
MaxLevel(i) <= (others => '0');
|
||||
elsif unsigned(InLevel(i)) > unsigned(MaxLevel(i)) then
|
||||
MaxLevel(i) <= InLevel(i);
|
||||
end if;
|
||||
end loop;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------
|
||||
-- Component Instantiations
|
||||
--------------------------------------------
|
||||
|
||||
-- *** Clock Crossings ***
|
||||
i_cc_smem_in : entity work.psi_common_pulse_cc
|
||||
generic map (
|
||||
NumPulses_g => Streams_g
|
||||
)
|
||||
port map (
|
||||
ClkA => ClkSmem,
|
||||
RstInA => RstSmem,
|
||||
PulseA => StrIrq,
|
||||
ClkB => ClkTmem,
|
||||
RstInB => RstTmem,
|
||||
PulseB => StrIrq_Sync
|
||||
);
|
||||
|
||||
blk_cc_smem_out : block
|
||||
signal ccIn, ccOut : std_logic_vector(Streams_g downto 0);
|
||||
begin
|
||||
-- Input Assembly
|
||||
ccIn(Streams_g-1 downto 0) <= r.Reg_StrEna;
|
||||
ccIn(Streams_g) <= r.Reg_Gcfg_Ena;
|
||||
|
||||
-- Instantiation
|
||||
i_cc_smem_out : entity work.psi_common_bit_cc
|
||||
generic map (
|
||||
NumBits_g => Streams_g+1
|
||||
)
|
||||
port map (
|
||||
BitsA => ccIn,
|
||||
ClkB => ClkSmem,
|
||||
BitsB => ccOut
|
||||
);
|
||||
|
||||
-- Output assembly
|
||||
StrEna <= ccOut(Streams_g-1 downto 0);
|
||||
GlbEna <= ccOut(Streams_g);
|
||||
end block;
|
||||
|
||||
i_cc_smem_out_pulse : entity work.psi_common_pulse_cc
|
||||
generic map (
|
||||
NumPulses_g => Streams_g
|
||||
)
|
||||
port map (
|
||||
ClkA => ClkTmem,
|
||||
RstInA => RstTmem,
|
||||
PulseA => r.MaxLvlClr,
|
||||
ClkB => ClkSmem,
|
||||
RstInB => RstSmem,
|
||||
PulseB => MaxLevelClr_Sync
|
||||
);
|
||||
|
||||
|
||||
-- *** Stream Context Memory ***
|
||||
-- Signal Assembly
|
||||
AddrCtxStr <= TmemRqst.ADD(23 downto 12) = X"001";
|
||||
@ -266,12 +340,12 @@ begin
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 3),
|
||||
WrA => CtxStr_WeLo,
|
||||
DinA => TmemRqst.DATW(31 downto 0),
|
||||
DoutA => CtxStr_Rdval(31 downto 0),
|
||||
ClkB => ToscaClk,
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxStr_AddrB,
|
||||
WrB => CtxStr_Cmd.WenLo,
|
||||
DinB => CtxStr_Cmd.WdatLo,
|
||||
@ -285,12 +359,12 @@ begin
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxStrAddrHigh_c downto 3),
|
||||
WrA => CtxStr_WeHi,
|
||||
DinA => TmemRqst.DATW(63 downto 32),
|
||||
DoutA => CtxStr_Rdval(63 downto 32),
|
||||
ClkB => ToscaClk,
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxStr_AddrB,
|
||||
WrB => CtxStr_Cmd.WenHi,
|
||||
DinB => CtxStr_Cmd.WdatHi,
|
||||
@ -313,12 +387,12 @@ begin
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 3),
|
||||
WrA => CtxWin_WeLo,
|
||||
DinA => TmemRqst.DATW(31 downto 0),
|
||||
DoutA => CtxWin_Rdval(31 downto 0),
|
||||
ClkB => ToscaClk,
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxWin_AddrB,
|
||||
WrB => CtxWin_Cmd.WenLo,
|
||||
DinB => CtxWin_Cmd.WdatLo,
|
||||
@ -332,12 +406,12 @@ begin
|
||||
Width_g => 32
|
||||
)
|
||||
port map (
|
||||
ClkA => ToscaClk,
|
||||
ClkA => ClkTmem,
|
||||
AddrA => TmemRqst.ADD(CtxWinAddrHigh_c downto 3),
|
||||
WrA => CtxWin_WeHi,
|
||||
DinA => TmemRqst.DATW(63 downto 32),
|
||||
DoutA => CtxWin_Rdval(63 downto 32),
|
||||
ClkB => ToscaClk,
|
||||
ClkB => ClkSmem,
|
||||
AddrB => CtxWin_AddrB,
|
||||
WrB => CtxWin_Cmd.WenHi,
|
||||
DinB => CtxWin_Cmd.WdatHi,
|
||||
|
||||
@ -21,6 +21,7 @@ add_sources $LibPath {
|
||||
psi_common/hdl/psi_common_logic_pkg.vhd \
|
||||
psi_common/hdl/psi_common_sdp_ram_rbw.vhd \
|
||||
psi_common/hdl/psi_common_pulse_cc.vhd \
|
||||
psi_common/hdl/psi_common_bit_cc.vhd \
|
||||
psi_common/hdl/psi_common_simple_cc.vhd \
|
||||
psi_common/hdl/psi_common_status_cc.vhd \
|
||||
psi_common/hdl/psi_common_async_fifo.vhd \
|
||||
|
||||
@ -56,7 +56,8 @@ architecture sim of psi_ms_daq_tb is
|
||||
signal Str_Vld : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Str_Rdy : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Str_Trig : std_logic_vector(StrCount_c-1 downto 0) := (others => '0');
|
||||
signal Tosca_Clk : std_logic := '0';
|
||||
signal Tmem_Clk : std_logic := '0';
|
||||
signal Smem_Clk : std_logic := '0';
|
||||
signal Tmem_Rst : std_logic := '1';
|
||||
signal Smem_Rst : std_logic := '1';
|
||||
signal TmemAcq : TmemRqst_t := TmemRqst_init_c;
|
||||
@ -88,7 +89,10 @@ architecture sim of psi_ms_daq_tb is
|
||||
end case;
|
||||
end if;
|
||||
end loop;
|
||||
wait until rising_edge(clk);
|
||||
-- Delay to ensure IRQ is cleared
|
||||
for i in 0 to 5 loop
|
||||
wait until rising_edge(clk);
|
||||
end loop;
|
||||
end procedure;
|
||||
|
||||
|
||||
@ -124,8 +128,9 @@ begin
|
||||
Str_Vld => Str_Vld,
|
||||
Str_Rdy => Str_Rdy,
|
||||
Str_Trig => Str_Trig,
|
||||
Tosca_Clk => Tosca_Clk,
|
||||
Tmem_Clk => Tmem_Clk,
|
||||
Tmem_Rst => Tmem_Rst,
|
||||
Smem_Clk => Smem_Clk,
|
||||
Smem_Rst => Smem_Rst,
|
||||
TmemAcq => TmemAcq,
|
||||
AcqTmem => AcqTmem,
|
||||
@ -142,22 +147,22 @@ begin
|
||||
variable Size_v : integer;
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait until (rising_edge(Tosca_Clk) and AcqSmem.WREQ = SMEM_REQ_Request_c) or (not TbRunning);
|
||||
wait until (rising_edge(Smem_Clk) and AcqSmem.WREQ = SMEM_REQ_Request_c) or (not TbRunning);
|
||||
if TbRunning then
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
Address_v := to_integer(unsigned(AcqSmem.WADD));
|
||||
Size_v := to_integer(unsigned(AcqSmem.WSIZ));
|
||||
SmemAcq.WACK <= SMEM_ACK_Grant_c;
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
SmemAcq.WACK <= SMEM_ACK_Burst_c;
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
for qw in 0 to Size_v-1 loop
|
||||
if qw = Size_v-1 then
|
||||
SmemAcq.WACK <= SMEM_ACK_Done_c;
|
||||
end if;
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
for byte in 0 to 7 loop
|
||||
if AcqSmem.WBE(byte) = '1' then
|
||||
Memory(Address_v+qw*8+byte) <= AcqSmem.WDAT(byte*8+7 downto byte*8);
|
||||
@ -165,7 +170,7 @@ begin
|
||||
end loop;
|
||||
end loop;
|
||||
SmemAcq.WACK <= SMEM_ACK_Idle_c;
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Smem_Clk);
|
||||
end if;
|
||||
end loop;
|
||||
wait;
|
||||
@ -175,16 +180,26 @@ begin
|
||||
-- Clocks
|
||||
------------------------------------------------------------
|
||||
|
||||
p_clk_tosca : process
|
||||
p_clk_smem : process
|
||||
constant Frequency_c : real := real(200e6);
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/Frequency_c;
|
||||
Tosca_Clk <= not Tosca_Clk;
|
||||
Smem_Clk <= not Smem_Clk;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_clk_tmem : process
|
||||
constant Frequency_c : real := real(166e6);
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/Frequency_c;
|
||||
Tmem_Clk <= not Tmem_Clk;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
g_clk_str : for i in 0 to StrCount_c-1 generate
|
||||
p_clk_str : process
|
||||
begin
|
||||
@ -213,32 +228,32 @@ begin
|
||||
Smem_Rst <= '0';
|
||||
|
||||
-- *** Initial Configuration ***
|
||||
TmemExpect32(16#0010#, 0, Tosca_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0014#, 16#000F#, Tosca_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0020#, 16#000F#, Tosca_Clk, TmemAcq, AcqTmem);
|
||||
TmemExpect32(16#0010#, 0, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0014#, 16#000F#, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0020#, 16#000F#, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
-- Stream Setup
|
||||
Str0Setup(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str1Setup(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str2Setup(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str3Setup(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str0Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str1Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str2Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str3Setup(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
|
||||
-- Enable
|
||||
TmemWriteAndRead32(16#0000#, 16#0101#, Tosca_Clk, TmemAcq, AcqTmem);
|
||||
TmemWriteAndRead32(16#0000#, 16#0101#, Tmem_Clk, TmemAcq, AcqTmem);
|
||||
|
||||
|
||||
-- *** Run Test ***
|
||||
StartTime_v := now;
|
||||
while now < StartTime_v+100 us loop
|
||||
wait until rising_edge(Tosca_Clk);
|
||||
wait until rising_edge(Tmem_Clk);
|
||||
-- IRQ Handling
|
||||
if Irq = '1' then
|
||||
IrqHandler(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
IrqHandler(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
end if;
|
||||
-- Regular actions
|
||||
Str0Update(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str1Update(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str2Update(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str3Update(Tosca_Clk, TmemAcq, AcqTmem);
|
||||
Str0Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str1Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str2Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
Str3Update(Tmem_Clk, TmemAcq, AcqTmem);
|
||||
|
||||
end loop;
|
||||
TbRunning <= false;
|
||||
|
||||
@ -123,6 +123,8 @@ package body psi_ms_daq_tb_str0_pkg is
|
||||
variable winlast : integer;
|
||||
variable addr : integer;
|
||||
variable tslo : integer;
|
||||
variable firstLoop : boolean := true;
|
||||
variable HasTrigger : boolean;
|
||||
begin
|
||||
print("------------ Stream 0 Handler ------------", PrintStr0_c);
|
||||
HlGetMaxLvl(0, clk, rqst, rsp, v);
|
||||
@ -134,7 +136,10 @@ package body psi_ms_daq_tb_str0_pkg is
|
||||
print("Skipped, stream disabled", PrintStr0_c);
|
||||
print("", PrintStr0_c);
|
||||
else
|
||||
while Str0NextWin /= curwin loop
|
||||
HlIsTrigWin(0, Str0NextWin, clk, rqst, rsp, HasTrigger);
|
||||
-- curwin = nextwin can occur if al lwindows are filled. In all cases we only interpret windows containing triggers.
|
||||
while ((Str0NextWin /= curwin) or firstLoop) and HasTrigger loop
|
||||
firstLoop := false;
|
||||
print("*** Window " & to_string(Str0NextWin) & " / Number: " & to_string(Str0WinCheck) & " ***", PrintStr0_c);
|
||||
HlGetWinCnt(0, Str0NextWin, clk, rqst, rsp, wincnt);
|
||||
print("WINCNT: " & to_string(wincnt), PrintStr0_c);
|
||||
|
||||
@ -73,8 +73,10 @@ architecture sim of psi_ms_daq_input_tb is
|
||||
signal Str_Data : std_logic_vector(StreamWidth_g-1 downto 0) := (others => '0');
|
||||
signal Str_Trig : std_logic := '0';
|
||||
signal Str_Ts : std_logic_vector(63 downto 0) := (others => '0');
|
||||
signal Clk : std_logic := '1';
|
||||
signal Rst : std_logic := '1';
|
||||
signal ClkTmem : std_logic := '1';
|
||||
signal RstTmem : std_logic := '1';
|
||||
signal ClkSmem : std_logic := '1';
|
||||
signal RstSmem : std_logic := '1';
|
||||
signal PostTrigSpls : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal Mode : RecMode_t := (others => '0');
|
||||
signal Arm : std_logic := '0';
|
||||
@ -108,12 +110,14 @@ begin
|
||||
Str_Data => Str_Data,
|
||||
Str_Trig => Str_Trig,
|
||||
Str_Ts => Str_Ts,
|
||||
Clk => Clk,
|
||||
Rst => Rst,
|
||||
ClkTmem => ClkTmem,
|
||||
RstTmem => RstTmem,
|
||||
PostTrigSpls => PostTrigSpls,
|
||||
Mode => Mode,
|
||||
Arm => Arm,
|
||||
IsArmed => IsArmed,
|
||||
ClkSmem => ClkSmem,
|
||||
RstSmem => RstSmem,
|
||||
Daq_Vld => Daq_Vld,
|
||||
Daq_Rdy => Daq_Rdy,
|
||||
Daq_Data => Daq_Data,
|
||||
@ -129,7 +133,7 @@ begin
|
||||
------------------------------------------------------------
|
||||
p_tb_control : process
|
||||
begin
|
||||
wait until Rst = '0';
|
||||
wait until RstTmem = '0' and RstSmem = '0';
|
||||
-- single_frame
|
||||
NextCase <= 0;
|
||||
wait until ProcessDone = AllProcessesDone_c;
|
||||
@ -171,16 +175,26 @@ begin
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_clock_Clk : process
|
||||
p_clock_ClkSmem : process
|
||||
constant Frequency_c : real := real(200e6);
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/Frequency_c;
|
||||
Clk <= not Clk;
|
||||
ClkSmem <= not ClkSmem;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
p_clock_ClkTmem : process
|
||||
constant Frequency_c : real := real(166e6);
|
||||
begin
|
||||
while TbRunning loop
|
||||
wait for 0.5*(1 sec)/Frequency_c;
|
||||
ClkTmem <= not ClkTmem;
|
||||
end loop;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
|
||||
------------------------------------------------------------
|
||||
-- Resets
|
||||
@ -189,9 +203,12 @@ begin
|
||||
begin
|
||||
wait for 1 us;
|
||||
-- Wait for two clk edges to ensure reset is active for at least one edge
|
||||
wait until rising_edge(Clk);
|
||||
wait until rising_edge(Clk);
|
||||
Rst <= '0';
|
||||
wait until rising_edge(ClkSmem);
|
||||
wait until rising_edge(ClkSmem);
|
||||
RstSmem <= '0';
|
||||
wait until rising_edge(ClkTmem);
|
||||
wait until rising_edge(ClkTmem);
|
||||
RstTmem <= '0';
|
||||
wait;
|
||||
end process;
|
||||
|
||||
@ -205,49 +222,49 @@ begin
|
||||
-- single_frame
|
||||
wait until NextCase = 0;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_single_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_single_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- multi_frame
|
||||
wait until NextCase = 1;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_multi_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_multi_frame.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- timeout
|
||||
wait until NextCase = 2;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_timeout.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_timeout.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- ts_overflow
|
||||
wait until NextCase = 3;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_ts_overflow.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_ts_overflow.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- trig_in_posttrig
|
||||
wait until NextCase = 4;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_trig_in_posttrig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_trig_in_posttrig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- always_trig
|
||||
wait until NextCase = 5;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_always_trig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_always_trig.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- backpressure
|
||||
wait until NextCase = 6;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_backpressure.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_backpressure.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
-- modes
|
||||
wait until NextCase = 7;
|
||||
ProcessDone(TbProcNr_stream_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_modes.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, Clk, Arm, IsArmed, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_modes.stream(Str_Clk, Str_Vld, Str_Rdy, Str_Data, Str_Trig, Str_Ts, ClkTmem, Arm, IsArmed, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_stream_c) <= '1';
|
||||
wait;
|
||||
@ -259,49 +276,49 @@ begin
|
||||
-- single_frame
|
||||
wait until NextCase = 0;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_single_frame.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_single_frame.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- multi_frame
|
||||
wait until NextCase = 1;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_multi_frame.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_multi_frame.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- timeout
|
||||
wait until NextCase = 2;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_timeout.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_timeout.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- ts_overflow
|
||||
wait until NextCase = 3;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_ts_overflow.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_ts_overflow.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- trig_in_posttrig
|
||||
wait until NextCase = 4;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_trig_in_posttrig.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_trig_in_posttrig.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- always_trig
|
||||
wait until NextCase = 5;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_always_trig.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_always_trig.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- backpressure
|
||||
wait until NextCase = 6;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_backpressure.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_backpressure.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
-- modes
|
||||
wait until NextCase = 7;
|
||||
ProcessDone(TbProcNr_daq_c) <= '0';
|
||||
work.psi_ms_daq_input_tb_case_modes.daq(Clk, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
work.psi_ms_daq_input_tb_case_modes.daq(ClkSmem, PostTrigSpls, Mode, Daq_Vld, Daq_Rdy, Daq_Data, Daq_Level, Daq_HasLast, Ts_Vld, Ts_Rdy, Ts_Data, Generics_c);
|
||||
wait for 1 ps;
|
||||
ProcessDone(TbProcNr_daq_c) <= '1';
|
||||
wait;
|
||||
|
||||
Reference in New Issue
Block a user