DEVEL: Replaced round-robing arbiters by priority arbitters (less logic)

hdl/psi_ms_daq_daq_sm.vhd

@@ -137,7 +137,6 @@ architecture rtl of psi_ms_daq_daq_sm is
 		NewBuffer		: std_logic_vector(Streams_g-1 downto 0);
 		FirstAfterEna	: std_logic_vector(Streams_g-1 downto 0);
 		FirstOngoing	: std_logic_vector(Streams_g-1 downto 0);
-		GrantRdy		: std_logic_vector(3 downto 1);
 		GrantVldReg		: std_logic_vector(3 downto 1);
 		State			: State_t;
 		GrantPrio1Reg	: std_logic_vector(GrantPrio1'range);
@@ -191,7 +190,6 @@ begin
 		v := r;
 		
 		-- *** Default Values ***
-		v.GrantRdy			:= (others => '0');
 		v.CtxStr_Cmd.WenLo	:= '0';
 		v.CtxStr_Cmd.WenHi	:= '0';
 		v.CtxWin_Cmd.WenLo	:= '0';
@@ -242,15 +240,13 @@ begin
 				v.HndlWinDone	:= '0';
 				-- check if data to write is available	(only if IRQ FIFO has space for the response for sure)
 				if IrqFifoAlmFull = '0' then				
-					v.State 		:= CheckPrio1_s;
-					v.GrantRdy(1)	:= '1';					
+					v.State 		:= CheckPrio1_s;			
 					v.HndlAfterCtxt	:= CalcAccess0_s;
 				end if;
 				-- Delay arbitration in simulation to allow TB to react
 				if Simulation_g then
 					if r.SimDelCnt /= 4 then
 						v.State 		:= Idle_s;
-						v.GrantRdy(1)	:= '0';
 						v.SimDelCnt		:= r.SimDelCnt + 1;
 					else
 						v.SimDelCnt		:= 0;
@@ -269,7 +265,6 @@ begin
 				-- Otherwise check lower priority streams
 				else
 					v.State			:= CheckPrio2_s;
-					v.GrantRdy(2)	:= '1';
 				end if;
 				
 			when CheckPrio2_s =>
@@ -283,7 +278,6 @@ begin
 				-- Otherwise check lower priority streams
 				else
 					v.State			:= CheckPrio3_s;
-					v.GrantRdy(3)	:= '1';
 				end if;	
 
 			when CheckPrio3_s =>
@@ -584,7 +578,6 @@ begin
 				end if;
 				r.InpDataAvail		<= (others => '0');
 				r.DataAvailArbIn	<= (others => '0');
-				r.GrantRdy			<= (others => '0');
 				r.HndlStream		<= 0;
 				r.State				<= Idle_s;
 				r.CtxStr_Cmd.WenLo	<= '0';
@@ -612,7 +605,7 @@ begin
 	--------------------------------------------
 	-- *** Round Robin Arbiter - Prio 1 ***
 	AvailPrio1 <= GetBitsOfStreamPrio(r.DataAvailArbIn, 1);
-	i_rrarb_1 : entity work.psi_common_arb_round_robin
+	i_rrarb_1 : entity work.psi_common_arb_priority
 		generic map (
 			Size_g			=> count(StreamPrio_g, 1)
 		)
@@ -620,14 +613,13 @@ begin
 			Clk				=> Clk,
 			Rst				=> Rst,
 			Request			=> AvailPrio1,
-			Grant			=> GrantPrio1,
-			Grant_Rdy		=> r.GrantRdy(1),
-			Grant_Vld		=> GrantVld(1)
+			Grant			=> GrantPrio1
 		);	
+		GrantVld(1) <= '1' when unsigned(GrantPrio1) /= 0 else '0';
 		
 	-- *** Round Robin Arbiter - Prio 2 ***
 	AvailPrio2 <= GetBitsOfStreamPrio(r.DataAvailArbIn, 2);
-	i_rrarb_2 : entity work.psi_common_arb_round_robin
+	i_rrarb_2 : entity work.psi_common_arb_priority
 		generic map (
 			Size_g			=> count(StreamPrio_g, 2)
 		)
@@ -635,14 +627,13 @@ begin
 			Clk				=> Clk,
 			Rst				=> Rst,
 			Request			=> AvailPrio2,
-			Grant			=> GrantPrio2,
-			Grant_Rdy		=> r.GrantRdy(2),
-			Grant_Vld		=> GrantVld(2)
+			Grant			=> GrantPrio2
 		);
+		GrantVld(2) <= '1' when unsigned(GrantPrio2) /= 0 else '0';
 
 	-- *** Round Robin Arbiter - Prio 3 ***
 	AvailPrio3 <= GetBitsOfStreamPrio(r.DataAvailArbIn, 3);
-	i_rrarb_3 : entity work.psi_common_arb_round_robin
+	i_rrarb_3 : entity work.psi_common_arb_priority
 		generic map (
 			Size_g			=> count(StreamPrio_g, 3)
 		)
@@ -650,10 +641,9 @@ begin
 			Clk				=> Clk,
 			Rst				=> Rst,
 			Request			=> AvailPrio3,
-			Grant			=> GrantPrio3,
-			Grant_Rdy		=> r.GrantRdy(3),
-			Grant_Vld		=> GrantVld(3)
+			Grant			=> GrantPrio3
 		);	
+	 GrantVld(3) <= '1' when unsigned(GrantPrio3) /= 0 else '0';
 
 
 	-- *** IRQ Information FIFO ***

sim/config.tcl

@@ -24,7 +24,6 @@ add_sources $LibPath {
 	psi_common/hdl/psi_common_status_cc.vhd \
 	psi_common/hdl/psi_common_async_fifo.vhd \
 	psi_common/hdl/psi_common_arb_priority.vhd \
-	psi_common/hdl/psi_common_arb_round_robin.vhd \
 	psi_common/hdl/psi_common_sync_fifo.vhd \
 } -tag lib
 

tb/psi_ms_daq_daq_sm/psi_ms_daq_daq_sm_tb_case_enable.vhd

@@ -89,6 +89,7 @@ package body psi_ms_daq_daq_sm_tb_case_enable is
 		print(">> Disabled stream does not react (global)");
 		InitTestCase(Clk, Rst);
 		GlbEna	<= '0';
+		wait for 100 ns;
 		TestCase := 0;
 		ConfigureAuto(	WinSize => 4096*2, Ringbuf => '0', Overwrite => '1', Wincnt => 2, Wincur => 0);		
 		for i in 0 to 3 loop