7414bcacf6
Updated changelog
2023-09-11 13:05:53 +02:00
4826a093f4
Updated to the newest libraries
2023-09-11 11:28:47 +02:00
5bf9caae3a
Merge branch 'added_robustness' into 'master'
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Add robustness to comma-detection and reset generation.
See merge request GFA/Libraries/Firmware/VHDL/evr320!3
2021-03-16 07:44:43 +01:00
13d42baf14
Merge branch 'fix_issue_#5' into 'master'
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Amendment: removed 'evr_params.cs_timeout_cnt' assignment
See merge request GFA/Libraries/Firmware/VHDL/evr320!2
2021-02-25 09:45:32 +01:00
d135fbddca
Add robustness to comma-detection and reset generation.
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This patch addresses issues I occasionally observed:
a) I have seen occurrences when the GTX deasserts RXBYTEISALIGNED
while the RXLOSSOFSYNC is *not* asserted.
The comma-alignment state machine can be stuck in 'idle' believing
all is well when in fact RXBYTEISALIGNED is deasserted.
The proposed patch monitors RXBYTEISALIGNED in addition to
RXLOSSOFSYNC in 'idle' state.
b) The synchronizer (inst_cdc_fast_stat) which takes the pulse
width/delay to the EVR clock domain relies on a proper
reset sequence for correct operation.
It is possible, however, that the 'evr_clk' (which is generated
from the recovered RX clock) is not ticking at all when 'xuser_RESET'
resets said synchronizer. If e.g., there is no GTX reference clock
present (because it requires i2c initialization which is performed
later) then the EVR clock may not be ticking and prevent the
destination side of the synchronizer from being reset. This
has the consequence of 'width' and 'delay' *never* being
updated.
The proposed patch asserts the synchronizer reset while the RX PLL
and/or MMCM are not locked.
2021-02-24 14:03:16 +01:00
badd801839
Amendment: removed 'evr_params.cs_timeout_cnt' assignment
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This parameter is a local enhancement and not present on the
master branch.
Also: two small changes which address GHDL issues.
2021-02-24 13:46:29 +01:00
df8522473d
Merge branch 'fix_issue_#5' into 'master'
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Fix for issue #5 (wrong endianness of data stream in test bed)
See merge request GFA/Libraries/Firmware/VHDL/evr320!1
2021-02-24 11:47:11 +01:00
50860b9e20
Fix for issue #5 (wrong endianness of data stream in test bed)
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The 'evr320_data_filter' entity presents data in little-endian format.
However, the test is written for big-endian; set the SWAP generic to
fix this.
Also; once this test passes events won't be detected because the checksum
timeout is not reached. Set to zero.
Last: ghdl complains about mem_data(x) indexing when x > C_MEM_DATA_WIDTH.
Replaced hard-coded statements by a simple loop that runs from
0 to C_MEM_DATA_WIDTH/8 - 1.
2021-02-24 11:08:05 +01:00
5bebe6dc41
Doc: Corrected latency counter register 0x38 description
2021-02-03 15:26:50 +01:00
83b6d6562d
FIX: event_decoder ports in tb updated. Added Event Flag check for data width = 64.
2020-12-17 09:33:03 +01:00
34b221f62a
FIX: typo introduced in rebase
2020-12-02 15:04:20 +01:00
26cc7548a3
FIX: default pulse width of user events set to 4
2020-12-02 10:29:58 +01:00
6d3fa8708a
Merge branch 'latfix'
2020-11-18 15:21:13 +01:00
95a88cbba0
FEATURES: Add reset at the output of the ifc1210 wrapper
2020-09-02 08:30:00 +02:00
e6a3441a7a
BUGFIX: added write register to stop latency counter
2020-03-05 07:46:30 +01:00
287bfde2e0
FEATURE: Add SWAP generic to filter and correct TB accordingly
2020-01-31 13:58:41 +01:00
3f1b7acc50
DEVEL: filter modification based on address decoding
2020-01-28 13:15:06 +01:00
fdcadda6ed
FEATURE: evr320 filter input address settable
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DOC: Correct address map for pulse length & delay
2020-01-23 07:27:41 +01:00
0d6457cb77
BIGFIX: For simu initialize delay value to 0
2019-12-13 14:34:37 +01:00
83a4435e41
BUGFIX: std_logic_vector -> std_logic at output of delay (0)
2019-12-12 18:27:50 +01:00
b77484c659
UPDATE: update due to delay modification
2019-12-11 16:28:26 +01:00
071cf50ded
DPDCY: due to change in PSI_COMMON suffix 2 -> cfg in ifc1210 wrapper
2019-12-02 15:12:31 +01:00
5a060a160c
FEATURE: add to TMEM interface regiter width & delay
2019-11-29 15:13:46 +01:00
6b1f4fbcbc
FEATUE: Modify delay & width as registers
2019-11-29 11:48:12 +01:00
ffb3eb6331
FEATURE: add delay/length pulse parameters as generics on ifc1210 wrapper
2019-11-25 16:42:03 +01:00
d5b3545ef2
FEATURE: Add parameters for delay and pulse length on IFC1210 wrapper
2019-11-25 16:38:13 +01:00
2ce1941a6c
added gitignore for modelsim
2019-11-06 10:03:57 +01:00
99e2fe462a
updated doc with latency measurement register description
2019-11-05 13:18:22 +01:00
16e7d3e9f6
added testbench over ifc wrapper for tmem test
2019-11-04 15:47:49 +01:00
60ad0be56e
feature: added register for latency measurement counter since a specific
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event occured
2019-11-04 15:26:04 +01:00
740c93fd7a
BUGFIX: inserted address delay for read data mux
2019-10-24 17:00:10 +02:00
c846a32902
DEVEL: removed usage of lib ieee.std_logic_unsigned
2019-10-21 11:05:34 +02:00
b171096b8a
DEVEL: extended testbench with checks for event recorder
2019-10-18 16:23:28 +02:00
a3ff15adec
FIX: rearrange compile order and set LibPath relative to file location to be able source from application project
2019-10-16 15:18:21 +02:00
bc987bee99
DEVL: decouple user event counting from events in the event stream, peparation to simulate event recorder functionality
2019-10-04 13:15:22 +02:00
4f9e87b16d
readme: add dependencies
2018-12-06 10:46:24 +01:00
82c023c610
change: split streaming port to data and address
2018-12-06 10:00:53 +01:00
84f23d13ab
event event reception check in simulation, fix stimuli
2018-12-05 17:14:04 +01:00
c52673a8ca
simulate stream filter, integrated to if1210 wrapper, syntax fixes
2018-12-05 10:08:52 +01:00
d7e669cb75
extended ifc1210_wrapper with data streaming port and replaced frequency
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measurement by common lib
2018-12-04 21:13:51 +01:00
84440ce6a0
added data filter from decoder stream
2018-12-04 17:02:10 +01:00
5e79f3f426
self checking segment sent/recv comparison
2018-12-04 17:01:38 +01:00
35077a9d84
self checking testbench: read MGT frame from file and compare data
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stream
2018-12-03 17:15:39 +01:00
2634412bd0
added decoder streaming output and UVVM simulation
2018-11-30 16:25:00 +01:00
da6ab3236a
added constrain template
2018-11-29 14:07:45 +01:00
6b512782f3
migrate decoder sim from cvs: prints transfered data buffer to terminal
2018-11-29 13:05:15 +01:00
426fa8bc1c
added new GTX for Virtex-6 in HIPA Timing System
2018-07-16 15:00:47 +02:00
30d692b872
Repository was moved from git@git.psi.ch:DigitaleSignalVerarbeitung/Libraries/VHDL/evr320.git
2018-07-09 08:34:33 +02:00
5f1af19d28
signal name updated to introduced sync stage.
2018-06-26 14:52:06 +02:00
77adb7b9e2
reg sync, clean-up comments
2018-06-08 11:25:56 +02:00
