DEVEL: filter modification based on address decoding

hdl/evr320_data_filter.vhd

@@ -4,67 +4,85 @@
 --  Project:      evr320
 --  Authors:      Jonas Purtschert
 --  Description:  Filter a specific data field from data buffer stream of the decoder:
---  Modif:        Benoit Stef -> ADDRES is set as an input and not anymore as generic
+--  Modif:        Benoit Stef 
+--                not based on counter anymore but map to LSB into a generic array
 ------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_1164.all;
+
+library psi_lib;
+use psi_lib.psi_common_math_pkg.all;
 
 entity evr320_data_filter is
-  generic (
-    --ADDRESS   : std_logic_vector(11 downto 0);
-    NUM_BYTES : integer := 8
-  );
-  port (
-    -- User stream interface
-    i_stream_clk        : in    std_logic;                          -- user clock
-    i_stream_data       : in    std_logic_vector(7 downto 0);  
-    i_stream_addr       : in    std_logic_vector(10 downto 0);  
-    i_stream_valid      : in    std_logic;
-    i_address           : in    std_logic_vector(11 downto 0);
-    -- filter output:
-    o_data              : out   std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
-    o_valid             : out   std_logic := '0'
-  );
-end evr320_data_filter;
-
+  generic (NUM_BYTES : integer := 8);
+  port (   -- User stream interface
+          i_stream_clk        : in    std_logic;                          -- user clock
+          i_stream_data       : in    std_logic_vector(7 downto 0);  
+          i_stream_addr       : in    std_logic_vector(10 downto 0);  
+          i_stream_valid      : in    std_logic;
+          i_address           : in    std_logic_vector(11 downto 0);
+          -- filter output:
+          o_data              : out   std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
+          o_valid             : out   std_logic := '0'
+        );
+end entity;
 
 architecture behavioral of evr320_data_filter is
-
-  signal data_shift : std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
-  signal match : std_logic := '0';
-  signal shift_cnt : integer range 0 to NUM_BYTES;
-
+  -- array to store data value prior to map to output  
+  type byte_array_t is array (NUM_BYTES-1 downto 0) of std_logic_vector(i_stream_data'range);
+  signal table_s    : byte_array_t;
+  --pipe help 
+  signal addr_dff_s : std_logic_vector(10 downto 0)         := (others=>'0');
+  signal data_dff_s : std_logic_vector(i_stream_data'range) := (others=>'0');
+  signal filt_dff_s : std_logic_vector(i_address'range);
+  --helper
+  constant low_bd_c : integer := log2ceil(NUM_BYTES);   --compute LSB for address decoding
+  signal ena_s      : std_logic_vector(1 downto 0);     --clock enable vector
+  
 begin
-  process(i_stream_clk)
-    variable addr : std_logic_vector(10 downto 0) := (others=>'0');
-    variable data : std_logic_vector(7 downto 0) := (others=>'0');
+  
+  p : process(i_stream_clk)
   begin
-     if (rising_edge(i_stream_clk)) then
-       o_valid <= '0';
-
+    if (rising_edge(i_stream_clk)) then
+      
+       --*** 1st pipe stage ***
+       ena_s(0) <= i_stream_valid;
+       filt_dff_s <= i_address;
        if (i_stream_valid = '1') then
-         addr := i_stream_addr;
-         data := i_stream_data;
-
-         if (addr = i_address(10 downto 0) or match = '1') then
-           match <= '1';
-           if (shift_cnt < NUM_BYTES) then
-             data_shift <= data_shift((data_shift'high - data'length) downto 0) & data;
-             shift_cnt <= shift_cnt + 1;
-           else    -- all data fetched, send to out
-             match <= '0';
-             shift_cnt <= 0;
-             o_valid <= '1';
-             o_data <= data_shift;
-           end if;
-         end if; -- if addr match
-       end if;   -- if valid
-
+         addr_dff_s <= i_stream_addr;
+         data_dff_s <= i_stream_data;
+       end if;
+      
+      --*** filling the array ***
+      if ena_s(0) = '1' then   
+        if addr_dff_s(10 downto low_bd_c) = filt_dff_s(10 downto low_bd_c) then
+            --*** spatial loop *** 
+            ena_s(1) <= '1';
+            for i in 0 to NUM_BYTES-1 loop
+              if addr_dff_s(low_bd_c-1 downto 0) = to_uslv(i,low_bd_c) then
+                table_s(i) <= data_dff_s ;
+              end if;           
+            end loop;
+        end if;
+      else 
+        ena_s(1) <= '0';
+      end if;
+       
+      --*** set the output & valid accordingly*** 
+      if ena_s(1) = '1' then
+        if (from_uslv(addr_dff_s) = (from_uslv(filt_dff_s) + NUM_BYTES -1))  then
+          o_valid <= '1';
+          --*** spatial loop map output ***
+          for i in 0 to NUM_BYTES-1 loop
+            o_data(NUM_BYTES+i*NUM_BYTES-1 downto 0+i*NUM_BYTES) <= table_s(NUM_BYTES-1-i);
+          end loop;
+        else
+           o_valid <= '0';      
+        end if;
+      end if;
+      
      end if;
   end process;
-
-end behavioral;
+  
+end architecture;