AEK_8220_Libraries/firmware_vhdl_evr320
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migrate decoder sim from cvs: prints transfered data buffer to terminal

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This commit is contained in:
purtschert_j
2018-11-29 13:05:15 +01:00
parent 426fa8bc1c
commit 6b512782f3
6 changed files with 392 additions and 12 deletions
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7
hdl/evr320_pkg.vhd
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@ -60,7 +60,10 @@ package evr320_pkg is
data_error => '0',
usr_events_counter => (others =>'0'));
constant c_INIT_EVT_REC_CTRL : typ_evt_rec_ctrl := ( event_number => (others=>'0'),
event_enable => '0',
data_ack => '0',
error_ack => '0');
-- --------------------------------------------------------------------------
-- Function Prototypes
-- --------------------------------------------------------------------------
@ -95,4 +98,4 @@ package body evr320_pkg is
end package body evr320_pkg;
--------------------------------------------------------------------------------
-- End of file
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------

2
hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd
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@ -284,7 +284,7 @@ begin
)
port map (
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => i_mgt.ctrl.LOOPBACK, --tied_to_ground_vec_i(2 downto 0),
LOOPBACK => i_mgt.CTRL.LOOPBACK, --tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN => "00", --
TXPOWERDOWN => "00", --
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------

2
sim/ci.do
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@ -1,2 +1,2 @@
source run.tcl
quit
#quit

19
sim/config.tcl
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@ -10,7 +10,7 @@ run_suppress 8684,3479,3813,8009,3812
# EVR320 Decoder
add_sources $LibPath/Libraries/VHDL/evr320/hdl {
add_sources $LibPath/Firmware/VHDL/evr320/hdl {
evr320_pkg.vhd \
evr320_buffer.vhd \
evr320_dpram.vhd \
@ -18,8 +18,17 @@ add_sources $LibPath/Libraries/VHDL/evr320/hdl {
evr320_decoder.vhd \
} -tag evr320_decoder
# EVR320 Decoder Testbench
add_sources $LibPath/Firmware/VHDL/evr320/tb {
evr320_decoder_tb.vhd \
} -tag evr320_decoder_tb
# setup tb runs
create_tb_run "evr320_decoder_tb"
add_tb_run
# IFC1210 Bindings
add_sources $LibPath/Libraries/VHDL/evr320/hdl {
add_sources $LibPath/Firmware/VHDL/evr320/hdl {
v6vlx_gtxe1_pkg.vhd \
v6vlx_gtxe1_101MHz27_1Gbps0127.vhd \
v6vlx_gtxe1_142MHz8_2Gbps856.vhd \
@ -31,6 +40,8 @@ add_sources $LibPath/Libraries/VHDL/evr320/hdl {
# tosca2_glb_pkg dependency
add_library tosca2
add_sources $LibPath/Libraries/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
add_sources $LibPath/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
tosca2_glb_pkg.vhd \
}
}

32
sim/run.tcl
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@ -1,8 +1,30 @@
# Library Path
set LibPath "../../../../"
set LibPath "../../../.."
#Load dependencies
source $LibPath/Libraries/TCL/PsiSim/PsiSim.tcl
pwd
vlib work
vmap work work
# Check if running in jenkins environment
if [info exists env(JENKINS_HOME)] {
set jenkins 1
} else {
set jenkins 0
}
# map different libraries when running on jenkins machine:
if {$jenkins == 1} {
vmap unisim /home/modelsim/xilinx_libs/13.4/unisim
vmap xilinxcorelib /home/modelsim/xilinx_libs/13.4/xilinxcorelib
vmap secureip /home/modelsim/xilinx_libs/13.4/secureip
} else {
vmap unisim C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
vmap xilinxcorelib C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/xilinxcorelib
vmap secureip C:/Xilinx/13.4/ISE_DS/ISE/vhdl/mti_se/10.3c/nt64/unisim
}
#Load dependencies TODO
source $LibPath/Firmware/TCL/PsiSim/PsiSim.tcl
#Import psi::sim library
namespace import psi::sim::*
@ -19,7 +41,9 @@ puts "-- Compile"
puts "------------------------------"
clean_libraries -all
compile_files -tag evr320_decoder
compile_files -tag evr320_decoder_tb
#compile_files -lib tosca2
#compile_files -lib evr320
run_check_errors "###ERROR###"
run_tb -all
run_check_errors "###ERROR###"

342
tb/evr320_decoder_tb.vhd Normal file
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@ -0,0 +1,342 @@
--------------------------------------------------------------------------------
-- Paul Scherrer Institute (PSI)
--------------------------------------------------------------------------------
-- Unit : evr320_decoder_tb.vhd
-- Author : Goran Marinkovic, Section Diagnostic
-- Version : $Revision: 1.1 $
--------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
--------------------------------------------------------------------------------
-- Comment : This is the test bench for the evr component.
--------------------------------------------------------------------------------
-- Std. library (platform) -----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
library std;
use std.env.all;
use std.textio.all;
-- Work library (application) --------------------------------------------------
library work;
use work.evr320_pkg.all;
entity evr320_decoder_tb is
end entity;
architecture testbench of evr320_decoder_tb is
---------------------------------------------------------------------------
-- System
---------------------------------------------------------------------------
-- System
constant C_RXUSRCLK_CYCLE : time:= 7 ns;
constant C_USRCLK_CYCLE : time:= 8 ns;
---------------------------------------------------------------------------
-- MGT stream
---------------------------------------------------------------------------
type mgt_stream_sample_type is record
data : std_logic_vector(15 downto 0);
charisk : std_logic_vector( 1 downto 0);
end record mgt_stream_sample_type;
type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
signal mgt_stream_index : integer range 0 to 127 := 0;
constant mgt_stream : mgt_stream_type(0 to 127) :=
(
0 => (data => X"0000", charisk => "00"), -- gap
1 => (data => X"00BC", charisk => "01"), -- align
2 => (data => X"0000", charisk => "00"), -- gap
3 => (data => X"0000", charisk => "00"), -- gap
4 => (data => X"0000", charisk => "00"), -- gap
5 => (data => X"00BC", charisk => "01"), -- align
6 => (data => X"0000", charisk => "00"), -- gap
7 => (data => X"0000", charisk => "00"), -- gap
8 => (data => X"0000", charisk => "00"), -- gap
9 => (data => X"00BC", charisk => "01"), -- align
10 => (data => X"5C00", charisk => "10"), -- frame start
11 => (data => X"0000", charisk => "00"), -- gap
12 => (data => X"0200", charisk => "00"), -- frame byte
13 => (data => X"00BC", charisk => "01"), -- align
14 => (data => X"DB00", charisk => "00"), -- frame byte
15 => (data => X"0000", charisk => "00"), -- gap
16 => (data => X"9300", charisk => "00"), -- frame byte
17 => (data => X"00BC", charisk => "01"), -- align
18 => (data => X"3600", charisk => "00"), -- frame byte
19 => (data => X"0000", charisk => "00"), -- gap
20 => (data => X"4100", charisk => "00"), -- frame byte
21 => (data => X"00BC", charisk => "01"), -- align
22 => (data => X"0000", charisk => "00"), -- frame byte
23 => (data => X"0000", charisk => "00"), -- gap
24 => (data => X"0000", charisk => "00"), -- frame byte
25 => (data => X"00BC", charisk => "01"), -- align
26 => (data => X"0000", charisk => "00"), -- frame byte
27 => (data => X"0000", charisk => "00"), -- gap
28 => (data => X"0000", charisk => "00"), -- frame byte
29 => (data => X"00BC", charisk => "01"), -- align
30 => (data => X"A300", charisk => "00"), -- frame byte
31 => (data => X"0000", charisk => "00"), -- gap
32 => (data => X"1D00", charisk => "00"), -- frame byte
33 => (data => X"00BC", charisk => "01"), -- align
34 => (data => X"7F00", charisk => "00"), -- frame byte
35 => (data => X"0000", charisk => "00"), -- gap
36 => (data => X"3300", charisk => "00"), -- frame byte
37 => (data => X"00BC", charisk => "01"), -- align
38 => (data => X"9B00", charisk => "00"), -- frame byte
39 => (data => X"0000", charisk => "00"), -- gap
40 => (data => X"F300", charisk => "00"), -- frame byte
41 => (data => X"00BC", charisk => "01"), -- align
42 => (data => X"5100", charisk => "00"), -- frame byte
43 => (data => X"0000", charisk => "00"), -- gap
44 => (data => X"0400", charisk => "00"), -- frame byte
45 => (data => X"00BC", charisk => "01"), -- align
46 => (data => X"6B00", charisk => "00"), -- frame byte
47 => (data => X"0000", charisk => "00"), -- gap
48 => (data => X"7C00", charisk => "00"), -- frame byte
49 => (data => X"00BC", charisk => "01"), -- align
50 => (data => X"1600", charisk => "00"), -- frame byte
51 => (data => X"0000", charisk => "00"), -- gap
52 => (data => X"0000", charisk => "00"), -- frame byte
53 => (data => X"00BC", charisk => "01"), -- align
54 => (data => X"0000", charisk => "00"), -- frame byte
55 => (data => X"0000", charisk => "00"), -- gap
56 => (data => X"0000", charisk => "00"), -- frame byte
57 => (data => X"00BC", charisk => "01"), -- align
58 => (data => X"0000", charisk => "00"), -- frame byte
59 => (data => X"0000", charisk => "00"), -- gap
60 => (data => X"0000", charisk => "00"), -- frame byte
61 => (data => X"00BC", charisk => "01"), -- align
62 => (data => X"0000", charisk => "00"), -- frame byte
63 => (data => X"0000", charisk => "00"), -- gap
64 => (data => X"0000", charisk => "00"), -- frame byte
65 => (data => X"00BC", charisk => "01"), -- align
66 => (data => X"0000", charisk => "00"), -- frame byte
67 => (data => X"0000", charisk => "00"), -- gap
68 => (data => X"0000", charisk => "00"), -- frame byte
69 => (data => X"00BC", charisk => "01"), -- align
70 => (data => X"0000", charisk => "00"), -- frame byte
71 => (data => X"0000", charisk => "00"), -- gap
72 => (data => X"0000", charisk => "00"), -- frame byte
73 => (data => X"00BC", charisk => "01"), -- align
74 => (data => X"0000", charisk => "00"), -- frame byte
75 => (data => X"0000", charisk => "00"), -- gap
76 => (data => X"0000", charisk => "00"), -- frame byte
77 => (data => X"00BC", charisk => "01"), -- align
78 => (data => X"3C00", charisk => "10"), -- frame end
79 => (data => X"0000", charisk => "00"), -- gap
80 => (data => X"F900", charisk => "00"), -- check sum MSB
81 => (data => X"00BC", charisk => "01"), -- align
82 => (data => X"C600", charisk => "00"), -- check sum LSB
83 => (data => X"0000", charisk => "00"), -- gap
84 => (data => X"0000", charisk => "00"), -- gap
85 => (data => X"00BC", charisk => "01"), -- align
86 => (data => X"0000", charisk => "00"), -- gap
87 => (data => X"0000", charisk => "00"), -- gap
88 => (data => X"0000", charisk => "00"), -- gap
89 => (data => X"00BC", charisk => "01"), -- align
90 => (data => X"0000", charisk => "00"), -- gap
91 => (data => X"0000", charisk => "00"), -- gap
92 => (data => X"0000", charisk => "00"), -- gap
93 => (data => X"00BC", charisk => "01"), -- align
94 => (data => X"0000", charisk => "00"), -- gap
95 => (data => X"0000", charisk => "00"), -- gap
96 => (data => X"0000", charisk => "00"), -- gap
97 => (data => X"00BC", charisk => "01"), -- align
98 => (data => X"0000", charisk => "00"), -- gap
99 => (data => X"0000", charisk => "00"), -- gap
100 => (data => X"0000", charisk => "00"), -- gap
101 => (data => X"00BC", charisk => "01"), -- align
102 => (data => X"0000", charisk => "00"), -- gap
103 => (data => X"0000", charisk => "00"), -- gap
104 => (data => X"0000", charisk => "00"), -- gap
105 => (data => X"00BC", charisk => "01"), -- align
106 => (data => X"0000", charisk => "00"), -- gap
107 => (data => X"0000", charisk => "00"), -- gap
108 => (data => X"0000", charisk => "00"), -- gap
109 => (data => X"00BC", charisk => "01"), -- align
110 => (data => X"0000", charisk => "00"), -- gap
111 => (data => X"0000", charisk => "00"), -- gap
112 => (data => X"0000", charisk => "00"), -- gap
113 => (data => X"00BC", charisk => "01"), -- align
114 => (data => X"0000", charisk => "00"), -- gap
115 => (data => X"0000", charisk => "00"), -- gap
116 => (data => X"0000", charisk => "00"), -- gap
117 => (data => X"00BC", charisk => "01"), -- align
118 => (data => X"0000", charisk => "00"), -- gap
119 => (data => X"0000", charisk => "00"), -- gap
120 => (data => X"0000", charisk => "00"), -- gap
121 => (data => X"00BC", charisk => "01"), -- align
122 => (data => X"0000", charisk => "00"), -- gap
123 => (data => X"0000", charisk => "00"), -- gap
124 => (data => X"0000", charisk => "00"), -- gap
125 => (data => X"00BC", charisk => "01"), -- align
126 => (data => X"0000", charisk => "00"), -- gap
127 => (data => X"000F", charisk => "00") -- BPM event
);
-----------------------------------------------------------------------------
-- Timing decoder interface
-----------------------------------------------------------------------------
-- Link status
signal rxlos : std_logic := '0';
-- Clock
signal rxusrclk : std_logic := '0';
-- Data
signal rxdata : std_logic_vector(15 downto 0) := (others => '0');
-- Status 8B/10B decoder
signal rxcharisk : std_logic_vector( 1 downto 0) := (others => '0');
signal usr_clk : std_logic := '0';
signal evr_params : typ_evr320_params;
signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
signal usr_events : std_logic_vector( 3 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------------
-- Timing decoder
-----------------------------------------------------------------------------
evr320_decoder_inst: entity work.evr320_decoder
port map
(
--------------------------------------------------------------------------
-- Debug interface
--------------------------------------------------------------------------
debug_clk => open,
debug => open,
--------------------------------------------------------------------------
-- GTX parallel interface
--------------------------------------------------------------------------
i_mgt_rst => rxlos,
i_mgt_rx_clk => rxusrclk,
i_mgt_rx_data => rxdata,
i_mgt_rx_charisk => rxcharisk,
--------------------------------------------------------------------------
-- User interface CPU clock
--------------------------------------------------------------------------
i_usr_clk => usr_clk,
i_evr_params => evr_params,
o_event_recorder_stat => open,
i_event_recorder_ctrl => c_INIT_EVT_REC_CTRL,
i_mem_addr => mem_addr,
o_mem_data => mem_data,
--------------------------------------------------------------------------
-- User interface MGT clock
--------------------------------------------------------------------------
o_usr_events => usr_events,
o_usr_events_ext => open,
o_sos_event => open
);
-----------------------------------------------------------------------------
-- MGT clock
-----------------------------------------------------------------------------
process
begin
loop
rxusrclk <= '0';
wait for C_RXUSRCLK_CYCLE / 2;
rxusrclk <= '1';
wait for C_RXUSRCLK_CYCLE / 2;
end loop;
end process;
-----------------------------------------------------------------------------
-- User clock
-----------------------------------------------------------------------------
process
begin
loop
usr_clk <= '0';
wait for C_USRCLK_CYCLE / 2;
usr_clk <= '1';
wait for C_USRCLK_CYCLE / 2;
end loop;
end process;
-----------------------------------------------------------------------------
-- Decoder reset due to MGT main status
-----------------------------------------------------------------------------
process
begin
rxlos <= '1';
wait for 50 ns;
wait until (falling_edge(rxusrclk));
rxlos <= '0';
wait ;
end process;
-----------------------------------------------------------------------------
-- Stimulus MGT interface
-----------------------------------------------------------------------------
-- mgt_stream_index_proc: process(rxusrclk)
-- begin
-- if rising_edge(rxusrclk) then
-- mgt_stream_index <= mgt_stream_index + 1;
-- end if;
-- end process mgt_stream_index_proc;
rxdata <= mgt_stream(mgt_stream_index).data;
rxcharisk <= mgt_stream(mgt_stream_index).charisk;
-----------------------------------------------------------------------------
-- Stimulus CPU interface
-----------------------------------------------------------------------------
process
variable mgt_stream_rep_var : integer := 0;
variable mgt_stream_index_var : integer := 0;
begin
--------------------------------------------------------------------------
-- Get out of reset
--------------------------------------------------------------------------
evr_params.event_enable( 0) <= '1';
evr_params.event_enable( 1) <= '0';
evr_params.event_enable( 2) <= '0';
evr_params.event_enable( 3) <= '0';
evr_params.event_numbers( 0)<= X"0F";
evr_params.event_numbers( 1)<= X"00";
evr_params.event_numbers( 2)<= X"00";
evr_params.event_numbers( 3)<= X"00";
evr_params.cs_min_cnt <= X"00000010";
evr_params.cs_min_time <= X"00000100";
mem_addr <= x"000";
wait until (rxlos = '0');
--------------------------------------------------------------------------
-- Test receiving a package
--------------------------------------------------------------------------
for mgt_stream_rep_var in 0 to 10 loop
wait for 1 ns;
for mgt_stream_index_var in 0 to 127 loop
wait until rising_edge(rxusrclk);
mgt_stream_index <= mgt_stream_index_var;
end loop;
end loop;
-- print 16 words from data buffer:
for offset in 0 to 16 loop
mem_addr <= std_logic_vector(to_unsigned(8 + offset, 12));
wait until rising_edge(rxusrclk);
wait until rising_edge(rxusrclk);
report "dpram: 0x" & to_hstring(mem_addr) & " : 0x" & to_hstring(mem_data);
end loop;
--------------------------------------------------------------------------
-- Test Done
--------------------------------------------------------------------------
stop(0);
wait;
end process;
end architecture testbench;
--------------------------------------------------------------------------------
-- End of file
--------------------------------------------------------------------------------