AEK_8220_Libraries/firmware_vhdl_evr320
0
0
Fork 0
Code Issues 5 Pull Requests Actions Packages Projects Releases Wiki Activity

added new GTX for Virtex-6 in HIPA Timing System

Browse Source
This commit is contained in:
bucher_p1
2018-07-16 15:00:47 +02:00
parent 30d692b872
commit 426fa8bc1c
9 changed files with 1270 additions and 719 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
Changelog.md
View File

@ -1,11 +1,19 @@
## 2.1
## 2.2
* Added Features
* Event Recorder functionality implemented as an option
* IFC1210 bindings for tosca2
* Bugfixes
* None
* Added Features
* HIPA option for Virtex-6 GTX -> pkg_v6vlx_gtxe1.vhd separated to different files to avoid duplicated code.
* use_MMCM generic is derived from FACILITY generic which implicitly contains line rate (use MMCM when line rate > 2.5Gbps).
* Bugfixes
* signal names in added sync stage were not adapted.
## 2.1
* Added Features
* Event Recorder functionality implemented as an option
* IFC1210 bindings for tosca2
* Bugfixes
* None
## 2.0
* Migration from CVS /G/GPAC/Lib/Vivado_Lib/axi_evr320_2.0
* Migration from CVS /G/GPAC/Lib/Vivado_Lib/axi_evr320_2.0

4
README.md
View File

@ -32,10 +32,10 @@ Examples for things that do not belong into this library:
- none
### Simulation
- Libraries/TCL/PsiSim
- Libraries/Firmware/TCL/PsiSim
### with IFC1210 Bindings
- Libraries/BoardSupport/ifc1210/tosca2
- Libraries/BoardSupport/IFC1210/tosca2

11
hdl/evr320_ifc1210_wrapper.vhd
View File

@ -17,15 +17,14 @@ library tosca2;
use tosca2.tosca2_glb_pkg.all;
use work.evr320_pkg.all;
use work.pkg_v6vlx_gtxe1.all;
use work.v6vlx_gtxe1_pkg.all;
entity evr320_ifc1210_wrapper is
generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16";
g_REFCLK_MHZ : real := 142.8;
g_USE_MMCM : boolean := false;
g_EVENT_RECORDER : boolean := false
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false -- enable/disable Event Recorder functionality
);
port(
tick1sec_i : in std_logic;
@ -193,7 +192,7 @@ begin
mgt_wrapper_inst: entity work.v6vlx_gtxe1_wrapper
generic map(
g_MGT_LOCATION => g_MGT_LOCATION,
g_USE_MMCM => g_USE_MMCM )
g_FACILITY => g_FACILITY )
port map(
-- MGT serial interface
i_mgt_refclk => mgt_refclk_i,

494
hdl/v6vlx_gtxe1_101MHz27_1Gbps0127.vhd Normal file
View File

@ -0,0 +1,494 @@
------------------------------------------------------------------------------
-- Paul Scherrer Institute (PSI)
------------------------------------------------------------------------------
-- Unit : v6vlx_gtxe1_101MHz27_1Gbps0127.vhd
-- Author : Goran Marinkovic, Section Diagnostic
-- : Waldemar Koprek, Section Diagnostic
-- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright<68> PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment : Virtex-6 GTXE1 primitive configured for HIPA 50.63282 MHz
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.v6vlx_gtxe1_pkg.all;
entity v6vlx_gtxe1_101MHz27_1Gbps0127 is
generic(
g_MGT_LOCATION : string
);
port (
i_mgt : in gtxe_in_type;
o_mgt : out gtxe_out_type
);
end v6vlx_gtxe1_101MHz27_1Gbps0127;
architecture RTL of v6vlx_gtxe1_101MHz27_1Gbps0127 is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
--***************************** Main Body of Code *****************************
signal slv_mgtrefclk : std_logic_vector(1 downto 0);
signal debug_refclk : std_logic_vector(1 downto 0);
--************************** Attribute Declarations ***************************
attribute LOC : string;
attribute LOC of gtxe1_i : label is g_MGT_LOCATION;
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
slv_mgtrefclk <= "0" & i_mgt.ctrl.CLKIN;
o_mgt.ctrl.REFCLKOUT <= debug_refclk(1);
--------------------------------- GTX Instance -----------------------------
gtxe1_i :GTXE1
generic map (
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_GTXRESET_SPEEDUP => (1), --(GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
SIM_RXREFCLK_SOURCE => ("000"),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE => "RXPLL", --
TX_OVERSAMPLE_MODE => FALSE, --
TXPLL_COM_CFG => X"21680A", --
TXPLL_CP_CFG => X"0D", --
TXPLL_DIVSEL_FB => 4, -- 1.2GHz < Fpll < 2.7GHz
TXPLL_DIVSEL_OUT => 4, --
TXPLL_DIVSEL_REF => 1, -- RXPLL_DIVSEL_FB * RXPLL_DIVSEL45_FB
TXPLL_DIVSEL45_FB => 5, -- Fpll = Fclkin -----------------------------------
TXPLL_LKDET_CFG => "111", -- RXPLL_DIVSEL_REF
TX_CLK25_DIVIDER => 4, --
TXPLL_SATA => "00", -- Fpll * 2
TX_TDCC_CFG => "00", -- Flinerate = ------------------
PMA_CAS_CLK_EN => FALSE, -- RXPLL_DIVSEL_OUT(FALSE)
POWER_SAVE => "0000110100", -- [4] '1' = bypass trasmit delay aligner, [5] '1' = bypass receive delay aligner
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => (TRUE), --
TX_DATA_WIDTH => (20), --
TX_USRCLK_CFG => (X"00"), --
TXOUTCLK_CTRL => ("TXOUTCLKPMA_DIV2"), --
TXOUTCLK_DLY => ("0000000000"), --
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => ('0'), --
PMA_TX_CFG => (x"80082"), --
TX_BUFFER_USE => (TRUE), --
TX_BYTECLK_CFG => (x"00"), --
TX_EN_RATE_RESET_BUF => (TRUE), --
TX_XCLK_SEL => ("TXOUT"), --
TX_DLYALIGN_CTRINC => ("0100"), --
TX_DLYALIGN_LPFINC => ("0110"), --
TX_DLYALIGN_MONSEL => ("000"), --
TX_DLYALIGN_OVRDSETTING => ("10000000"), --
-------------------------TX Gearbox--------------------------- --
GEARBOX_ENDEC => ("000"), --
TXGEARBOX_USE => (FALSE), --
--
----------------TX Driver and OOB Signalling------------------ --
TX_DRIVE_MODE => ("DIRECT"), --
TX_IDLE_ASSERT_DELAY => ("100"), --
TX_IDLE_DEASSERT_DELAY => ("010"), --
TXDRIVE_LOOPBACK_HIZ => (FALSE), --
TXDRIVE_LOOPBACK_PD => (FALSE), --
--
--------------TX Pipe Control for PCI Express/SATA------------ --
COM_BURST_VAL => ("1111"), --
--
------------------TX Attributes for PCI Express--------------- --
TX_DEEMPH_0 => ("11010"), --
TX_DEEMPH_1 => ("10000"), --
TX_MARGIN_FULL_0 => ("1001110"), --
TX_MARGIN_FULL_1 => ("1001001"), --
TX_MARGIN_FULL_2 => ("1000101"), --
TX_MARGIN_FULL_3 => ("1000010"), --
TX_MARGIN_FULL_4 => ("1000000"), --
TX_MARGIN_LOW_0 => ("1000110"), --
TX_MARGIN_LOW_1 => ("1000100"), --
TX_MARGIN_LOW_2 => ("1000010"), --
TX_MARGIN_LOW_3 => ("1000000"), --
TX_MARGIN_LOW_4 => ("1000000"), --
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE => FALSE, -- 1.2GHz < Fpll < 2.7GHz
RXPLL_COM_CFG => (x"21680a"), --
RXPLL_CP_CFG => (x"0D"), -- RXPLL_DIVSEL_FB * RXPLL_DIVSEL45_FB
RXPLL_DIVSEL_FB => 4, -- Fpll = Fclkin -----------------------------------
RXPLL_DIVSEL_OUT => 4, -- RXPLL_DIVSEL_REF
RXPLL_DIVSEL_REF => 1, --
RXPLL_DIVSEL45_FB => 5, -- Fpll * 2
RXPLL_LKDET_CFG => ("111"), -- Flinerate = ------------------
RX_CLK25_DIVIDER => 4, -- RXPLL_DIVSEL_OUT
-------------------------RX Interface-------------------------
GEN_RXUSRCLK => (TRUE), --
RX_DATA_WIDTH => (20), --
RXRECCLK_CTRL => ("RXRECCLKPMA_DIV2"), --
RXRECCLK_DLY => ("0000000000"), --
RXUSRCLK_DLY => (x"0000"), --
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => (FALSE), --
CDR_PH_ADJ_TIME => ("10100"), --
OOBDETECT_THRESHOLD => ("011"), --
PMA_CDR_SCAN => (x"640404C"), --
PMA_RX_CFG => (x"05ce008"), --
RCV_TERM_GND => (FALSE), --
RCV_TERM_VTTRX => (TRUE), --
RX_EN_IDLE_HOLD_CDR => (FALSE), --
RX_EN_IDLE_RESET_FR => (FALSE), --
RX_EN_IDLE_RESET_PH => (FALSE), --
TX_DETECT_RX_CFG => (x"1832"), --
TERMINATION_CTRL => ("00000"), --
TERMINATION_OVRD => (FALSE), --
CM_TRIM => ("01"), --
PMA_RXSYNC_CFG => (x"00"), --
PMA_CFG => (x"0040000040000000003"), --
BGTEST_CFG => ("00"), --
BIAS_CFG => (x"00000"), --
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME => ("01100"), --
DFE_CFG => ("00011011"), --
RX_EN_IDLE_HOLD_DFE => (TRUE), --
RX_EYE_OFFSET => (x"4C"), --
RX_EYE_SCANMODE => ("00"), --
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK => ('0'), --
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => (2), --(1),
COMMA_10B_ENABLE => ("1111111111"), --
COMMA_DOUBLE => (FALSE), --
DEC_MCOMMA_DETECT => (TRUE), --(FALSE),
DEC_PCOMMA_DETECT => (TRUE), --(FALSE),
DEC_VALID_COMMA_ONLY => (FALSE), --
MCOMMA_10B_VALUE => ("1010000011"), --
MCOMMA_DETECT => (TRUE), --
PCOMMA_10B_VALUE => ("0101111100"), --
PCOMMA_DETECT => (TRUE), --
RX_DECODE_SEQ_MATCH => (FALSE), --
RX_SLIDE_AUTO_WAIT => (5), --
RX_SLIDE_MODE => ("PMA"), --
SHOW_REALIGN_COMMA => (FALSE), --
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (8), --
RX_LOS_THRESHOLD => (128), --
RX_LOSS_OF_SYNC_FSM => (TRUE), --(FALSE),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (FALSE), --
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE => (FALSE), --
RX_EN_IDLE_RESET_BUF => (FALSE), --
RX_EN_MODE_RESET_BUF => (TRUE), --
RX_EN_RATE_RESET_BUF => (TRUE), --
RX_EN_REALIGN_RESET_BUF => (FALSE), --
RX_EN_REALIGN_RESET_BUF2 => (FALSE), --
RX_FIFO_ADDR_MODE => ("FAST"), --
RX_IDLE_HI_CNT => ("1000"), --
RX_IDLE_LO_CNT => ("0000"), --
RX_XCLK_SEL => ("RXUSR"), --
RX_DLYALIGN_CTRINC => ("1110"), --
RX_DLYALIGN_EDGESET => ("00010"), --
RX_DLYALIGN_LPFINC => ("1110"), --
RX_DLYALIGN_MONSEL => ("000"), --
RX_DLYALIGN_OVRDSETTING => ("10000000"), --
------------------------Clock Correction---------------------- --
CLK_COR_ADJ_LEN => (1), --
CLK_COR_DET_LEN => (1), --
CLK_COR_INSERT_IDLE_FLAG => (FALSE), --
CLK_COR_KEEP_IDLE => (FALSE), --
CLK_COR_MAX_LAT => (16), --
CLK_COR_MIN_LAT => (14), --
CLK_COR_PRECEDENCE => (TRUE), --
CLK_COR_REPEAT_WAIT => (0), --
CLK_COR_SEQ_1_1 => ("0000000000"), --
CLK_COR_SEQ_1_2 => ("0000000000"), --
CLK_COR_SEQ_1_3 => ("0000000000"), --
CLK_COR_SEQ_1_4 => ("0000000000"), --
CLK_COR_SEQ_1_ENABLE => ("1111"), --
CLK_COR_SEQ_2_1 => ("0000000000"), --
CLK_COR_SEQ_2_2 => ("0000000000"), --
CLK_COR_SEQ_2_3 => ("0000000000"), --
CLK_COR_SEQ_2_4 => ("0000000000"), --
CLK_COR_SEQ_2_ENABLE => ("1111"), --
CLK_COR_SEQ_2_USE => (FALSE), --
CLK_CORRECT_USE => (FALSE), --
--
------------------------Channel Bonding---------------------- --
CHAN_BOND_1_MAX_SKEW => (1), --
CHAN_BOND_2_MAX_SKEW => (1), --
CHAN_BOND_KEEP_ALIGN => (FALSE), --
CHAN_BOND_SEQ_1_1 => ("0000000000"), --
CHAN_BOND_SEQ_1_2 => ("0000000000"), --
CHAN_BOND_SEQ_1_3 => ("0000000000"), --
CHAN_BOND_SEQ_1_4 => ("0000000000"), --
CHAN_BOND_SEQ_1_ENABLE => ("1111"), --
CHAN_BOND_SEQ_2_1 => ("0000000000"), --
CHAN_BOND_SEQ_2_2 => ("0000000000"), --
CHAN_BOND_SEQ_2_3 => ("0000000000"), --
CHAN_BOND_SEQ_2_4 => ("0000000000"), --
CHAN_BOND_SEQ_2_CFG => ("00000"), --
CHAN_BOND_SEQ_2_ENABLE => ("1111"), --
CHAN_BOND_SEQ_2_USE => (FALSE), --
CHAN_BOND_SEQ_LEN => (1), --
PCI_EXPRESS_MODE => (FALSE), --
--
-------------RX Attributes for PCI Express/SATA/SAS---------- --
SAS_MAX_COMSAS => (52), --
SAS_MIN_COMSAS => (40), --
SATA_BURST_VAL => ("100"), --
SATA_IDLE_VAL => ("100"),
SATA_MAX_BURST => (9),
SATA_MAX_INIT => (27),
SATA_MAX_WAKE => (9),
SATA_MIN_BURST => (5),
SATA_MIN_INIT => (15),
SATA_MIN_WAKE => (5),
TRANS_TIME_FROM_P2 => (x"03c"),
TRANS_TIME_NON_P2 => (x"19"), --
TRANS_TIME_RATE => (x"ff"), --
TRANS_TIME_TO_P2 => (x"064") --
)
port map (
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => i_mgt.ctrl.LOOPBACK, --tied_to_ground_vec_i(2 downto 0),
RXPOWERDOWN => "00", --
TXPOWERDOWN => "00", --
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID => open, --
RXGEARBOXSLIP => tied_to_ground_i, --
RXHEADER => open, --
RXHEADERVALID => open, --
RXSTARTOFSEQ => open, --
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA => o_mgt.rx.RXCHARISCOMMA, --
RXCHARISK => o_mgt.rx.RXCHARISK, --
RXDEC8B10BUSE => '1', --tied_to_ground_i,
RXDISPERR => o_mgt.rx.RXDISPERR, --rxdisperr_i,
RXNOTINTABLE => o_mgt.rx.RXNOTINTABLE, --
RXRUNDISP => o_mgt.rx.RXRUNDISP, --
USRCODEERR => tied_to_ground_i, --
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ => open, --
RXCHBONDI => tied_to_ground_vec_i(3 downto 0), --
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0), --
RXCHBONDMASTER => tied_to_ground_i, --
RXCHBONDO => open, --
RXCHBONDSLAVE => tied_to_ground_i, --
RXENCHANSYNC => tied_to_ground_i, --
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => open, --
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED => o_mgt.rx.RXBYTEISALIGNED, --RXBYTEISALIGNED_OUT,
RXBYTEREALIGN => o_mgt.rx.RXBYTEREALIGN, --RXBYTEREALIGN_OUT,
RXCOMMADET => o_mgt.rx.RXCOMMADET, --RXCOMMADET_OUT,
RXCOMMADETUSE => '1', --tied_to_vcc_i,
RXENMCOMMAALIGN => i_mgt.rx.RXENMCOMMAALIGN, --tied_to_ground_i,
RXENPCOMMAALIGN => i_mgt.rx.RXENPCOMMAALIGN, --tied_to_ground_i,
RXSLIDE => i_mgt.rx.RXSLIDE,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET => tied_to_ground_i, --
RXENPRBSTST => tied_to_ground_vec_i(2 downto 0), --
RXPRBSERR => open, --
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA => o_mgt.rx.RXDATA, --rxdata_i,
RXRECCLK => o_mgt.rx.RXRECCLK, --RXRECCLK_OUT,
RXRECCLKPCS => open,
RXRESET => i_mgt.rx.RXRESET, --tied_to_ground_i,
RXUSRCLK => i_mgt.rx.RXUSRCLK, --tied_to_ground_i,
RXUSRCLK2 => i_mgt.rx.RXUSRCLK2, --RXUSRCLK2_IN,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0), --
DFECLKDLYADJMON => open, --
DFEDLYOVRD => tied_to_ground_i, --
DFEEYEDACMON => open, --
DFESENSCAL => open, --
DFETAP1 => tied_to_ground_vec_i(4 downto 0), --
DFETAP1MONITOR => open, --
DFETAP2 => tied_to_ground_vec_i(4 downto 0), --
DFETAP2MONITOR => open, --
DFETAP3 => tied_to_ground_vec_i(3 downto 0), --
DFETAP3MONITOR => open, --
DFETAP4 => tied_to_ground_vec_i(3 downto 0), --
DFETAP4MONITOR => open, --
DFETAPOVRD => tied_to_vcc_i, --
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE => tied_to_vcc_i, --
IGNORESIGDET => tied_to_vcc_i, --
RXCDRRESET => i_mgt.rx.RXCDRRESET, --
RXELECIDLE => o_mgt.rx.RXELECIDLE, --open,
RXEQMIX(9 downto 3) => tied_to_ground_vec_i(6 downto 0), --
RXEQMIX(2 downto 0) => "000", --RXEQMIX_IN,
RXN => i_mgt.rx.RXP, --RXN_IN,
RXP => i_mgt.rx.RXN, --RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => tied_to_ground_i, --
RXBUFSTATUS => open, --
RXCHANISALIGNED => open, --
RXCHANREALIGN => open, --
RXDLYALIGNDISABLE => i_mgt.rx.RXDLYALIGNDISABLE, --
RXDLYALIGNMONENB => i_mgt.rx.RXDLYALIGNMONENB, --
RXDLYALIGNMONITOR => o_mgt.rx.RXDLYALIGNMONITOR, --
RXDLYALIGNOVERRIDE => i_mgt.rx.RXDLYALIGNOVERRIDE, --
RXDLYALIGNRESET => i_mgt.rx.RXDLYALIGNRESET, --
RXDLYALIGNSWPPRECURB => tied_to_vcc_i, --
RXDLYALIGNUPDSW => tied_to_ground_i, --
RXENPMAPHASEALIGN => i_mgt.rx.RXENPMAPHASEALIGN, --RXENPMAPHASEALIGN_IN,
RXPMASETPHASE => i_mgt.rx.RXPMASETPHASE, --RXPMASETPHASE_IN,
RXSTATUS => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC => o_mgt.rx.RXLOSSOFSYNC, --
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN => tied_to_ground_i, --
RXOVERSAMPLEERR => open, --
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX => '0', --
GTXRXRESET => i_mgt.ctrl.GTXRESET, --GTXRXRESET_IN,
MGTREFCLKRX => slv_mgtrefclk, --MGTREFCLKRX_IN,
NORTHREFCLKRX => "00", --
PERFCLKRX => '0', --
PLLRXRESET => i_mgt.ctrl.PLLRXRESET, --PLLRXRESET_IN,
RXPLLLKDET => o_mgt.ctrl.RXPLLLKDET , --RXPLLLKDET_OUT,
RXPLLLKDETEN => '1', --
RXPLLPOWERDOWN => '0', --
RXPLLREFSELDY => "000", -- GREFCLKRX
RXRATE => "00", --
RXRATEDONE => open, --
RXRESETDONE => o_mgt.ctrl.RXRESETDONE , --RXRESETDONE_OUT,
SOUTHREFCLKRX => "00", --
-------------- Receive Ports - RX Pipe Control for PCI Express ------------- --
PHYSTATUS => open, --
RXVALID => open, --
----------------- Receive Ports - RX Polarity Control Ports ---------------- --
RXPOLARITY => tied_to_ground_i, --
--------------------- Receive Ports - RX Ports for SATA -------------------- --
COMINITDET => open, --
COMSASDET => open, --
COMWAKEDET => open, --
----------------------------------------------------------------------------
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------ --
----------------------------------------------------------------------------
DADDR => tied_to_ground_vec_i(7 downto 0), --
DCLK => tied_to_ground_i, --
DEN => tied_to_ground_i, --
DI => tied_to_ground_vec_i(15 downto 0), --
DRDY => open, --
DRPDO => open, --
DWE => tied_to_ground_i, --
----------------------------------------------------------------------------
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
----------------------------------------------------------------------------
TXGEARBOXREADY => open, --
TXHEADER => tied_to_ground_vec_i(2 downto 0), --
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0), --
TXSTARTSEQ => tied_to_ground_i, --
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B => i_mgt.tx.TXBYPASS8B10B, --tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE => i_mgt.tx.TXCHARDISPMODE, --txchardispmode_i,
TXCHARDISPVAL => i_mgt.tx.TXCHARDISPVAL , --txchardispval_i,
TXCHARISK => i_mgt.tx.TXCHARISK , --tied_to_ground_vec_i(3 downto 0),
TXENC8B10BUSE => '1', --tied_to_ground_i,
TXKERR => o_mgt.tx.TXKERR , --open,
TXRUNDISP => o_mgt.tx.TXRUNDISP, --open,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST => "1000000000000", --
MGTREFCLKFAB => debug_refclk, --
TSTCLK0 => tied_to_ground_i, --
TSTCLK1 => tied_to_ground_i, --
TSTIN => "11111111111111111111", --
TSTOUT => open, --
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => i_mgt.tx.TXDATA, --txdata_i,
TXOUTCLK => o_mgt.tx.TXOUTCLK, --TXOUTCLK_OUT,
TXOUTCLKPCS => open, --
TXRESET => i_mgt.tx.TXRESET, --tied_to_ground_i,
TXUSRCLK => i_mgt.tx.TXUSRCLK, --tied_to_ground_i,
TXUSRCLK2 => i_mgt.tx.TXUSRCLK2, --TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL => "100", --
TXDIFFCTRL => i_mgt.tx.TXDIFFCTRL, --TXDIFFCTRL_IN,
TXINHIBIT => tied_to_ground_i, --
TXN => o_mgt.tx.TXP, --TXN_OUT,
TXP => o_mgt.tx.TXN, --TXP_OUT,
TXPOSTEMPHASIS => i_mgt.tx.TXPOSTEMPHASIS, --TXPOSTEMPHASIS_IN,
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS => i_mgt.tx.TXPREEMPHASIS, --TXPREEMPHASIS_IN,
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => open,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE => tied_to_vcc_i, --
TXDLYALIGNMONENB => tied_to_ground_i, --
TXDLYALIGNMONITOR => open, --
TXDLYALIGNOVERRIDE => tied_to_ground_i, --
TXDLYALIGNRESET => tied_to_ground_i, --
TXDLYALIGNUPDSW => tied_to_vcc_i, --
TXENPMAPHASEALIGN => tied_to_ground_i, --
TXPMASETPHASE => tied_to_ground_i, --
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX => '0', --
GTXTXRESET => i_mgt.ctrl.GTXRESET, --GTXTXRESET_IN,
MGTREFCLKTX => slv_mgtrefclk, --MGTREFCLKTX_IN,
NORTHREFCLKTX => "00", --
PERFCLKTX => '0', --
PLLTXRESET => i_mgt.ctrl.PLLTXRESET, --PLLTXRESET_IN,
SOUTHREFCLKTX => "00", --
TXPLLLKDET => o_mgt.ctrl.TXPLLLKDET, --TXPLLLKDET_OUT,
TXPLLLKDETEN => '1', --
TXPLLPOWERDOWN => '0', --
TXPLLREFSELDY => "000", --
TXRATE => "00", --
TXRATEDONE => open, --
TXRESETDONE => o_mgt.ctrl.TXRESETDONE, --TXRESETDONE_OUT,
--------------------- Transmit Ports - TX PRBS Generator ------------------- --
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0), --
TXPRBSFORCEERR => tied_to_ground_i, --
-------------------- Transmit Ports - TX Polarity Control ------------------ --
TXPOLARITY => tied_to_ground_i, --
----------------- Transmit Ports - TX Ports for PCI Express ---------------- --
TXDEEMPH => tied_to_ground_i, --
TXDETECTRX => tied_to_ground_i, --
TXELECIDLE => tied_to_ground_i, --
TXMARGIN => tied_to_ground_vec_i(2 downto 0), --
TXPDOWNASYNCH => tied_to_ground_i, --
TXSWING => tied_to_ground_i, --
--------------------- Transmit Ports - TX Ports for SATA ------------------- --
COMFINISH => open, --
TXCOMINIT => tied_to_ground_i, --
TXCOMSAS => tied_to_ground_i, --
TXCOMWAKE => tied_to_ground_i --
);
end RTL;

746
hdl/pkg_v6vlx_gtxe1.vhd → hdl/v6vlx_gtxe1_142MHz8_2Gbps856.vhd
View File

@ -1,218 +1,26 @@
------------------------------------------------------------------------------
-- Paul Scherrer Institute (PSI)
------------------------------------------------------------------------------
-- Unit : pkg_v6vlx_gtxe1.vhd
-- Unit : v6vlx_gtxe1_142MHz8_2Gbps856.vhd
-- Author : Goran Marinkovic, Section Diagnostic
-- : Waldemar Koprek, Section Diagnostic
-- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright© PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment :
-- Comment : Virtex-6 GTXE1 primitive configured for SwissFEL 142.8 MHz
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
package pkg_v6vlx_gtxe1 is
library unisim;
use unisim.vcomponents.all;
---------------------------------------------------------------------------
-- Types
---------------------------------------------------------------------------
type gtxe_ctrl_in_type is record
GTXRESET : std_ulogic;
LOOPBACK : std_logic_vector( 2 downto 0);
CLKIN : std_ulogic;
PLLRXRESET : std_ulogic;
PLLTXRESET : std_ulogic;
end record gtxe_ctrl_in_type;
use work.v6vlx_gtxe1_pkg.all;
type gtxe_ctrl_out_type is record
RXPLLLKDET : std_ulogic;
RXRESETDONE : std_ulogic;
TXPLLLKDET : std_ulogic;
TXRESETDONE : std_ulogic;
REFCLKOUT : std_ulogic;
end record gtxe_ctrl_out_type;
-- type mgt_drp_in_type is record
-- -- Dynamic Reconfiguration Port (DRP)
-- DCLK : std_ulogic;
-- DEN : std_ulogic;
-- DWE : std_ulogic;
-- DADDR : std_logic_vector( 6 downto 0);
-- DI : std_logic_vector(15 downto 0);
-- end record mgt_drp_in_type;
--
-- type mgt_drp_out_type is record
-- -- Dynamic Reconfiguration Port (DRP)
-- DO : std_logic_vector(15 downto 0);
-- DRDY : std_ulogic;
-- end record mgt_drp_out_type;
type gtxe_rx_in_type is record
-- Comma Detection and Alignment ------------------------
RXENMCOMMAALIGN : std_ulogic;
RXENPCOMMAALIGN : std_ulogic;
-- RX resets
RXRESET : std_ulogic;
RXCDRRESET : std_ulogic;
-- RX user clocks
RXUSRCLK : std_ulogic;
RXUSRCLK2 : std_ulogic;
-- RX serial ports
RXP : std_ulogic;
RXN : std_ulogic;
-- RX Elastic Buffer and Phase Alignment Ports
RXDLYALIGNDISABLE : std_logic;
RXDLYALIGNMONENB : std_logic;
RXDLYALIGNOVERRIDE : std_logic;
RXDLYALIGNRESET : std_logic;
RXENPMAPHASEALIGN : std_logic;
RXPMASETPHASE : std_logic;
RXSLIDE : std_logic;
end record gtxe_rx_in_type;
type gtxe_rx_out_type is record
-- RX 8b10b Decoder
RXCHARISCOMMA : std_logic_vector( 3 downto 0);
RXCHARISK : std_logic_vector( 3 downto 0);
RXDISPERR : std_logic_vector( 3 downto 0);
RXNOTINTABLE : std_logic_vector( 3 downto 0);
RXRUNDISP : std_logic_vector( 3 downto 0);
-- Comma Detection and Alignment
RXBYTEISALIGNED : std_ulogic;
RXBYTEREALIGN : std_ulogic;
RXCOMMADET : std_ulogic;
-- RX data ports
RXDATA : std_logic_vector(31 downto 0);
-- RX user clocks
RXRECCLK : std_ulogic;
-- RX Out Of Band (OOB)
RXELECIDLE : std_ulogic;
-- RX Elastic Buffer and Phase Alignment Ports
RXDLYALIGNMONITOR : std_logic_vector(7 downto 0);
-- RX loss of sync fsm
RXLOSSOFSYNC : std_logic_vector( 1 downto 0);
end record gtxe_rx_out_type;
type gtxe_tx_in_type is record
-- 8b10b Encoder Control Ports
TXBYPASS8B10B : std_logic_vector( 3 downto 0);
TXCHARDISPMODE : std_logic_vector( 3 downto 0);
TXCHARDISPVAL : std_logic_vector( 3 downto 0);
TXCHARISK : std_logic_vector( 3 downto 0);
-- TX data ports
TXDATA : std_logic_vector(31 downto 0);
-- TX resets
TXRESET : std_ulogic;
-- TX user clocks
TXUSRCLK : std_ulogic;
TXUSRCLK2 : std_ulogic;
-- TX driver
TXDIFFCTRL : std_logic_vector( 3 downto 0);
TXPOSTEMPHASIS : std_logic_vector( 4 downto 0);
TXPREEMPHASIS : std_logic_vector( 3 downto 0);
end record gtxe_tx_in_type;
type gtxe_tx_out_type is record
-- TX serial ports
TXP : std_ulogic;
TXN : std_ulogic;
-- TX 8b10b encoder
TXKERR : std_logic_vector( 3 downto 0);
TXRUNDISP : std_logic_vector( 3 downto 0);
-- TX user clocks
TXOUTCLK : std_ulogic;
end record gtxe_tx_out_type;
type gtxe_in_type is record
ctrl : gtxe_ctrl_in_type;
--drp : mgt_drp_in_type;
rx : gtxe_rx_in_type;
tx : gtxe_tx_in_type;
end record gtxe_in_type;
type gtxe_out_type is record
ctrl : gtxe_ctrl_out_type;
--drp : mgt_drp_out_type;
rx : gtxe_rx_out_type;
tx : gtxe_tx_out_type;
end record gtxe_out_type;
---------------------------------------------------------------------------
-- Module virtex6 GTXE
---------------------------------------------------------------------------
component v6vlx_gtxe1
generic(
g_MGT_LOCATION : string
);
port
(
i_mgt : in gtxe_in_type;
o_mgt : out gtxe_out_type
);
end component;
component virtex6_gtxe_sync is
port
(
RXENPMAPHASEALIGN : out std_logic;
RXPMASETPHASE : out std_logic;
RXDLYALIGNDISABLE : out std_logic;
RXDLYALIGNOVERRIDE : out std_logic;
RXDLYALIGNRESET : out std_logic;
SYNC_DONE : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end component;
component v6vlx_gtxe1_wrapper is
generic(
g_MGT_LOCATION : string;
g_USE_MMCM : boolean := false
);
port
(
-- MGT serial interface
i_mgt_refclk : in std_logic;
o_mgt_refclk : out std_logic;
i_mgt_rx_p : in std_logic;
i_mgt_rx_n : in std_logic;
o_mgt_tx_p : out std_logic;
o_mgt_tx_n : out std_logic;
-- MGT parallel interface
o_mgt_status : out std_logic_vector(31 downto 0); -- see lines 134-139 for details
i_mgt_control : in std_logic_vector(31 downto 0); -- see lines 127-131 for details
o_mgt_recclk : out std_logic;
o_mgt_rx_data : out std_logic_vector(15 downto 0);
o_mgt_rx_charisk : out std_logic_vector( 1 downto 0)
);
end component;
end package pkg_v6vlx_gtxe1;
-------------------------------------------------------------------------------
-- virtex6_gtxe --------------------------------------------------------------
-------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library ieee;
use ieee.std_logic_1164.all;
use work.pkg_v6vlx_gtxe1.all;
entity v6vlx_gtxe1 is
entity v6vlx_gtxe1_142MHz8_2Gbps856 is
generic(
g_MGT_LOCATION : string
);
@ -220,9 +28,10 @@ entity v6vlx_gtxe1 is
i_mgt : in gtxe_in_type;
o_mgt : out gtxe_out_type
);
end v6vlx_gtxe1;
end v6vlx_gtxe1_142MHz8_2Gbps856;
architecture RTL of v6vlx_gtxe1 is
architecture RTL of v6vlx_gtxe1_142MHz8_2Gbps856 is
--**************************** Signal Declarations ****************************
@ -258,8 +67,8 @@ begin
gtxe1_i :GTXE1
generic map (
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => TRUE,
SIM_GTXRESET_SPEEDUP => 1, --(GTX_SIM_GTXRESET_SPEEDUP),
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_GTXRESET_SPEEDUP => (1), --(GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
@ -281,39 +90,39 @@ begin
POWER_SAVE => "0000110100", -- [4] '1' = bypass trasmit delay aligner, [5] '1' = bypass receive delay aligner
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => TRUE, --(TRUE),
TX_DATA_WIDTH => 20, --(20),
TX_USRCLK_CFG => X"00", --(x"00"),
TXOUTCLK_CTRL => "TXOUTCLKPMA_DIV2", --("TXOUTCLKPMA_DIV2"),
TXOUTCLK_DLY => "0000000000", --("0000000000"),
GEN_TXUSRCLK => (TRUE), --
TX_DATA_WIDTH => (20), --
TX_USRCLK_CFG => (X"00"), --
TXOUTCLK_CTRL => ("TXOUTCLKPMA_DIV2"), --
TXOUTCLK_DLY => ("0000000000"), --
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => '0', --('0'),
PMA_TX_CFG => x"80082", --(x"80082"),
TX_BUFFER_USE => TRUE, --(TRUE),
TX_BYTECLK_CFG => x"00", --(x"00"),
TX_EN_RATE_RESET_BUF => TRUE, --(TRUE),
TX_XCLK_SEL => "TXOUT", --("TXOUT"),
TX_DLYALIGN_CTRINC => "0100", --("0100"),
TX_DLYALIGN_LPFINC => "0110", --("0110"),
TX_DLYALIGN_MONSEL => "000", --("000"),
TX_DLYALIGN_OVRDSETTING => "10000000", --("10000000"),
TX_PMADATA_OPT => ('0'), --
PMA_TX_CFG => (x"80082"), --
TX_BUFFER_USE => (TRUE), --
TX_BYTECLK_CFG => (x"00"), --
TX_EN_RATE_RESET_BUF => (TRUE), --
TX_XCLK_SEL => ("TXOUT"), --
TX_DLYALIGN_CTRINC => ("0100"), --
TX_DLYALIGN_LPFINC => ("0110"), --
TX_DLYALIGN_MONSEL => ("000"), --
TX_DLYALIGN_OVRDSETTING => ("10000000"), --
-------------------------TX Gearbox--------------------------- --
-------------------------TX Gearbox--------------------------- --
GEARBOX_ENDEC => ("000"), --
TXGEARBOX_USE => (FALSE), --
--
----------------TX Driver and OOB Signalling------------------ --
----------------TX Driver and OOB Signalling------------------ --
TX_DRIVE_MODE => ("DIRECT"), --
TX_IDLE_ASSERT_DELAY => ("100"), --
TX_IDLE_DEASSERT_DELAY => ("010"), --
TXDRIVE_LOOPBACK_HIZ => (FALSE), --
TXDRIVE_LOOPBACK_PD => (FALSE), --
--
--------------TX Pipe Control for PCI Express/SATA------------ --
--------------TX Pipe Control for PCI Express/SATA------------ --
COM_BURST_VAL => ("1111"), --
--
------------------TX Attributes for PCI Express--------------- --
------------------TX Attributes for PCI Express--------------- --
TX_DEEMPH_0 => ("11010"), --
TX_DEEMPH_1 => ("10000"), --
TX_MARGIN_FULL_0 => ("1001110"), --
@ -346,7 +155,7 @@ begin
RXUSRCLK_DLY => (x"0000"), --
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => FALSE, --(FALSE),
AC_CAP_DIS => (FALSE), --
CDR_PH_ADJ_TIME => ("10100"), --
OOBDETECT_THRESHOLD => ("011"), --
PMA_CDR_SCAN => (x"640404C"), --
@ -354,10 +163,10 @@ begin
RCV_TERM_GND => (FALSE), --
RCV_TERM_VTTRX => (TRUE), --
RX_EN_IDLE_HOLD_CDR => (FALSE), --
RX_EN_IDLE_RESET_FR => FALSE, --(FALSE),
RX_EN_IDLE_RESET_PH => FALSE, --(FALSE),
RX_EN_IDLE_RESET_FR => (FALSE), --
RX_EN_IDLE_RESET_PH => (FALSE), --
TX_DETECT_RX_CFG => (x"1832"), --
TERMINATION_CTRL => "00000", --("00000"),
TERMINATION_CTRL => ("00000"), --
TERMINATION_OVRD => (FALSE), --
CM_TRIM => ("01"), --
PMA_RXSYNC_CFG => (x"00"), --
@ -376,11 +185,11 @@ begin
RXPRBSERR_LOOPBACK => ('0'), --
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => 2, --(1),
ALIGN_COMMA_WORD => (2), --(1),
COMMA_10B_ENABLE => ("1111111111"), --
COMMA_DOUBLE => (FALSE), --
DEC_MCOMMA_DETECT => TRUE, --(FALSE),
DEC_PCOMMA_DETECT => TRUE, --(FALSE),
DEC_MCOMMA_DETECT => (TRUE), --(FALSE),
DEC_PCOMMA_DETECT => (TRUE), --(FALSE),
DEC_VALID_COMMA_ONLY => (FALSE), --
MCOMMA_10B_VALUE => ("1010000011"), --
MCOMMA_DETECT => (TRUE), --
@ -389,12 +198,12 @@ begin
RX_DECODE_SEQ_MATCH => (FALSE), --
RX_SLIDE_AUTO_WAIT => (5), --
RX_SLIDE_MODE => ("PMA"), --
SHOW_REALIGN_COMMA => (FALSE), --
SHOW_REALIGN_COMMA => (FALSE), --
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (8), --
RX_LOS_THRESHOLD => (128), --
RX_LOSS_OF_SYNC_FSM => TRUE, --(FALSE),
RX_LOSS_OF_SYNC_FSM => (TRUE), --(FALSE),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (FALSE), --
@ -416,7 +225,7 @@ begin
RX_DLYALIGN_MONSEL => ("000"), --
RX_DLYALIGN_OVRDSETTING => ("10000000"), --
------------------------Clock Correction---------------------- --
------------------------Clock Correction---------------------- --
CLK_COR_ADJ_LEN => (1), --
CLK_COR_DET_LEN => (1), --
CLK_COR_INSERT_IDLE_FLAG => (FALSE), --
@ -438,7 +247,7 @@ begin
CLK_COR_SEQ_2_USE => (FALSE), --
CLK_CORRECT_USE => (FALSE), --
--
------------------------Channel Bonding---------------------- --
------------------------Channel Bonding---------------------- --
CHAN_BOND_1_MAX_SKEW => (1), --
CHAN_BOND_2_MAX_SKEW => (1), --
CHAN_BOND_KEEP_ALIGN => (FALSE), --
@ -457,7 +266,7 @@ begin
CHAN_BOND_SEQ_LEN => (1), --
PCI_EXPRESS_MODE => (FALSE), --
--
-------------RX Attributes for PCI Express/SATA/SAS---------- --
-------------RX Attributes for PCI Express/SATA/SAS---------- --
SAS_MAX_COMSAS => (52), --
SAS_MIN_COMSAS => (40), --
SATA_BURST_VAL => ("100"), --
@ -682,473 +491,4 @@ begin
TXCOMWAKE => tied_to_ground_i --
);
end RTL;
-------------------------------------------------------------------------------
-- virtex6_gtxe_sync-----------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity virtex6_gtxe_sync is
port
(
RXENPMAPHASEALIGN : out std_logic;
RXPMASETPHASE : out std_logic;
RXDLYALIGNDISABLE : out std_logic;
RXDLYALIGNOVERRIDE : out std_logic;
RXDLYALIGNRESET : out std_logic;
SYNC_DONE : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end virtex6_gtxe_sync;
architecture RTL of virtex6_gtxe_sync is
--***********************************Parameter Declarations********************
constant DLY : time := 1 ns;
--*******************************Register Declarations************************
signal begin_r : std_logic;
signal phase_align_r : std_logic;
signal ready_r : std_logic;
signal sync_counter_r : unsigned(5 downto 0);
signal sync_done_count_r : unsigned(5 downto 0);
signal align_reset_counter_r : unsigned(4 downto 0);
signal wait_after_sync_r : std_logic;
signal wait_before_setphase_counter_r : unsigned(5 downto 0);
signal wait_before_setphase_r : std_logic;
signal align_reset_r : std_logic;
--*******************************Wire Declarations****************************
signal count_32_setphase_complete_r : std_logic;
signal count_32_wait_complete_r : std_logic;
signal count_align_reset_complete_r : std_logic;
signal next_phase_align_c : std_logic;
signal next_align_reset_c : std_logic;
signal next_ready_c : std_logic;
signal next_wait_after_sync_c : std_logic;
signal next_wait_before_setphase_c : std_logic;
signal sync_32_times_done_r : std_logic;
attribute max_fanout:string;
attribute max_fanout of ready_r : signal is "2";
begin
--*******************************Main Body of Code****************************
--________________________________ State machine __________________________
-- This state machine manages the phase alingment procedure of the GTX on the
-- receive side. The module is held in reset till the usrclk source is stable
-- and RXRESETDONE is asserted. In the case that a MMCM is used to generate
-- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.
-- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes
-- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles.
-- After this, it goes into the wait_before_setphase_r state for 32 cycles.
-- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the
-- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles.
-- After the port is deasserted, the state machine goes into a wait state for
-- 32 cycles. This procedure is repeated 32 times.
-- State registers
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(RESET='1') then
begin_r <= '1' after DLY;
align_reset_r <= '0' after DLY;
wait_before_setphase_r <= '0' after DLY;
phase_align_r <= '0' after DLY;
wait_after_sync_r <= '0' after DLY;
ready_r <= '0' after DLY;
else
begin_r <= '0' after DLY;
align_reset_r <= next_align_reset_c after DLY;
wait_before_setphase_r <= next_wait_before_setphase_c after DLY;
phase_align_r <= next_phase_align_c after DLY;
wait_after_sync_r <= next_wait_after_sync_c after DLY;
ready_r <= next_ready_c after DLY;
end if;
end if;
end process;
-- Next state logic
next_align_reset_c <= begin_r or
(align_reset_r and not count_align_reset_complete_r);
next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or
(wait_before_setphase_r and not count_32_wait_complete_r);
next_phase_align_c <= (wait_before_setphase_r and count_32_wait_complete_r) or
(phase_align_r and not count_32_setphase_complete_r) or
(wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);
next_wait_after_sync_c <= (phase_align_r and count_32_setphase_complete_r) or
(wait_after_sync_r and not count_32_wait_complete_r);
next_ready_c <= (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or
ready_r;
--______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if (align_reset_r='0') then
align_reset_counter_r <= (others=>'0') after DLY;
else
align_reset_counter_r <= align_reset_counter_r + 1 after DLY;
end if;
end if ;
end process;
count_align_reset_complete_r <= align_reset_counter_r(4)
and align_reset_counter_r(2);
--_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then
wait_before_setphase_counter_r <= (others=>'0') after DLY;
else
wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;
end if;
end if;
end process;
count_32_wait_complete_r <= wait_before_setphase_counter_r(5);
--_______________ Counter for holding SYNC for SYNC_CYCLES ________________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if (phase_align_r='0') then
sync_counter_r <= (others=>'0') after DLY;
else
sync_counter_r <= sync_counter_r + 1 after DLY;
end if;
end if;
end process;
count_32_setphase_complete_r <= sync_counter_r(5);
--__________ Counter for counting number of times sync is done ____________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if (RESET='1') then
sync_done_count_r <= (others=>'0') after DLY;
elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then
sync_done_count_r <= sync_done_count_r + 1 after DLY;
end if;
end if;
end process;
sync_32_times_done_r <= sync_done_count_r(5);
--_______________ Assign the phase align ports into the GTX _______________
RXDLYALIGNRESET <= align_reset_r;
RXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);
RXPMASETPHASE <= phase_align_r;
RXDLYALIGNDISABLE <= '1';
RXDLYALIGNOVERRIDE <= '1';
--_______________________ Assign the sync_done port _______________________
SYNC_DONE <= ready_r;
end RTL;
-------------------------------------------------------------------------------
-- ioxos_mgt_v1 ---------------------------------------------------------------
-------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.pkg_v6vlx_gtxe1.all;
entity v6vlx_gtxe1_wrapper is
generic(
g_MGT_LOCATION : string;
g_USE_MMCM : boolean := false
);
port(
-- MGT serial interface
i_mgt_refclk : in std_logic;
o_mgt_refclk : out std_logic;
i_mgt_rx_p : in std_logic;
i_mgt_rx_n : in std_logic;
o_mgt_tx_p : out std_logic;
o_mgt_tx_n : out std_logic;
-- MGT parallel interface
o_mgt_status : out std_logic_vector(31 downto 0); -- see lines 134-139 for details
i_mgt_control : in std_logic_vector(31 downto 0); -- see lines 127-131 for details
o_mgt_recclk : out std_logic;
o_mgt_rx_data : out std_logic_vector(15 downto 0);
o_mgt_rx_charisk : out std_logic_vector( 1 downto 0)
);
end v6vlx_gtxe1_wrapper;
architecture RTL of v6vlx_gtxe1_wrapper is
type typ_align_fsm is (
align_idle,
align_slide ,
align_wait_for_sync
);
signal s_align_fsm : typ_align_fsm := align_idle;
-- GTXE
signal i_mgt : gtxe_in_type;
signal o_mgt : gtxe_out_type;
signal sl_txoutclk : std_logic;
--fifo
signal sl_cpu_rx_empty : std_logic;
signal sl_gtxe_fifo_rst : std_logic;
signal sl_gtxe_rx_sync_done : std_logic;
signal slv_rxresetdone : std_logic_vector(7 downto 0);
signal sl_rx_sync_rst : std_logic;
signal sl_rxrecclk : std_logic;
signal sl_rx0_slide : std_logic;
signal slv_cnt : std_logic_vector(5 downto 0);
-- MMCM
signal mmcm_CLKFB : std_logic;
signal mmcm_CLKFBOUT : std_logic;
signal mmcm_LOCKED : std_logic;
signal mmcm_RESET : std_logic;
signal mmcm_CLOCK : std_logic;
begin
-- inst_mgt_refclk_bufg: BUFG
-- port map
-- (
-- I => o_mgt.ctrl.REFCLKOUT,
-- O => o_mgt_refclk
-- );
-- GTXE INSTANCE ------------------------------------------------------------------
ins_v6vlx_gtxe1: v6vlx_gtxe1
generic map (
g_MGT_LOCATION => g_MGT_LOCATION )
port map (
i_mgt => i_mgt,
o_mgt => o_mgt
);
-- GTXE CONTROL IF ----------------------------------------------------------------
i_mgt.ctrl.GTXRESET <= i_mgt_control(0);
i_mgt.ctrl.PLLRXRESET <= '0';
i_mgt.ctrl.PLLTXRESET <= '0';
i_mgt.ctrl.LOOPBACK <= "100"; -- Far-End PMA Loopback --> UG366 page 125
i_mgt.ctrl.CLKIN <= i_mgt_refclk;
-- GTXE STATUS IF (adapted to PSI generic part) -----------------------------------
o_mgt_status( 0) <= o_mgt.ctrl.TXPLLLKDET;
o_mgt_status( 1) <= o_mgt.ctrl.RXPLLLKDET;
o_mgt_status( 2) <= mmcm_LOCKED;
o_mgt_status( 3) <= o_mgt.ctrl.TXRESETDONE;
o_mgt_status( 4) <= o_mgt.ctrl.RXRESETDONE;
o_mgt_status( 5) <= '0'; -- TX_polarity inverted
o_mgt_status( 6) <= '0'; -- RX_polarity inverted
o_mgt_status( 7) <= '0'; -- reserved
o_mgt_status(12 downto 8) <= "00000"; -- DFEEYEDACMON[4:0]
o_mgt_status(13) <= '0'; -- RXPRBSERR
o_mgt_status(14) <= o_mgt.rx.RXBYTEISALIGNED;
o_mgt_status(15) <= o_mgt.rx.RXLOSSOFSYNC(1);
---------- additional status -------------
o_mgt_status(16) <= sl_rx0_slide;
o_mgt_status(17) <= sl_gtxe_rx_sync_done;
o_mgt_status(19 downto 18) <= o_mgt.rx.RXNOTINTABLE(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(21 downto 20) <= o_mgt.rx.RXDISPERR(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(31 downto 22) <= B"00_0000_0000"; -- undefined
-- GTXE RX IF ---------------------------------------------------------------------
-- MMCM use model based on AR#39430
gen_MMCM: if g_USE_MMCM generate
begin
-- Use Core Generator to define parameters -> actual frequency 142.8 MHz
mmcm_rxclk : MMCM_BASE
generic map (
CLKFBOUT_MULT_F => 33.000 , -- Counter multiply value, Now supports non-integer values
CLKIN1_PERIOD => 7.002 , -- The reference clock frequency is required for properly configuring the
-- LOCK detect circuit and checking to make sure the VCO is operating within
-- the allowed range. If no value is specified, a warning should be issued
-- stating it was not provided so no error checking will be done.
CLKOUT0_DIVIDE_F => 8.250 , -- Counter divide value, Now supports non-integer values but you lose CLKOUT5
DIVCLK_DIVIDE => 4 -- Counter divide value, always configured for 50% duty cycle
)
port map (
CLKFBOUT => mmcm_CLKFBOUT, -- 1-bit MMCM Feedback clock output
CLKFBOUTB => open, -- 1-bit Inverted MMCM feedback clock output
CLKOUT0 => mmcm_CLOCK, -- 1-bit MMCM clock output 0
CLKOUT0B => open, -- 1-bit Inverted MMCM clock output 0
CLKOUT1 => open, -- 1-bit MMCM clock output 1
CLKOUT1B => open, -- 1-bit Inverted MMCM clock output 1
CLKOUT2 => open, -- 1-bit MMCM clock output 2
CLKOUT2B => open, -- 1-bit Inverted MMCM clock output 2
CLKOUT3 => open, -- 1-bit MMCM clock output 3
CLKOUT3B => open, -- 1-bit Inverted MMCM clock output 3
CLKOUT4 => open, -- 1-bit MMCM clock output 4
CLKOUT5 => open, -- 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer
CLKOUT6 => open, -- 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer
LOCKED => mmcm_LOCKED, -- 1-bit MMC locked signal
CLKFBIN => mmcm_CLKFB, -- 1-bit Feedback clock pin to the MMCM
CLKIN1 => o_mgt.rx.RXRECCLK, -- 1-bit Reference clock pin 1 to the MMCM
PWRDWN => '0', -- 1-bit Power down
RST => mmcm_RESET -- 1-bit MMCM global reset pin
);
mmcm_RESET <= not o_mgt.ctrl.RXPLLLKDET;
rxoutCLKFB_bufg0_i : BUFG
port map (
I => mmcm_CLKFBOUT,
O => mmcm_CLKFB
);
rxoutclk_bufg1_i : BUFG
port map (
I => mmcm_CLOCK,
O => sl_rxrecclk
);
end generate;
gen_BUFG: if not(g_USE_MMCM) generate
begin
rxoutclk_bufg0_i : BUFG
port map (
I => o_mgt.rx.RXRECCLK,
O => sl_rxrecclk
);
-- forward lock state
mmcm_LOCKED <= o_mgt.ctrl.RXPLLLKDET;
-- unused without mmcm
mmcm_CLKFB <= '0';
mmcm_CLKFBOUT <= '0';
mmcm_RESET <= '0';
mmcm_CLOCK <= '0';
end generate;
o_mgt_recclk <= sl_rxrecclk;
ins_virtex6_gtxe_sync : virtex6_gtxe_sync
port map (
RXENPMAPHASEALIGN => i_mgt.rx.RXENPMAPHASEALIGN ,
RXPMASETPHASE => i_mgt.rx.RXPMASETPHASE ,
RXDLYALIGNDISABLE => i_mgt.rx.RXDLYALIGNDISABLE ,
RXDLYALIGNOVERRIDE => i_mgt.rx.RXDLYALIGNOVERRIDE,
RXDLYALIGNRESET => i_mgt.rx.RXDLYALIGNRESET ,
SYNC_DONE => sl_gtxe_rx_sync_done,
USER_CLK => sl_rxrecclk,
RESET => sl_rx_sync_rst
);
prc_rx_reset_done_delay : process ( sl_rxrecclk )
begin
if rising_edge( sl_rxrecclk ) then
slv_rxresetdone <= slv_rxresetdone(6 downto 0) & o_mgt.ctrl.RXRESETDONE;
end if;
end process ;
sl_rx_sync_rst <= not slv_rxresetdone(7);
i_mgt.rx.RXUSRCLK <= sl_rxrecclk;
i_mgt.rx.RXUSRCLK2 <= sl_rxrecclk;
i_mgt.rx.RXP <= i_mgt_rx_p;
i_mgt.rx.RXN <= i_mgt_rx_n;
i_mgt.rx.RXENMCOMMAALIGN <= '0';
i_mgt.rx.RXENPCOMMAALIGN <= '0';
i_mgt.rx.RXRESET <= not mmcm_LOCKED;
i_mgt.rx.RXCDRRESET <= i_mgt_control(5);
i_mgt.rx.RXDLYALIGNMONENB <= '0';
o_mgt_rx_data <= o_mgt.rx.RXDATA(15 downto 0);
o_mgt_rx_charisk <= o_mgt.rx.RXCHARISK( 1 downto 0);
------------------------------------------------------------------------------
--RX comma alignment
------------------------------------------------------------------------------
prc_comma_align : process ( sl_rxrecclk )
begin
if rising_edge( sl_rxrecclk ) then
if o_mgt.ctrl.RXRESETDONE = '0' then
s_align_fsm <= align_idle;
else
case s_align_fsm is
when align_idle =>
if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' then
s_align_fsm <= align_slide;
end if;
when align_slide =>
slv_cnt <= (others => '0');
s_align_fsm <= align_wait_for_sync;
when align_wait_for_sync =>
if slv_cnt(slv_cnt'left) = '1' then
if o_mgt.rx.RXLOSSOFSYNC( 1) = '0' and o_mgt.rx.RXBYTEISALIGNED = '1' then
s_align_fsm <= align_idle;
else
s_align_fsm <= align_slide;
end if;
else
slv_cnt <= slv_cnt + X"1";
end if;
end case;
end if;
end if;
end process ;
sl_rx0_slide <= '1' when s_align_fsm = align_slide or i_mgt_control(2) = '1' else '0';
i_mgt.rx.RXSLIDE <= sl_rx0_slide;
-- GTXE TX IF ---------------------------------------------------------------------
o_mgt_tx_p <= o_mgt.tx.TXP;
o_mgt_tx_n <= o_mgt.tx.TXN;
-- txoutclk_bufg0_i : BUFG
-- port map (
-- I => o_mgt.tx.TXOUTCLK,
-- O => sl_txoutclk
-- );
i_mgt.tx.TXRESET <= not mmcm_LOCKED;
i_mgt.tx.TXBYPASS8B10B <= X"0";
i_mgt.tx.TXCHARDISPMODE <= X"0";
i_mgt.tx.TXCHARDISPVAL <= X"0";
i_mgt.tx.TXUSRCLK <= sl_rxrecclk;
i_mgt.tx.TXUSRCLK2 <= sl_rxrecclk;
i_mgt.tx.TXDIFFCTRL <= "0110";
i_mgt.tx.TXPOSTEMPHASIS <= "00000";
i_mgt.tx.TXPREEMPHASIS <= "0000";
end RTL;

207
hdl/v6vlx_gtxe1_pkg.vhd Normal file
View File

@ -0,0 +1,207 @@
------------------------------------------------------------------------------
-- Paul Scherrer Institute (PSI)
------------------------------------------------------------------------------
-- Unit : v6vlx_gtxe1_pkg.vhd
-- Author : Goran Marinkovic, Section Diagnostic
-- : Waldemar Koprek, Section Diagnostic
-- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright<68> PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment :
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package v6vlx_gtxe1_pkg is
---------------------------------------------------------------------------
-- Types
---------------------------------------------------------------------------
type gtxe_ctrl_in_type is record
GTXRESET : std_ulogic;
LOOPBACK : std_logic_vector( 2 downto 0);
CLKIN : std_ulogic;
PLLRXRESET : std_ulogic;
PLLTXRESET : std_ulogic;
end record gtxe_ctrl_in_type;
type gtxe_ctrl_out_type is record
RXPLLLKDET : std_ulogic;
RXRESETDONE : std_ulogic;
TXPLLLKDET : std_ulogic;
TXRESETDONE : std_ulogic;
REFCLKOUT : std_ulogic;
end record gtxe_ctrl_out_type;
-- type mgt_drp_in_type is record
-- -- Dynamic Reconfiguration Port (DRP)
-- DCLK : std_ulogic;
-- DEN : std_ulogic;
-- DWE : std_ulogic;
-- DADDR : std_logic_vector( 6 downto 0);
-- DI : std_logic_vector(15 downto 0);
-- end record mgt_drp_in_type;
--
-- type mgt_drp_out_type is record
-- -- Dynamic Reconfiguration Port (DRP)
-- DO : std_logic_vector(15 downto 0);
-- DRDY : std_ulogic;
-- end record mgt_drp_out_type;
type gtxe_rx_in_type is record
-- Comma Detection and Alignment ------------------------
RXENMCOMMAALIGN : std_ulogic;
RXENPCOMMAALIGN : std_ulogic;
-- RX resets
RXRESET : std_ulogic;
RXCDRRESET : std_ulogic;
-- RX user clocks
RXUSRCLK : std_ulogic;
RXUSRCLK2 : std_ulogic;
-- RX serial ports
RXP : std_ulogic;
RXN : std_ulogic;
-- RX Elastic Buffer and Phase Alignment Ports
RXDLYALIGNDISABLE : std_logic;
RXDLYALIGNMONENB : std_logic;
RXDLYALIGNOVERRIDE : std_logic;
RXDLYALIGNRESET : std_logic;
RXENPMAPHASEALIGN : std_logic;
RXPMASETPHASE : std_logic;
RXSLIDE : std_logic;
end record gtxe_rx_in_type;
type gtxe_rx_out_type is record
-- RX 8b10b Decoder
RXCHARISCOMMA : std_logic_vector( 3 downto 0);
RXCHARISK : std_logic_vector( 3 downto 0);
RXDISPERR : std_logic_vector( 3 downto 0);
RXNOTINTABLE : std_logic_vector( 3 downto 0);
RXRUNDISP : std_logic_vector( 3 downto 0);
-- Comma Detection and Alignment
RXBYTEISALIGNED : std_ulogic;
RXBYTEREALIGN : std_ulogic;
RXCOMMADET : std_ulogic;
-- RX data ports
RXDATA : std_logic_vector(31 downto 0);
-- RX user clocks
RXRECCLK : std_ulogic;
-- RX Out Of Band (OOB)
RXELECIDLE : std_ulogic;
-- RX Elastic Buffer and Phase Alignment Ports
RXDLYALIGNMONITOR : std_logic_vector(7 downto 0);
-- RX loss of sync fsm
RXLOSSOFSYNC : std_logic_vector( 1 downto 0);
end record gtxe_rx_out_type;
type gtxe_tx_in_type is record
-- 8b10b Encoder Control Ports
TXBYPASS8B10B : std_logic_vector( 3 downto 0);
TXCHARDISPMODE : std_logic_vector( 3 downto 0);
TXCHARDISPVAL : std_logic_vector( 3 downto 0);
TXCHARISK : std_logic_vector( 3 downto 0);
-- TX data ports
TXDATA : std_logic_vector(31 downto 0);
-- TX resets
TXRESET : std_ulogic;
-- TX user clocks
TXUSRCLK : std_ulogic;
TXUSRCLK2 : std_ulogic;
-- TX driver
TXDIFFCTRL : std_logic_vector( 3 downto 0);
TXPOSTEMPHASIS : std_logic_vector( 4 downto 0);
TXPREEMPHASIS : std_logic_vector( 3 downto 0);
end record gtxe_tx_in_type;
type gtxe_tx_out_type is record
-- TX serial ports
TXP : std_ulogic;
TXN : std_ulogic;
-- TX 8b10b encoder
TXKERR : std_logic_vector( 3 downto 0);
TXRUNDISP : std_logic_vector( 3 downto 0);
-- TX user clocks
TXOUTCLK : std_ulogic;
end record gtxe_tx_out_type;
type gtxe_in_type is record
ctrl : gtxe_ctrl_in_type;
--drp : mgt_drp_in_type;
rx : gtxe_rx_in_type;
tx : gtxe_tx_in_type;
end record gtxe_in_type;
type gtxe_out_type is record
ctrl : gtxe_ctrl_out_type;
--drp : mgt_drp_out_type;
rx : gtxe_rx_out_type;
tx : gtxe_tx_out_type;
end record gtxe_out_type;
---------------------------------------------------------------------------
-- Components
---------------------------------------------------------------------------
component v6vlx_gtxe1_142MHz8_2Gbps856
generic(
g_MGT_LOCATION : string
);
port
(
i_mgt : in gtxe_in_type;
o_mgt : out gtxe_out_type
);
end component;
component v6vlx_gtxe1_101MHz27_1Gbps0127
generic(
g_MGT_LOCATION : string
);
port
(
i_mgt : in gtxe_in_type;
o_mgt : out gtxe_out_type
);
end component;
component v6vlx_gtxe1_sync is
port
(
RXENPMAPHASEALIGN : out std_logic;
RXPMASETPHASE : out std_logic;
RXDLYALIGNDISABLE : out std_logic;
RXDLYALIGNOVERRIDE : out std_logic;
RXDLYALIGNRESET : out std_logic;
SYNC_DONE : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end component;
component v6vlx_gtxe1_wrapper is
generic(
g_MGT_LOCATION : string;
g_USE_MMCM : boolean := false
);
port
(
-- MGT serial interface
i_mgt_refclk : in std_logic;
o_mgt_refclk : out std_logic;
i_mgt_rx_p : in std_logic;
i_mgt_rx_n : in std_logic;
o_mgt_tx_p : out std_logic;
o_mgt_tx_n : out std_logic;
-- MGT parallel interface
o_mgt_status : out std_logic_vector(31 downto 0); -- see lines 134-139 for details
i_mgt_control : in std_logic_vector(31 downto 0); -- see lines 127-131 for details
o_mgt_recclk : out std_logic;
o_mgt_rx_data : out std_logic_vector(15 downto 0);
o_mgt_rx_charisk : out std_logic_vector( 1 downto 0)
);
end component;
end package v6vlx_gtxe1_pkg;

191
hdl/v6vlx_gtxe1_sync.vhd Normal file
View File

@ -0,0 +1,191 @@
------------------------------------------------------------------------------
-- Paul Scherrer Institute (PSI)
------------------------------------------------------------------------------
-- Unit : v6vlx_gtxe1_sync.vhd
-- Author : Goran Marinkovic, Section Diagnostic
-- : Waldemar Koprek, Section Diagnostic
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright<68> PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment : GTX synchronisation and alignment process.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity v6vlx_gtxe1_sync is
port
(
RXENPMAPHASEALIGN : out std_logic;
RXPMASETPHASE : out std_logic;
RXDLYALIGNDISABLE : out std_logic;
RXDLYALIGNOVERRIDE : out std_logic;
RXDLYALIGNRESET : out std_logic;
SYNC_DONE : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end v6vlx_gtxe1_sync;
architecture RTL of v6vlx_gtxe1_sync is
--***********************************Parameter Declarations********************
constant DLY : time := 1 ns;
--*******************************Register Declarations************************
signal begin_r : std_logic;
signal phase_align_r : std_logic;
signal ready_r : std_logic;
signal sync_counter_r : unsigned(5 downto 0);
signal sync_done_count_r : unsigned(5 downto 0);
signal align_reset_counter_r : unsigned(4 downto 0);
signal wait_after_sync_r : std_logic;
signal wait_before_setphase_counter_r : unsigned(5 downto 0);
signal wait_before_setphase_r : std_logic;
signal align_reset_r : std_logic;
--*******************************Wire Declarations****************************
signal count_32_setphase_complete_r : std_logic;
signal count_32_wait_complete_r : std_logic;
signal count_align_reset_complete_r : std_logic;
signal next_phase_align_c : std_logic;
signal next_align_reset_c : std_logic;
signal next_ready_c : std_logic;
signal next_wait_after_sync_c : std_logic;
signal next_wait_before_setphase_c : std_logic;
signal sync_32_times_done_r : std_logic;
attribute max_fanout:string;
attribute max_fanout of ready_r : signal is "2";
begin
--*******************************Main Body of Code****************************
--________________________________ State machine __________________________
-- This state machine manages the phase alingment procedure of the GTX on the
-- receive side. The module is held in reset till the usrclk source is stable
-- and RXRESETDONE is asserted. In the case that a MMCM is used to generate
-- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.
-- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes
-- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles.
-- After this, it goes into the wait_before_setphase_r state for 32 cycles.
-- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the
-- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles.
-- After the port is deasserted, the state machine goes into a wait state for
-- 32 cycles. This procedure is repeated 32 times.
-- State registers
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if(RESET='1') then
begin_r <= '1' after DLY;
align_reset_r <= '0' after DLY;
wait_before_setphase_r <= '0' after DLY;
phase_align_r <= '0' after DLY;
wait_after_sync_r <= '0' after DLY;
ready_r <= '0' after DLY;
else
begin_r <= '0' after DLY;
align_reset_r <= next_align_reset_c after DLY;
wait_before_setphase_r <= next_wait_before_setphase_c after DLY;
phase_align_r <= next_phase_align_c after DLY;
wait_after_sync_r <= next_wait_after_sync_c after DLY;
ready_r <= next_ready_c after DLY;
end if;
end if;
end process;
-- Next state logic
next_align_reset_c <= begin_r or
(align_reset_r and not count_align_reset_complete_r);
next_wait_before_setphase_c <= (align_reset_r and count_align_reset_complete_r) or
(wait_before_setphase_r and not count_32_wait_complete_r);
next_phase_align_c <= (wait_before_setphase_r and count_32_wait_complete_r) or
(phase_align_r and not count_32_setphase_complete_r) or
(wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);
next_wait_after_sync_c <= (phase_align_r and count_32_setphase_complete_r) or
(wait_after_sync_r and not count_32_wait_complete_r);
next_ready_c <= (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or
ready_r;
--______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if (align_reset_r='0') then
align_reset_counter_r <= (others=>'0') after DLY;
else
align_reset_counter_r <= align_reset_counter_r + 1 after DLY;
end if;
end if ;
end process;
count_align_reset_complete_r <= align_reset_counter_r(4)
and align_reset_counter_r(2);
--_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then
wait_before_setphase_counter_r <= (others=>'0') after DLY;
else
wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;
end if;
end if;
end process;
count_32_wait_complete_r <= wait_before_setphase_counter_r(5);
--_______________ Counter for holding SYNC for SYNC_CYCLES ________________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if (phase_align_r='0') then
sync_counter_r <= (others=>'0') after DLY;
else
sync_counter_r <= sync_counter_r + 1 after DLY;
end if;
end if;
end process;
count_32_setphase_complete_r <= sync_counter_r(5);
--__________ Counter for counting number of times sync is done ____________
process( USER_CLK )
begin
if(USER_CLK'event and USER_CLK = '1') then
if (RESET='1') then
sync_done_count_r <= (others=>'0') after DLY;
elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then
sync_done_count_r <= sync_done_count_r + 1 after DLY;
end if;
end if;
end process;
sync_32_times_done_r <= sync_done_count_r(5);
--_______________ Assign the phase align ports into the GTX _______________
RXDLYALIGNRESET <= align_reset_r;
RXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);
RXPMASETPHASE <= phase_align_r;
RXDLYALIGNDISABLE <= '1';
RXDLYALIGNOVERRIDE <= '1';
--_______________________ Assign the sync_done port _______________________
SYNC_DONE <= ready_r;
end RTL;

308
hdl/v6vlx_gtxe1_wrapper.vhd Normal file
View File

@ -0,0 +1,308 @@
------------------------------------------------------------------------------
-- Paul Scherrer Institute (PSI)
------------------------------------------------------------------------------
-- Unit : v6vlx_gtxe1_wrapper.vhd
-- Author : Goran Marinkovic, Section Diagnostic
-- : Waldemar Koprek, Section Diagnostic
-- : Patric Bucher, Section DSV
-- Version : $Revision: 1.1 $
------------------------------------------------------------------------------
-- Copyright<68> PSI, Section Diagnostic
------------------------------------------------------------------------------
-- Comment : Wrapper vor Virtex-6 GTX ready to use in HIPA and SwissFEL (SFEL)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
use work.v6vlx_gtxe1_pkg.all;
entity v6vlx_gtxe1_wrapper is
generic(
g_MGT_LOCATION : string; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string -- "HIPA" | "SFEL"
);
port(
-- MGT serial interface
i_mgt_refclk : in std_logic;
o_mgt_refclk : out std_logic;
i_mgt_rx_p : in std_logic;
i_mgt_rx_n : in std_logic;
o_mgt_tx_p : out std_logic;
o_mgt_tx_n : out std_logic;
-- MGT parallel interface
o_mgt_status : out std_logic_vector(31 downto 0); -- see lines 134-139 for details
i_mgt_control : in std_logic_vector(31 downto 0); -- see lines 127-131 for details
o_mgt_recclk : out std_logic;
o_mgt_rx_data : out std_logic_vector(15 downto 0);
o_mgt_rx_charisk : out std_logic_vector( 1 downto 0)
);
end v6vlx_gtxe1_wrapper;
architecture RTL of v6vlx_gtxe1_wrapper is
type typ_align_fsm is (
align_idle,
align_slide ,
align_wait_for_sync
);
signal s_align_fsm : typ_align_fsm := align_idle;
-- GTXE
signal i_mgt : gtxe_in_type;
signal o_mgt : gtxe_out_type;
signal sl_txoutclk : std_logic;
--fifo
signal sl_cpu_rx_empty : std_logic;
signal sl_gtxe_fifo_rst : std_logic;
signal sl_gtxe_rx_sync_done : std_logic;
signal slv_rxresetdone : std_logic_vector(7 downto 0);
signal sl_rx_sync_rst : std_logic;
signal sl_rxrecclk : std_logic;
signal sl_rx0_slide : std_logic;
signal slv_cnt : std_logic_vector(5 downto 0);
-- MMCM
signal mmcm_CLKFB : std_logic;
signal mmcm_CLKFBOUT : std_logic;
signal mmcm_LOCKED : std_logic;
signal mmcm_RESET : std_logic;
signal mmcm_CLOCK : std_logic;
begin
-- inst_mgt_refclk_bufg: BUFG
-- port map
-- (
-- I => o_mgt.ctrl.REFCLKOUT,
-- O => o_mgt_refclk
-- );
-- GTXE INSTANCE ------------------------------------------------------------------
gen_gtxe1_sfel: if g_FACILITY = "SFEL" generate
ins_v6vlx_gtxe1_sfel: entity work.v6vlx_gtxe1_142MHz8_2Gbps856
generic map (
g_MGT_LOCATION => g_MGT_LOCATION )
port map (
i_mgt => i_mgt,
o_mgt => o_mgt
);
end generate;
gen_gtxe1_hipa: if g_FACILITY = "HIPA" generate
ins_v6vlx_gtxe1_hipa: entity work.v6vlx_gtxe1_101MHz27_1Gbps0127
generic map (
g_MGT_LOCATION => g_MGT_LOCATION )
port map (
i_mgt => i_mgt,
o_mgt => o_mgt
);
end generate;
assert not(g_FACILITY /= "HIPA" and g_FACILITY /= "SFEL")
report "Invalid value for g_FACILITY, valid values are 'HIPA'|'SFEL'"
severity failure;
-- GTXE CONTROL IF ----------------------------------------------------------------
i_mgt.ctrl.GTXRESET <= i_mgt_control(0);
i_mgt.ctrl.PLLRXRESET <= '0';
i_mgt.ctrl.PLLTXRESET <= '0';
i_mgt.ctrl.LOOPBACK <= "100"; -- Far-End PMA Loopback --> UG366 page 125
i_mgt.ctrl.CLKIN <= i_mgt_refclk;
-- GTXE STATUS IF (adapted to PSI generic part) -----------------------------------
o_mgt_status( 0) <= o_mgt.ctrl.TXPLLLKDET;
o_mgt_status( 1) <= o_mgt.ctrl.RXPLLLKDET;
o_mgt_status( 2) <= mmcm_LOCKED;
o_mgt_status( 3) <= o_mgt.ctrl.TXRESETDONE;
o_mgt_status( 4) <= o_mgt.ctrl.RXRESETDONE;
o_mgt_status( 5) <= '0'; -- TX_polarity inverted
o_mgt_status( 6) <= '0'; -- RX_polarity inverted
o_mgt_status( 7) <= '0'; -- reserved
o_mgt_status(12 downto 8) <= "00000"; -- DFEEYEDACMON[4:0]
o_mgt_status(13) <= '0'; -- RXPRBSERR
o_mgt_status(14) <= o_mgt.rx.RXBYTEISALIGNED;
o_mgt_status(15) <= o_mgt.rx.RXLOSSOFSYNC(1);
---------- additional status -------------
o_mgt_status(16) <= sl_rx0_slide;
o_mgt_status(17) <= sl_gtxe_rx_sync_done;
o_mgt_status(19 downto 18) <= o_mgt.rx.RXNOTINTABLE(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(21 downto 20) <= o_mgt.rx.RXDISPERR(1 downto 0); -- Byte 1 + Byte 0
o_mgt_status(31 downto 22) <= B"00_0000_0000"; -- undefined
-- GTXE RX IF ---------------------------------------------------------------------
-- MMCM use model based on AR#39430
gen_MMCM: if g_FACILITY = "SFEL" generate
begin
-- Use Core Generator to define parameters -> actual frequency 142.8 MHz
mmcm_rxclk : MMCM_BASE
generic map (
CLKFBOUT_MULT_F => 33.000 , -- Counter multiply value, Now supports non-integer values
CLKIN1_PERIOD => 7.002 , -- The reference clock frequency is required for properly configuring the
-- LOCK detect circuit and checking to make sure the VCO is operating within
-- the allowed range. If no value is specified, a warning should be issued
-- stating it was not provided so no error checking will be done.
CLKOUT0_DIVIDE_F => 8.250 , -- Counter divide value, Now supports non-integer values but you lose CLKOUT5
DIVCLK_DIVIDE => 4 -- Counter divide value, always configured for 50% duty cycle
)
port map (
CLKFBOUT => mmcm_CLKFBOUT, -- 1-bit MMCM Feedback clock output
CLKFBOUTB => open, -- 1-bit Inverted MMCM feedback clock output
CLKOUT0 => mmcm_CLOCK, -- 1-bit MMCM clock output 0
CLKOUT0B => open, -- 1-bit Inverted MMCM clock output 0
CLKOUT1 => open, -- 1-bit MMCM clock output 1
CLKOUT1B => open, -- 1-bit Inverted MMCM clock output 1
CLKOUT2 => open, -- 1-bit MMCM clock output 2
CLKOUT2B => open, -- 1-bit Inverted MMCM clock output 2
CLKOUT3 => open, -- 1-bit MMCM clock output 3
CLKOUT3B => open, -- 1-bit Inverted MMCM clock output 3
CLKOUT4 => open, -- 1-bit MMCM clock output 4
CLKOUT5 => open, -- 1-bit MMCM clock output 5, not used if CLKOUT0 is not an integer
CLKOUT6 => open, -- 1-bit MMCM clock output 6, not used if CLKFBOUT_MULT is not an integer
LOCKED => mmcm_LOCKED, -- 1-bit MMC locked signal
CLKFBIN => mmcm_CLKFB, -- 1-bit Feedback clock pin to the MMCM
CLKIN1 => o_mgt.rx.RXRECCLK, -- 1-bit Reference clock pin 1 to the MMCM
PWRDWN => '0', -- 1-bit Power down
RST => mmcm_RESET -- 1-bit MMCM global reset pin
);
mmcm_RESET <= not o_mgt.ctrl.RXPLLLKDET;
rxoutCLKFB_bufg0_i : BUFG
port map (
O => mmcm_CLKFB,
I => mmcm_CLKFBOUT
);
rxoutclk_bufg1_i : BUFG
port map (
O => sl_rxrecclk,
I => mmcm_CLOCK
);
end generate;
gen_BUFG: if g_FACILITY = "HIPA" generate
begin
rxoutclk_bufg0_i : BUFG
port map (
O => sl_rxrecclk,
I => o_mgt.rx.RXRECCLK
);
-- forward lock state
mmcm_LOCKED <= o_mgt.ctrl.RXPLLLKDET;
-- unused without mmcm
mmcm_CLKFB <= '0';
mmcm_CLKFBOUT <= '0';
mmcm_RESET <= '0';
mmcm_CLOCK <= '0';
end generate;
o_mgt_recclk <= sl_rxrecclk;
ins_v6vlx_gtxe1_sync : entity work.v6vlx_gtxe1_sync
port map (
RXENPMAPHASEALIGN => i_mgt.rx.RXENPMAPHASEALIGN ,
RXPMASETPHASE => i_mgt.rx.RXPMASETPHASE ,
RXDLYALIGNDISABLE => i_mgt.rx.RXDLYALIGNDISABLE ,
RXDLYALIGNOVERRIDE => i_mgt.rx.RXDLYALIGNOVERRIDE,
RXDLYALIGNRESET => i_mgt.rx.RXDLYALIGNRESET ,
SYNC_DONE => sl_gtxe_rx_sync_done,
USER_CLK => sl_rxrecclk,
RESET => sl_rx_sync_rst
);
prc_rx_reset_done_delay : process ( sl_rxrecclk )
begin
if rising_edge( sl_rxrecclk ) then
slv_rxresetdone <= slv_rxresetdone(6 downto 0) & o_mgt.ctrl.RXRESETDONE;
end if;
end process ;
sl_rx_sync_rst <= not slv_rxresetdone(7);
i_mgt.rx.RXUSRCLK <= sl_rxrecclk;
i_mgt.rx.RXUSRCLK2 <= sl_rxrecclk;
i_mgt.rx.RXP <= i_mgt_rx_p;
i_mgt.rx.RXN <= i_mgt_rx_n;
i_mgt.rx.RXENMCOMMAALIGN <= '0';
i_mgt.rx.RXENPCOMMAALIGN <= '0';
i_mgt.rx.RXRESET <= not mmcm_LOCKED;
i_mgt.rx.RXCDRRESET <= i_mgt_control(5);
i_mgt.rx.RXDLYALIGNMONENB <= '0';
o_mgt_rx_data <= o_mgt.rx.RXDATA(15 downto 0);
o_mgt_rx_charisk <= o_mgt.rx.RXCHARISK( 1 downto 0);
------------------------------------------------------------------------------
--RX comma alignment
------------------------------------------------------------------------------
prc_comma_align : process ( sl_rxrecclk )
begin
if rising_edge( sl_rxrecclk ) then
if o_mgt.ctrl.RXRESETDONE = '0' then
s_align_fsm <= align_idle;
else
case s_align_fsm is
when align_idle =>
if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' then
s_align_fsm <= align_slide;
end if;
when align_slide =>
slv_cnt <= (others => '0');
s_align_fsm <= align_wait_for_sync;
when align_wait_for_sync =>
if slv_cnt(slv_cnt'left) = '1' then
if o_mgt.rx.RXLOSSOFSYNC( 1) = '0' and o_mgt.rx.RXBYTEISALIGNED = '1' then
s_align_fsm <= align_idle;
else
s_align_fsm <= align_slide;
end if;
else
slv_cnt <= slv_cnt + X"1";
end if;
end case;
end if;
end if;
end process ;
sl_rx0_slide <= '1' when s_align_fsm = align_slide or i_mgt_control(2) = '1' else '0';
i_mgt.rx.RXSLIDE <= sl_rx0_slide;
-- GTXE TX IF ---------------------------------------------------------------------
o_mgt_tx_p <= o_mgt.tx.TXP;
o_mgt_tx_n <= o_mgt.tx.TXN;
-- txoutclk_bufg0_i : BUFG
-- port map (
-- I => o_mgt.tx.TXOUTCLK,
-- O => sl_txoutclk
-- );
i_mgt.tx.TXRESET <= not mmcm_LOCKED;
i_mgt.tx.TXBYPASS8B10B <= X"0";
i_mgt.tx.TXCHARDISPMODE <= X"0";
i_mgt.tx.TXCHARDISPVAL <= X"0";
i_mgt.tx.TXUSRCLK <= sl_rxrecclk;
i_mgt.tx.TXUSRCLK2 <= sl_rxrecclk;
i_mgt.tx.TXDIFFCTRL <= "0110";
i_mgt.tx.TXPOSTEMPHASIS <= "00000";
i_mgt.tx.TXPREEMPHASIS <= "0000";
end RTL;

6
sim/config.tcl
View File

@ -20,7 +20,11 @@ add_sources $LibPath/Libraries/VHDL/evr320/hdl {
# IFC1210 Bindings
add_sources $LibPath/Libraries/VHDL/evr320/hdl {
pkg_v6vlx_gtxe1.vhd \
v6vlx_gtxe1_pkg.vhd \
v6vlx_gtxe1_101MHz27_1Gbps0127.vhd \
v6vlx_gtxe1_142MHz8_2Gbps856.vhd \
v6vlx_gtxe1_sync.vhd \
v6vlx_gtxe1_wrapper.vhd \
evr320_tmem.vhd \
evr320_ifc1210_wrapper.vhd \
} -tag evr320_ifc1210