AEK_8220_Libraries/firmware_vhdl_evr320
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DEVEL: removed usage of lib ieee.std_logic_unsigned

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This commit is contained in:
bucher_p1
2019-10-21 11:05:34 +02:00
parent b171096b8a
commit c846a32902
7 changed files with 90 additions and 89 deletions
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32
hdl/evr320_buffer.vhd
View File

@ -11,7 +11,7 @@
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
@ -89,7 +89,7 @@ begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(page_addr_clka & addra)) := dia;
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra)))) := dia;
end if;
end if;
end if;
@ -99,10 +99,10 @@ begin
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(23 downto 16) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(31 downto 24) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00"))));
dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01"))));
dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10"))));
dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11"))));
end if;
end if;
end process;
@ -117,9 +117,9 @@ begin
if (ena = '1') then
if (wea = '1') then
if (addra(0) = '1') then
RAM_ODD (conv_integer(page_addr_clka & addra(addra'high downto 1))) := dia;
RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clka & addra(addra'high downto 1))))) := dia;
else
RAM_EVEN(conv_integer(page_addr_clka & addra(addra'high downto 1))) := dia;
RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra(addra'high downto 1))))) := dia;
end if;
end if;
end if;
@ -130,14 +130,14 @@ begin
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(23 downto 16) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(31 downto 24) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(39 downto 32) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(47 downto 40) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(55 downto 48) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob(63 downto 56) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00"))));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00"))));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01"))));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01"))));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10"))));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10"))));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11"))));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11"))));
end if;
end if;
end process;

60
hdl/evr320_decoder.vhd
View File

@ -12,7 +12,7 @@
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
@ -94,9 +94,9 @@ architecture behavioral of evr320_decoder is
-- Events received
type usr_events_type is array (0 to 3) of std_logic_vector( 3 downto 0);
signal usr_events : usr_events_type := (others => (others => '0'));
signal cs_timeout_cnt : std_logic_vector(23 downto 0) := (others => '0');
signal cs_min_cnt : std_logic_vector(31 downto 0) := (others => '0');
signal cs_min_time : std_logic_vector(31 downto 0) := (others => '0');
signal cs_timeout_cnt : unsigned(23 downto 0) := (others => '0');
signal cs_min_cnt : unsigned(31 downto 0) := (others => '0');
signal cs_min_time : unsigned(31 downto 0) := (others => '0');
signal evr_stable : std_logic := '0';
-- Frame fsm
@ -124,7 +124,7 @@ architecture behavioral of evr320_decoder is
constant frame_chk2 : std_logic_vector( 3 downto 0) := "1000";
signal frame_fsm : std_logic_vector( 3 downto 0) := "0000";
-- Frame checksum
signal frame_chk : std_logic_vector(15 downto 0) := X"FFFF";
signal frame_chk : unsigned(15 downto 0) := X"FFFF";
signal frame_chk_ok : std_logic := '0';
signal frame_chk1_ok : std_logic := '0';
signal frame_chk2_ok : std_logic := '0';
@ -149,8 +149,8 @@ architecture behavioral of evr320_decoder is
signal frame_data_rden : std_logic := '0';
signal frame_data_do : std_logic_vector(63 downto 0) := (others => '0');
-- Frame data FIFO write port
signal frame_data_wr_id : std_logic_vector( 7 downto 0) := (others => '0');
signal frame_data_wr_addr_cnt: std_logic_vector(15 downto 0) := (others => '0');
signal frame_data_wr_id : unsigned( 7 downto 0) := (others => '0');
signal frame_data_wr_addr_cnt: unsigned(15 downto 0) := (others => '0');
signal frame_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
signal frame_data_wr_byte : std_logic_vector( 7 downto 0) := (others => '0');
-- Frame data FIFO read port
@ -189,16 +189,16 @@ architecture behavioral of evr320_decoder is
signal usr_events_save_dly : std_logic := '0';
signal usr_events_nr : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_nr_dly : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_addr : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_addr : unsigned( 7 downto 0) := (others => '0');
signal usr_events_addr_dly : std_logic_vector( 7 downto 0) := (others => '0');
signal usr_events_cnt : std_logic_vector( 31 downto 0) := (others => '0');
signal usr_events_cnt_d : std_logic_vector( 31 downto 0) := (others => '0');
signal usr_events_cnt : unsigned( 31 downto 0) := (others => '0');
signal usr_events_cnt_d : unsigned( 31 downto 0) := (others => '0');
signal all_events_flags : std_logic_vector(255 downto 0) := (others => '0');
signal all_events_flags_d : std_logic_vector(255 downto 0) := (others => '0');
signal all_events_flags_sync1 : std_logic_vector(255 downto 0) := (others => '0');
signal all_events_flags_sync2 : std_logic_vector(255 downto 0) := (others => '0');
signal timestamp_cnt : std_logic_vector( 31 downto 0) := (others => '0');
signal timestamp_cnt_dly : std_logic_vector( 31 downto 0) := (others => '0');
signal timestamp_cnt : unsigned( 31 downto 0) := (others => '0');
signal timestamp_cnt_dly : unsigned( 31 downto 0) := (others => '0');
signal segment_addr_wren : std_logic;
signal mem_data_valid : std_logic;
signal mem_data_error : std_logic;
@ -253,14 +253,14 @@ begin
debug( 65) <= usr_events_save_dly;
debug( 73 downto 66) <= usr_events_nr_dly;
debug( 81 downto 74) <= usr_events_addr_dly;
debug(113 downto 82) <= timestamp_cnt_dly;
debug(113 downto 82) <= std_logic_vector(timestamp_cnt_dly);
debug(114) <= segment_addr_wren;
debug(115) <= mem_data_valid;
debug(116) <= mem_data_error;
debug(117) <= mem_data_read_ack(0);
debug(118) <= mem_data_error_ack(0);
debug(119) <= all_events_flags(27); -- event code 27 (photonics)
debug(127 downto 120) <= usr_events_cnt(7 downto 0);
debug(127 downto 120) <= std_logic_vector(usr_events_cnt(7 downto 0));
end generate dbg_evt_rec;
dbg_no_evt_rec: if not(EVENT_RECORDER) generate
@ -293,7 +293,9 @@ begin
if (i_mgt_rst = '1') then
evr_stable <= '0';
else
if ((cs_min_cnt > i_evr_params.cs_min_cnt) and (cs_min_time > i_evr_params.cs_min_time) and (cs_timeout_cnt < X"15CA20")) then
if ((std_logic_vector(cs_min_cnt) > i_evr_params.cs_min_cnt) and
(std_logic_vector(cs_min_time) > i_evr_params.cs_min_time) and
(std_logic_vector(cs_timeout_cnt) < X"15CA20")) then
evr_stable <= '1';
else
evr_stable <= '0';
@ -455,7 +457,7 @@ begin
frame_data_wr_addr_cnt <= (others => '0');
when frame_addr =>
frame_data_wr_id <= frame_data_wr_id + X"01";
frame_data_wr_addr_cnt <= "0000" & i_mgt_rx_data(15 downto 8) & "0000";
frame_data_wr_addr_cnt <= "0000" & unsigned(i_mgt_rx_data(15 downto 8)) & "0000";
segment_addr_wren <= '1';
when frame_data =>
if (((i_mgt_rx_charisk( 1) = '1') and (i_mgt_rx_data(15 downto 8) = C_KCHAR_END)) or
@ -464,7 +466,7 @@ begin
else
frame_data_wren <= not frame_data_full;
frame_data_wr_addr_cnt <= frame_data_wr_addr_cnt + X"0001";
frame_data_wr_addr <= frame_data_wr_addr_cnt(10 downto 0);
frame_data_wr_addr <= std_logic_vector(frame_data_wr_addr_cnt(10 downto 0));
frame_data_wr_byte <= i_mgt_rx_data(15 downto 8);
end if;
when others =>
@ -485,7 +487,7 @@ begin
frame_chk <= X"FFFF";
when frame_addr | frame_data =>
if (i_mgt_rx_charisk = "00") then
frame_chk <= frame_chk - (X"00" & i_mgt_rx_data(15 downto 8));
frame_chk <= frame_chk - (X"00" & unsigned(i_mgt_rx_data(15 downto 8)));
end if;
when others =>
null;
@ -501,11 +503,11 @@ begin
frame_chk1_ok <= '0';
frame_chk2_ok <= '0';
when frame_chk1 =>
if (frame_chk(15 downto 8) = i_mgt_rx_data(15 downto 8)) then
if (frame_chk(15 downto 8) = unsigned(i_mgt_rx_data(15 downto 8))) then
frame_chk1_ok <= '1';
end if;
when frame_chk2 =>
if (frame_chk( 7 downto 0) = i_mgt_rx_data(15 downto 8)) then
if (frame_chk( 7 downto 0) = unsigned(i_mgt_rx_data(15 downto 8))) then
frame_chk2_ok <= '1';
end if;
when others =>
@ -531,7 +533,7 @@ begin
end if;
end process;
frame_ctrl_wr_id <= frame_data_wr_id;
frame_ctrl_wr_id <= std_logic_vector(frame_data_wr_id);
frame_ctrl_wr_ok <= frame_chk_ok;
frame_ctrl_di( 7 downto 0) <= frame_ctrl_wr_id;
@ -593,7 +595,7 @@ begin
frame_ctrl_rd_ok <= frame_ctrl_do( 8);
-- Frame data received
frame_data_di( 7 downto 0) <= frame_data_wr_id;
frame_data_di( 7 downto 0) <= std_logic_vector(frame_data_wr_id);
frame_data_di(18 downto 8) <= frame_data_wr_addr;
frame_data_di(23 downto 19) <= "00000";
frame_data_di(31 downto 24) <= frame_data_wr_byte;
@ -960,7 +962,7 @@ begin
end if;
-- set flag for appeared event
all_events_flags(conv_integer(i_mgt_rx_data(7 downto 0))) <= '1';
all_events_flags(to_integer(unsigned(i_mgt_rx_data(7 downto 0)))) <= '1';
end if;
end if;
@ -977,7 +979,7 @@ begin
timestamp_cnt_dly <= timestamp_cnt;
usr_events_save_dly <= usr_events_save;
usr_events_nr_dly <= usr_events_nr;
usr_events_addr_dly <= usr_events_addr;
usr_events_addr_dly <= std_logic_vector(usr_events_addr);
end if;
end process;
@ -1075,8 +1077,8 @@ begin
clka => i_mgt_rx_clk,
ena => HIGH,
wea => segment_addr_wren,
addra => frame_data_wr_addr_cnt(10 downto 4),
dia => timestamp_cnt,
addra => std_logic_vector(frame_data_wr_addr_cnt(10 downto 4)),
dia => std_logic_vector(timestamp_cnt),
page => sos_event(3),
-- port b
clkb => i_usr_clk,
@ -1101,7 +1103,7 @@ begin
ena => HIGH,
wea => usr_events_save_dly,
addra => usr_events_addr_dly,
dia => timestamp_cnt_dly,
dia => std_logic_vector(timestamp_cnt_dly),
page => sos_event(3),
-- port b
clkb => i_usr_clk,
@ -1147,7 +1149,7 @@ begin
all_events_flags_sync2 <= all_events_flags_sync1;
-- address fragment of vector / expand bit to bytes for data read
v_addr := conv_integer(mem_addr(5 downto MEM_ADDR_LSB) & LOW_slv(1 + MEM_ADDR_LSB downto 0));
v_addr := to_integer(unsigned(std_logic_vector'(mem_addr(5 downto MEM_ADDR_LSB) & LOW_slv(1 + MEM_ADDR_LSB downto 0))));
mem_data_event_flag <= bit2byte(all_events_flags_sync2(v_addr + MEM_DATA_BYTES - 1 downto v_addr));
end if;
end process;
@ -1157,7 +1159,7 @@ begin
-- port mapping
--------------------------------------------------------------------------
o_sos_event <= sos_event(3);
o_event_recorder_stat.usr_events_counter <= usr_events_cnt_d;
o_event_recorder_stat.usr_events_counter <= std_logic_vector(usr_events_cnt_d);
o_event_recorder_stat.data_valid <= mem_data_valid;
o_event_recorder_stat.data_error <= mem_data_error;

32
hdl/evr320_dpram.vhd
View File

@ -11,7 +11,7 @@
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity evr320_dpram is
@ -59,7 +59,7 @@ begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) := dia;
RAM(to_integer(unsigned(addra))) := dia;
end if;
end if;
end if;
@ -69,10 +69,10 @@ begin
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM(conv_integer(addrb & "00"));
dob(15 downto 8) <= RAM(conv_integer(addrb & "01"));
dob(23 downto 16) <= RAM(conv_integer(addrb & "10"));
dob(31 downto 24) <= RAM(conv_integer(addrb & "11"));
dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "00"))));
dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "01"))));
dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "10"))));
dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(addrb & "11"))));
end if;
end if;
end process;
@ -87,9 +87,9 @@ begin
if (ena = '1') then
if (wea = '1') then
if (addra(0) = '1') then
RAM_ODD (conv_integer(addra(addra'high downto 1))) := dia;
RAM_ODD (to_integer(unsigned(addra(addra'high downto 1)))) := dia;
else
RAM_EVEN(conv_integer(addra(addra'high downto 1))) := dia;
RAM_EVEN(to_integer(unsigned(addra(addra'high downto 1)))) := dia;
end if;
end if;
end if;
@ -100,14 +100,14 @@ begin
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(conv_integer(addrb & "00"));
dob(15 downto 8) <= RAM_ODD (conv_integer(addrb & "00"));
dob(23 downto 16) <= RAM_EVEN(conv_integer(addrb & "01"));
dob(31 downto 24) <= RAM_ODD (conv_integer(addrb & "01"));
dob(39 downto 32) <= RAM_EVEN(conv_integer(addrb & "10"));
dob(47 downto 40) <= RAM_ODD (conv_integer(addrb & "10"));
dob(55 downto 48) <= RAM_EVEN(conv_integer(addrb & "11"));
dob(63 downto 56) <= RAM_ODD (conv_integer(addrb & "11"));
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "00"))));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "00"))));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "01"))));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "01"))));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "10"))));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "10"))));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(addrb & "11"))));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(addrb & "11"))));
end if;
end if;
end process;

1
hdl/evr320_ifc1210_wrapper.vhd
View File

@ -10,7 +10,6 @@
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
library tosca2;

42
hdl/evr320_timestamp.vhd
View File

@ -11,7 +11,7 @@
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
@ -95,10 +95,10 @@ begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM(conv_integer(page_addr_clka & addra & "00")) := dia( 7 downto 0);
RAM(conv_integer(page_addr_clka & addra & "01")) := dia(15 downto 8);
RAM(conv_integer(page_addr_clka & addra & "10")) := dia(23 downto 16);
RAM(conv_integer(page_addr_clka & addra & "11")) := dia(31 downto 24);
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "00")))) := dia( 7 downto 0);
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "01")))) := dia(15 downto 8);
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "10")))) := dia(23 downto 16);
RAM(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & "11")))) := dia(31 downto 24);
end if;
end if;
end if;
@ -108,10 +108,10 @@ begin
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(23 downto 16) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(31 downto 24) <= RAM(conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob( 7 downto 0) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00"))));
dob(15 downto 8) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01"))));
dob(23 downto 16) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10"))));
dob(31 downto 24) <= RAM(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11"))));
end if;
end if;
end process;
@ -125,10 +125,10 @@ begin
if rising_edge(clka) then
if (ena = '1') then
if (wea = '1') then
RAM_EVEN(conv_integer(page_addr_clka & addra & '0')) := dia( 7 downto 0);
RAM_ODD (conv_integer(page_addr_clka & addra & '0')) := dia(15 downto 8);
RAM_EVEN(conv_integer(page_addr_clka & addra & '1')) := dia(23 downto 16);
RAM_ODD (conv_integer(page_addr_clka & addra & '1')) := dia(31 downto 24);
RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '0')))) := dia( 7 downto 0);
RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '0')))) := dia(15 downto 8);
RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '1')))) := dia(23 downto 16);
RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clka & addra & '1')))) := dia(31 downto 24);
end if;
end if;
end if;
@ -138,14 +138,14 @@ begin
begin
if rising_edge(clkb) then
if (enb = '1') then
dob( 7 downto 0) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(15 downto 8) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "00"));
dob(23 downto 16) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(31 downto 24) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "01"));
dob(39 downto 32) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(47 downto 40) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "10"));
dob(55 downto 48) <= RAM_EVEN(conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob(63 downto 56) <= RAM_ODD (conv_integer(page_addr_clkb( 3) & addrb & "11"));
dob( 7 downto 0) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00"))));
dob(15 downto 8) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "00"))));
dob(23 downto 16) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01"))));
dob(31 downto 24) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "01"))));
dob(39 downto 32) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10"))));
dob(47 downto 40) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "10"))));
dob(55 downto 48) <= RAM_EVEN(to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11"))));
dob(63 downto 56) <= RAM_ODD (to_integer(unsigned(std_logic_vector'(page_addr_clkb( 3) & addrb & "11"))));
end if;
end if;
end process;

8
hdl/evr320_tmem.vhd
View File

@ -10,7 +10,6 @@
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
@ -54,6 +53,7 @@ architecture rtl of evr320_tmem is
-- Constants
-- ---------------------------------------------------------------------------
constant reserved : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
constant c_LOW : std_logic_vector(63 downto 0) := X"0000_0000_0000_0000";
constant NUM_REG64 : integer := 16;
constant TMEM_ADDR_LSB : integer := 3; -- 64 bit
constant REG_ADDR_WIDTH : integer := integer(ceil(log2(real(NUM_REG64)))) + TMEM_ADDR_LSB;
@ -146,7 +146,7 @@ begin
begin
if (rising_edge(xuser_CLK)) then
if (xuser_TMEM_ENA_reg = '1') then
if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0) then
if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
@ -180,7 +180,7 @@ begin
er_error_ack <= er_error_ack(2 downto 0) & '0';
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = 0) then
if (xuser_TMEM_ENA_reg = '1' and xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"0" then --ByteAddr 000
-- if xuser_TMEM_WE_reg(0) = '1' then -read only- <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
@ -246,7 +246,7 @@ begin
-- Port mapping
-- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK;
mem_addr_o <= xuser_TMEM_ADD - MEM_ADDR_START;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;

4
hdl/v6vlx_gtxe1_wrapper.vhd
View File

@ -13,7 +13,7 @@
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
@ -68,7 +68,7 @@ architecture RTL of v6vlx_gtxe1_wrapper is
signal sl_rx0_slide : std_logic;
signal slv_cnt : std_logic_vector(5 downto 0);
signal slv_cnt : unsigned(5 downto 0);
-- MMCM
signal mmcm_CLKFB : std_logic;