AEK_8220_Libraries/firmware_vhdl_evr320
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extended ifc1210_wrapper with data streaming port and replaced frequency

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measurement by common lib
This commit is contained in:
purtschert_j
2018-12-04 21:13:51 +01:00
parent 84440ce6a0
commit d7e669cb75
3 changed files with 26 additions and 20 deletions
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2
hdl/evr320_decoder.vhd
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@ -54,7 +54,7 @@ entity evr320_decoder is
-- User stream interface User clock
--------------------------------------------------------------------------
i_stream_clk : in std_logic;
o_stream_data : out std_logic_vector(11+8-1 downto 0); -- | byte-address (12bit) | data buffer (8bit) |
o_stream_data : out std_logic_vector(18 downto 0); -- | addr 11bit | data 8bit |
o_stream_valid : out std_logic;
--------------------------------------------------------------------------
-- User interface MGT clock

43
hdl/evr320_ifc1210_wrapper.vhd
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@ -24,7 +24,8 @@ entity evr320_ifc1210_wrapper is
generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false -- enable/disable Event Recorder functionality
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz
);
port(
tick1sec_i : in std_logic;
@ -61,6 +62,12 @@ entity evr320_ifc1210_wrapper is
usr_events_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with one clock cycle length
usr_events_ext_o : out std_logic_vector( 3 downto 0); -- User defined event pulses with four clock cycle length
sos_event_o : out std_logic -- Start-of-Sequence Event
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(18 downto 0); -- | addr 11bit | data 8bit |
stream_valid_o : out std_logic;
);
end evr320_ifc1210_wrapper;
@ -103,8 +110,6 @@ architecture rtl of evr320_ifc1210_wrapper is
signal event_recorder_control_sync : typ_evt_rec_ctrl;
signal event_recorder_control_xuser : typ_evt_rec_ctrl;
signal evr_counter_rst : std_logic_vector( 2 downto 0) := (others => '0');
signal evr_clk_counter : std_logic_vector(31 downto 0) := (others => '0');
signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0');
signal debug_data : std_logic_vector(127 downto 0);
@ -179,6 +184,10 @@ begin
i_event_recorder_ctrl => event_recorder_control,
i_mem_addr => mem_addr_evr,
o_mem_data => mem_data,
-- user stream interface, user clock
i_stream_clk => stream_clk_i,
o_stream_data => stream_data_o,
o_stream_valid => stream_valid_o,
-- User interface MGT clock
o_usr_events => usr_events_o,
o_usr_events_ext => usr_events_ext_o,
@ -235,24 +244,20 @@ begin
mem_data_i => mem_data
);
-- --------------------------------------------------------------------------
-- Measure EVR Clock (based on xuser_CLK)
-- --------------------------------------------------------------------------
prc_count_cycles: process(clk_evr)
begin
if rising_edge(clk_evr) then
if (evr_counter_rst(2 downto 1) = "01") then
evr_frequency <= evr_clk_counter;
evr_clk_counter <= (others => '0');
else
evr_clk_counter <= evr_clk_counter + X"0000_0001";
end if;
-- sync reset and detect edge
evr_counter_rst <= evr_counter_rst(1 downto 0) & tick1sec_i;
end if;
end process;
clock_meas_inst : entity work.psi_common_clk_meas
generic map (
MasterFrequency_g => g_XUSER_CLK_FREQ,
MaxMeasFrequency_g => 150000000
);
port map (
ClkMaster => xuser_CLK,
Rst => xuser_RST,
ClkTest => clk_evr,
FrequencyHz => evr_frequency
);
-- --------------------------------------------------------------------------
-- port mapping
@ -266,4 +271,4 @@ begin
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------

1
sim/config.tcl
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@ -47,6 +47,7 @@ add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
psi_common_sdp_ram.vhd \
psi_common_pulse_cc.vhd \
psi_common_async_fifo.vhd \
psi_common_clk_meas.vhd \
} -tag psi_common
# tosca2_glb_pkg dependency