added data filter from decoder stream

hdl/evr320_data_filter.vhd

@@ -0,0 +1,67 @@
+------------------------------------------------------------------------------
+--  Copyright (c) 2018 by Paul Scherrer Institute, Switzerland
+--  All rights reserved.
+--  Project:      evr320
+--  Authors:      Jonas Purtschert
+--  Description:  Filter a specific data field from data buffer stream of the decoder:
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_1164.all;
+
+entity evr320_data_filter is
+  generic (
+    ADDRESS   : std_logic_vector(10 downto 0);
+    NUM_BYTES : integer := 8
+  );
+  port (
+    -- User stream interface
+    i_stream_clk        : in    std_logic;                          -- user clock
+    i_stream_data       : in    std_logic_vector(11+8-1 downto 0);  -- | byte-address (12bit) | data buffer (8bit) |
+    i_stream_valid      : in    std_logic;
+    -- filter output:
+    o_data              : out   std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
+    o_valid             : out   std_logic := '0'
+  );
+end evr320_data_filter;
+
+
+architecture behavioral of evr320_data_filter is
+
+  signal data_shift : std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
+  signal match : std_logic := '0';
+  signal shift_cnt : integer range 0 to NUM_BYTES;
+
+begin
+  process(i_stream_clk)
+    variable addr : std_logic_vector(10 downto 0) := (others=>'0');
+    variable data : std_logic_vector(7 downto 0) := (others=>'0');
+  begin
+     if (rising_edge(i_stream_clk)) then
+       o_valid <= '0';
+
+       if (i_stream_valid = '1') then
+         addr := i_stream_data(i_stream_data'high downto 8);
+         data := i_stream_data(7 downto 0);
+
+         if (addr = ADDRESS or match = '1') then
+           match <= '1';
+           if (shift_cnt < NUM_BYTES) then
+             data_shift <= data_shift((data_shift'high - data'length) downto 0) & data;
+             shift_cnt <= shift_cnt + 1;
+           else    -- all data fetched, send to out
+             match <= '0';
+             shift_cnt <= 0;
+             o_valid <= '1';
+             o_data <= data_shift;
+           end if;
+         end if; -- if addr match
+       end if;   -- if valid
+
+     end if;
+  end process;
+
+end behavioral;

sim/config.tcl

@@ -16,6 +16,7 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
 	evr320_dpram.vhd \
 	evr320_timestamp.vhd \
 	evr320_decoder.vhd \
+  evr320_data_filter.vhd \
 } -tag evr320_decoder
 
 # EVR320 Decoder Testbench