added testbench over ifc wrapper for tmem test
This commit is contained in:
@ -16,6 +16,11 @@ add_sources $LibPath/BoardSupport/IFC1210/tosca2/hdl/top_ip/src {
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tosca2_glb_pkg.vhd \
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} -version 2002
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add_sources $LibPath/BoardSupport/IFC1210/tosca2/testbench/utilities {
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ifc1210_simu_mapping_xuser_pkg.vhd \
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ifc1210_simu_procedures_pkg.vhd \
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}
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#Set library
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add_library evr320
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@ -40,18 +45,6 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
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evr320_data_filter.vhd \
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} -tag evr320_decoder
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# EVR320 Decoder Testbench
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add_sources $LibPath/Firmware/VHDL/evr320/tb {
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evr320_decoder_tb.vhd \
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} -tag evr320_decoder_tb
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# setup tb runs
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create_tb_run "evr320_decoder_tb"
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tb_run_add_arguments \
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"-gg_EVENT_NR_0=16#0F# -gg_EVENT_NR_1=0 -gg_EVENT_NR_2=0 -gg_EVENT_NR_3=0 -gg_EVENT_NR_SOS=0" \
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"-gg_EVENT_NR_0=2 -gg_EVENT_NR_1=4 -gg_EVENT_NR_2=0 -gg_EVENT_NR_3=3 -gg_EVENT_NR_SOS=0" \
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"-gg_EVENT_NR_0=0 -gg_EVENT_NR_1=0 -gg_EVENT_NR_2=5 -gg_EVENT_NR_3=0 -gg_EVENT_NR_SOS=6"
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add_tb_run
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# IFC1210 Bindings
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add_sources $LibPath/Firmware/VHDL/evr320/hdl {
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@ -64,6 +57,24 @@ add_sources $LibPath/Firmware/VHDL/evr320/hdl {
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evr320_ifc1210_wrapper.vhd \
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} -tag evr320_ifc1210
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# EVR320 Decoder Testbench
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add_sources $LibPath/Firmware/VHDL/evr320/tb {
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evr320_decoder_tb.vhd \
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evr320_ifc1210_wrapper_tb.vhd \
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} -tag evr320_tb
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# EVR320 IFC1210 Wrapper Testbench
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#add_sources $LibPath/Firmware/VHDL/evr320/tb {
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# evr320_ifc1210_wrapper_tb.vhd \
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#} -tag evr320_ifc1210_wrapper_tb
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# setup tb runs
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create_tb_run "evr320_decoder_tb"
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tb_run_add_arguments \
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"-gg_EVENT_NR_0=16#0F# -gg_EVENT_NR_1=0 -gg_EVENT_NR_2=0 -gg_EVENT_NR_3=0 -gg_EVENT_NR_SOS=0" \
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"-gg_EVENT_NR_0=2 -gg_EVENT_NR_1=4 -gg_EVENT_NR_2=0 -gg_EVENT_NR_3=3 -gg_EVENT_NR_SOS=0" \
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"-gg_EVENT_NR_0=0 -gg_EVENT_NR_1=0 -gg_EVENT_NR_2=5 -gg_EVENT_NR_3=0 -gg_EVENT_NR_SOS=6"
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add_tb_run
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create_tb_run "evr320_ifc1210_wrapper_tb"
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add_tb_run
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@ -27,11 +27,14 @@ puts "-- Compile"
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puts "------------------------------"
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clean_libraries -all
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compile_files -tag psi_common
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compile_files -tag evr320_decoder
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compile_files -tag evr320_decoder_tb
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compile_files -lib tosca2
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compile_files -tag evr320_decoder
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compile_files -tag evr320_ifc1210
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#compile_files -tag evr320_decoder_tb
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compile_files -tag evr320_tb
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#compile_files -lib evr320
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run_tb -all
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#run_tb -all
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run_tb -name evr320_decoder_tb
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run_tb -name evr320_ifc1210_wrapper_tb
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run_check_errors "###ERROR###"
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482
tb/evr320_ifc1210_wrapper_tb.vhd
Normal file
482
tb/evr320_ifc1210_wrapper_tb.vhd
Normal file
@ -0,0 +1,482 @@
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--------------------------------------------------------------------------------
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-- ifc1210_wrapper testbench
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_1164.all;
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library std;
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use std.env.all;
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use std.textio.all;
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library tosca2;
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use tosca2.ifc1210_simu_procedures_pkg.all;
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library uvvm_util;
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context uvvm_util.uvvm_util_context;
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-- Work library (application) --------------------------------------------------
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library work;
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use work.evr320_pkg.all;
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entity evr320_ifc1210_wrapper_tb is
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end entity;
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architecture testbench of evr320_ifc1210_wrapper_tb is
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---------------------------------------------------------------------------
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-- System
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---------------------------------------------------------------------------
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constant C_RXUSRCLK_CYCLE : time:= 7 ns;
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constant C_USRCLK_CYCLE : time:= 8 ns;
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constant C_EVT_NR : integer := 4;
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constant C_MEM_DATA_WIDTH : integer := 32; -- 32|64 (64 bit used for tosca2 on ifc1210)
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constant C_EVENT_RECORDER : boolean := true;
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constant C_EVENT_REC_FLAGS : std_logic_vector(11 downto 6) := B"1101_11";
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constant g_EVENT_NR_SOS : integer range 0 to 255 := 16#20#;
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constant g_EVENT_NR_0 : integer range 0 to 255 := 16#00#;
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constant g_EVENT_NR_1 : integer range 0 to 255 := 16#04#;
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constant g_EVENT_NR_2 : integer range 0 to 255 := 16#00#;
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constant g_EVENT_NR_3 : integer range 0 to 255 := 16#00#;
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---------------------------------------------------------------------------
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-- MGT stream
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---------------------------------------------------------------------------
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type mgt_stream_sample_type is record
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data : std_logic_vector(7 downto 0);
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data_k : std_logic_vector(0 downto 0);
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event : std_logic_vector(7 downto 0);
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event_k : std_logic_vector(0 downto 0);
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end record mgt_stream_sample_type;
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type mgt_stream_type is array (natural range <>) of mgt_stream_sample_type;
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signal mgt_stream_index : integer range 0 to 511 := 0;
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signal mgt_stream : mgt_stream_type(511 downto 0) := (others=>(others=>(others=>'0')));
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-----------------------------------------------------------------------------
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-- Timing decoder interface
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-----------------------------------------------------------------------------
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signal usr_clk : std_logic := '0';
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signal evr_params : typ_evr320_params;
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signal mem_addr : std_logic_vector(11 downto 0) := (others => '0');
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signal mem_data : std_logic_vector(31 downto 0) := (others => '0');
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-- Decoder stream
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type dec_stream_type is record
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data : std_logic_vector(7 downto 0);
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addr : std_logic_vector(10 downto 0);
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end record dec_stream_type;
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type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
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signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
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signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
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signal dec_stream_valid : std_logic;
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signal dec_stream_check : dec_stream_check_arr(0 to 2047);
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signal dec_stream_recv_bytes : integer range 0 to 2047;
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type segment_data_arr is array (natural range <>) of std_logic_vector(7 downto 0);
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signal segment_addr : std_logic_vector(7 downto 0);
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signal segment_data : segment_data_arr(0 to 2047);
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signal segment_length : natural range 0 to 2047;
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constant FILTER_ADDRESS : std_logic_vector(11 downto 0) := x"028";
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constant FILTER_NUM_BYTES : integer := 8;
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constant STIMULI_RUNS : integer := 2;
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signal filter_data, filter_data_check : std_logic_vector(63 downto 0) := (others => '0');
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signal filter_valid : std_logic := '0';
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signal tmem_i : tmem_bus_in_t;
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signal tmem_o : tmem_bus_out_t;
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signal tmem_clk : std_logic;
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signal tmem_rst : std_logic;
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signal tmem_data_rd : std_logic_vector(63 downto 0);
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signal tick1sec : std_logic;
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alias rxlos is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rst : std_logic>>;
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alias clk_evr is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.clk_evr : std_logic>>;
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alias rxdata is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_data : std_logic_vector(15 downto 0)>>;
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alias rxcharisk is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.i_mgt_rx_charisk : std_logic_vector(1 downto 0)>>;
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alias sos_event is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_sos_event : std_logic>>;
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alias usr_events is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.o_usr_events : std_logic_vector(3 downto 0)>>;
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alias evr_stable is <<signal .evr320_ifc1210_wrapper_tb.evr320_ifc1210_wrapper_inst.evr320_decoder_inst.evr_stable : std_logic>>;
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begin
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tmem_o.TMEM_BUSY_o <= '0';
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tmem_o.TMEM_PIPE_o <= "10";
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-----------------------------------------------------------------------------
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-- Timing decoder
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-----------------------------------------------------------------------------
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evr320_ifc1210_wrapper_inst: entity work.evr320_ifc1210_wrapper
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generic map
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(
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g_MGT_LOCATION => "GTXE1_X0Y16", -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
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g_FACILITY => "SFEL", -- "HIPA" | "SFEL"
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g_EVENT_RECORDER => C_EVENT_RECORDER, -- enable/disable Event Recorder functionality
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g_XUSER_CLK_FREQ => 125000000 -- Xuser Clk Frequency in Hz
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)
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port map
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(
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tick1sec_i => tick1sec,
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--------------------------------------------------------------------------
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-- Debug interface
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--------------------------------------------------------------------------
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debug_clk => open,
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debug => open,
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--------------------------------------------------------------------------
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-- TOSCA2 TMEM interface
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--------------------------------------------------------------------------
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xuser_CLK => tmem_clk,
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xuser_RESET => tmem_rst,
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xuser_TMEM_ENA => tmem_i.TMEM_ENA_i,
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xuser_TMEM_WE => tmem_i.TMEM_WE_i,
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xuser_TMEM_ADD => tmem_i.TMEM_ADD_i(13 downto 3),
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xuser_TMEM_DATW => tmem_i.TMEM_DATW_i,
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xuser_TMEM_DATR => tmem_o.TMEM_DATR_o,
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-- ------------------------------------------------------------------------
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-- MGT Interface
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-- ------------------------------------------------------------------------
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mgt_refclk_i => '0',
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mgt_sfp_los_i => '0',
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mgt_rx_n => '0',
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mgt_rx_p => '0',
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mgt_tx_n => open,
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mgt_tx_p => open,
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mgt_status_o => open,
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mgt_control_i => (others=>'0'),
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---------------------------------------------------------------------------
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-- User interface MGT clock
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---------------------------------------------------------------------------
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clk_evr_o => open,
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usr_events_o => open,
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usr_events_ext_o => open,
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sos_event_o => open,
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--------------------------------------------------------------------------
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-- Decoder axi stream interface, User clock
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--------------------------------------------------------------------------
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stream_clk_i => '1',
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stream_data_o => open,
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stream_addr_o => open,
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stream_valid_o => open
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);
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gen_pulse(tick1sec, '1', usr_clk, 1, "");
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-----------------------------------------------------------------------------
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-- MGT / User clock
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-----------------------------------------------------------------------------
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clock_generator(usr_clk, C_USRCLK_CYCLE);
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tmem_clk <= usr_clk;
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-- Simulate MGT Clock
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mgt_clk_proc: process
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begin
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clk_evr <= force in '0';
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loop
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wait for C_RXUSRCLK_CYCLE/2;
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clk_evr <= force in not(clk_evr);
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end loop;
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end process;
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-----------------------------------------------------------------------------
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-- Decoder reset due to MGT main status
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-----------------------------------------------------------------------------
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process
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begin
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rxlos <= force in '1';
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tmem_rst <= '1';
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wait for 50 ns;
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wait until (falling_edge(clk_evr));
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rxlos <= force in '0';
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tmem_rst <= '0';
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wait ;
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end process;
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-----------------------------------------------------------------------------
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-- Read stimuli file
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-----------------------------------------------------------------------------
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file_blk : block
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file file_stimuli : text;
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type parse_fsm_state is (idle, seg_start, seg_addr, seg_Wait, seg_payload, seg_payload_wait, seg_done);
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begin
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process
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variable file_line : line;
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variable data, event : std_logic_vector(7 downto 0);
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variable data_k, event_k : std_logic_vector(0 downto 0);
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variable space : character;
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variable i : integer;
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variable parse_fsm : parse_fsm_state := idle;
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variable payload_cnt : integer range 0 to 2047;
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variable event_cnt_total : integer := 0;
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variable event_cnt_0 : integer := 0;
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variable event_cnt_1 : integer := 0;
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variable event_cnt_2 : integer := 0;
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variable event_cnt_3 : integer := 0;
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variable event_cnt_user : integer := 0;
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begin
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file_open(file_stimuli, "../tb/stimuli_mgt.dat", read_mode);
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readline(file_stimuli, file_line); -- comment
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readline(file_stimuli, file_line); -- comment
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i := 0;
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-- read line by line from .dat file:
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while not endfile(file_stimuli) loop
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readline(file_stimuli, file_line);
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hread(file_line, event);
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read(file_line, event_k);
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read(file_line, space);
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read(file_line, space);
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hread(file_line, data);
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read(file_line, space);
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read(file_line, data_k);
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-- write to array:
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mgt_stream(i).data <= data;
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mgt_stream(i).data_k <= data_k;
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mgt_stream(i).event <= event;
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mgt_stream(i).event_k <= event_k;
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mgt_stream_index <= i;
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--debug output:
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--log(ID_SEGMENT_DATA, "stimuli file: i=" & integer'image(i) & " event=0x" & to_string(event, HEX) & " k=" & to_string(event_k, HEX)
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-- & " data=0x" & to_string(data, HEX) & " k=" & to_string(data_k, HEX) & " ");
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-- Parse only segment:
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----------------------
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case (parse_fsm) is
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when idle =>
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if (data = x"5C" and data_k = "1") then -- check if frame start
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parse_fsm := seg_start;
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end if;
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when seg_start =>
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parse_fsm := seg_addr;
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when seg_addr =>
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segment_addr <= data;
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parse_fsm := seg_wait;
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when seg_wait =>
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parse_fsm := seg_payload;
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payload_cnt := 0;
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when seg_payload =>
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if (data = x"3C" and data_k = "1") then -- check if frame end
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parse_fsm := seg_done;
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else
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segment_data(payload_cnt) <= data;
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parse_fsm := seg_payload_wait;
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segment_length <= payload_cnt+1;
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end if;
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when seg_payload_wait =>
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payload_cnt := payload_cnt + 1;
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parse_fsm := seg_payload;
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when seg_done =>
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-- done
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end case;
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i := i + 1;
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end loop;
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file_close(file_stimuli);
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wait;
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end process;
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end block;
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---------------------------------------------------------
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-- Wait for Start of Sequence Event
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---------------------------------------------------------
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process
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begin
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wait until rising_edge(sos_event);
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log(ID_CTRL, "Start of Sequence Event Received: "& to_string(std_logic_vector(to_unsigned(g_EVENT_NR_SOS, 8)), HEX, AS_IS, INCL_RADIX) ); -- change to await_value
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end process;
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--------------------------------------------------------------------------
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-- Stimuli MGT
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--------------------------------------------------------------------------
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process
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begin
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wait until rising_edge(clk_evr);
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for b in 0 to STIMULI_RUNS-1 loop
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log(ID_LOG_HDR, "Send stimuli stream to MGT - RUN " & to_string(b+1));
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for idx in 0 to mgt_stream_index loop
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--log(ID_FRAME_DATA, to_string(mgt_stream(idx).data, HEX), to_string(mgt_stream(idx).event, HEX));
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wait until rising_edge(clk_evr);
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rxdata <= force out mgt_stream(idx).data & mgt_stream(idx).event;
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rxcharisk <= force out mgt_stream(idx).data_k & mgt_stream(idx).event_k;
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end loop;
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wait for 3 us;
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end loop;
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wait;
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end process;
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-----------------------------------------------------------------------------
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-- Main Process
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-----------------------------------------------------------------------------
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process
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constant C_SCOPE : string := C_TB_SCOPE_DEFAULT;
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constant c_TB_NAME : string := "evr320_decoder_tb";
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variable latency_cnt_val : unsigned(31 downto 0);
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begin
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disable_log_msg(ID_GEN_PULSE);
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--------------------------------------------------------------------------
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log(ID_LOG_HDR, "Start Simulation of evr320 decoder", C_SCOPE);
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--------------------------------------------------------------------------
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--------------------------------------------------------------------------
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-- Get out of reset, enable events
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--------------------------------------------------------------------------
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evr_params.event_enable( 0) <= '0' when g_EVENT_NR_0 = 0 else '1';
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evr_params.event_enable( 1) <= '0' when g_EVENT_NR_1 = 0 else '1';
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evr_params.event_enable( 2) <= '0' when g_EVENT_NR_2 = 0 else '1';
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evr_params.event_enable( 3) <= '0' when g_EVENT_NR_3 = 0 else '1';
|
||||
evr_params.event_numbers( 0) <= std_logic_vector(to_unsigned(g_EVENT_NR_0, 8));
|
||||
evr_params.event_numbers( 1) <= std_logic_vector(to_unsigned(g_EVENT_NR_1, 8));
|
||||
evr_params.event_numbers( 2) <= std_logic_vector(to_unsigned(g_EVENT_NR_2, 8));
|
||||
evr_params.event_numbers( 3) <= std_logic_vector(to_unsigned(g_EVENT_NR_3, 8));
|
||||
evr_params.cs_min_cnt <= X"00000000";
|
||||
evr_params.cs_min_time <= X"00000000";
|
||||
mem_addr <= x"000";
|
||||
await_value(rxlos, '0', 0 ns, 10 us, FAILURE, "wait for release RX LOS");
|
||||
|
||||
-- overwrite evr_stable flag:
|
||||
evr_stable <= force '1';
|
||||
|
||||
-- enable sos event and set event number:
|
||||
TMEM_BUS_WRITE(seqid => "A00_001",
|
||||
tmem_add => x"00_0040",
|
||||
tmem_we => x"0F",
|
||||
tmem_burst => 1,
|
||||
tmem_data_wr => x"0000_0000_0000_2001",
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
|
||||
wait for 20 ns;
|
||||
|
||||
-- read back sos event and event number:
|
||||
TMEM_BUS_READ(seqid => "A00_001",
|
||||
tmem_add => x"00_0040",
|
||||
tmem_burst => 1,
|
||||
tmem_data_rd => tmem_data_rd,
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
|
||||
wait for 20 ns;
|
||||
|
||||
check_value(tmem_data_rd, x"0000_0000_0000_2001", ERROR, "TMEM Write/Read check: EVR SOS Event Cfg");
|
||||
|
||||
-- latency measurement: set event nr:
|
||||
TMEM_BUS_WRITE(seqid => "A00_002",
|
||||
tmem_add => x"00_0030",
|
||||
tmem_we => x"0F",
|
||||
tmem_burst => 1,
|
||||
tmem_data_wr => x"0000_0000_0000_0020",
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
|
||||
wait for 20 ns;
|
||||
|
||||
-- read back sos event and event number:
|
||||
TMEM_BUS_READ(seqid => "A00_002",
|
||||
tmem_add => x"00_0030",
|
||||
tmem_burst => 1,
|
||||
tmem_data_rd => tmem_data_rd,
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
|
||||
wait for 20 ns;
|
||||
|
||||
check_value(tmem_data_rd, x"0000_0000_0000_0020", ERROR, "TMEM Write/Read check: lat. meas. event nr");
|
||||
|
||||
-- 1. check latency measurement counter:
|
||||
----------------------------------------
|
||||
await_value(sos_event, '1', 0 ns, 2 us, ERROR, "wait for sos event");
|
||||
wait for 2000 ns;
|
||||
latency_cnt_val := x"00000000";
|
||||
|
||||
-- read latency measurement counter without rearm:
|
||||
TMEM_BUS_READ(seqid => "A00_002",
|
||||
tmem_add => x"00_0030",
|
||||
tmem_burst => 1,
|
||||
tmem_data_rd => tmem_data_rd,
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
wait for 20 ns;
|
||||
latency_cnt_val := unsigned(tmem_data_rd(63 downto 32));
|
||||
|
||||
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
|
||||
check_value_in_range(latency_cnt_val, x"000000F5", x"000000FE", ERROR, "Latency Counter Value (no-rearm) Check after 2us");
|
||||
|
||||
-- 2. read latency measurement counter again with rearm:
|
||||
--------------------------------------------------------
|
||||
latency_cnt_val := x"00000000";
|
||||
|
||||
TMEM_BUS_READ(seqid => "A00_002",
|
||||
tmem_add => x"00_0038",
|
||||
tmem_burst => 1,
|
||||
tmem_data_rd => tmem_data_rd,
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
wait for 20 ns;
|
||||
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
|
||||
|
||||
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
|
||||
check_value_in_range(latency_cnt_val, x"000000FA", x"00000102", ERROR, "Latency Counter Value (rearm) Check directly after first read");
|
||||
|
||||
-- read 2. time rearm latency counter which should be cleared now:
|
||||
TMEM_BUS_READ(seqid => "A00_002",
|
||||
tmem_add => x"00_0038",
|
||||
tmem_burst => 1,
|
||||
tmem_data_rd => tmem_data_rd,
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
wait for 20 ns;
|
||||
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
|
||||
check_value(latency_cnt_val, x"00000000", ERROR, "Check if counter is cleared");
|
||||
|
||||
-- 4. read latency measurement counter with rearm:
|
||||
--------------------------------------------------
|
||||
await_value(sos_event, '1', 0 ns, 3 us, ERROR, "wait for sos event");
|
||||
wait for 1 us;
|
||||
|
||||
-- read counter and rearm:
|
||||
TMEM_BUS_READ(seqid => "A00_002",
|
||||
tmem_add => x"00_0038",
|
||||
tmem_burst => 1,
|
||||
tmem_data_rd => tmem_data_rd,
|
||||
xuser_clk_i => tmem_clk,
|
||||
xuser_tmem_bus_o => tmem_i,
|
||||
xuser_tmem_bus_i => tmem_o);
|
||||
wait for 20 ns;
|
||||
latency_cnt_val := unsigned(tmem_data_rd(31 downto 0));
|
||||
log(ID_CTRL, "Latency Counter: 0x" & to_string(latency_cnt_val, HEX));
|
||||
check_value_in_range(latency_cnt_val, x"0000007A", x"00000080", ERROR, "Latency Counter Value (rearm) Check after 1us");
|
||||
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Test Done
|
||||
--------------------------------------------------------------------------
|
||||
wait for 1000 ns; -- to allow some time for completion
|
||||
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
|
||||
-- ------------------------------------------------------------------------
|
||||
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
|
||||
-- ------------------------------------------------------------------------
|
||||
-- assert error if UVVM mismatch flag is 1 => upstream info for scripts/jenkins
|
||||
assert shared_uvvm_status.mismatch_on_expected_simulation_errors_or_worse = 0 report "###ERROR### - UVVM Mismatch Errors with Expected Errors -> Check Log for details" severity ERROR;
|
||||
std.env.stop(0);
|
||||
wait; -- stop simulation
|
||||
|
||||
end process;
|
||||
|
||||
end architecture testbench;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- End of file
|
||||
--------------------------------------------------------------------------------
|
||||
Reference in New Issue
Block a user