AEK_8220_Libraries/firmware_vhdl_evr320
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feature: added register for latency measurement counter since a specific

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event occured
This commit is contained in:
purtschert_j
2019-11-04 15:26:04 +01:00
parent 740c93fd7a
commit 60ad0be56e
4 changed files with 145 additions and 20 deletions
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21
hdl/evr320_decoder.vhd
View File

@ -62,7 +62,9 @@ entity evr320_decoder is
--------------------------------------------------------------------------
o_usr_events : out std_logic_vector( 3 downto 0);
o_usr_events_ext : out std_logic_vector( 3 downto 0);
o_sos_event : out std_logic
o_sos_event : out std_logic;
o_event : out std_logic_vector( 7 downto 0);
o_event_valid : out std_logic
);
end evr320_decoder;
@ -894,6 +896,23 @@ begin
o_stream_data <= stream_raw(7 downto 0);
o_stream_addr <= stream_raw(18 downto 8);
-----------------------------------------------------------------------------
-- Raw Event Output
-----------------------------------------------------------------------------
raw_event_output_proc : process(i_mgt_rx_clk)
begin
if (rising_edge(i_mgt_rx_clk)) then
o_event_valid <= '0';
o_event <= (others=>'0');
if ((i_mgt_rx_charisk(0) = '0') and (evr_stable = '1')) then
o_event_valid <= '1';
o_event <= i_mgt_rx_data(7 downto 0);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- EVENT RECORDER

77
hdl/evr320_ifc1210_wrapper.vhd
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@ -10,6 +10,7 @@
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library tosca2;
@ -109,11 +110,15 @@ architecture rtl of evr320_ifc1210_wrapper is
signal event_recorder_control : typ_evt_rec_ctrl;
signal event_recorder_control_sync : typ_evt_rec_ctrl;
signal event_recorder_control_xuser : typ_evt_rec_ctrl;
signal evr_latency_measure_stat : typ_rec_latency_measure_stat;
signal evr_latency_measure_ctrl : typ_rec_latency_measure_ctrl;
signal evr_frequency : std_logic_vector(31 downto 0) := (others => '0');
signal debug_data : std_logic_vector(127 downto 0);
signal decoder_event_valid : std_logic;
signal decoder_event : std_logic_vector(7 downto 0);
-- --------------------------------------------------------------------------
-- Attribute definitions
@ -192,7 +197,9 @@ begin
-- User interface MGT clock
o_usr_events => usr_events_o,
o_usr_events_ext => usr_events_ext_o,
o_sos_event => sos_event_o
o_sos_event => sos_event_o,
o_event => decoder_event,
o_event_valid => decoder_event_valid
);
@ -238,6 +245,8 @@ begin
evr_frequency_i => evr_frequency,
evr_evt_rec_status_i => event_recorder_status,
evr_evt_rec_control_o => event_recorder_control_xuser,
evr_latency_measure_stat_i => evr_latency_measure_stat,
evr_latency_measure_ctrl_o => evr_latency_measure_ctrl,
mgt_status_i => mgt_status,
mgt_reset_o => mgt_reset_tmem_evr,
mem_clk_o => mem_clk,
@ -260,6 +269,72 @@ begin
FrequencyHz => evr_frequency
);
-- --------------------------------------------------------------------------
-- Event Latency Measurement for SW tests
-- --------------------------------------------------------------------------
lat_meas_block : block
type state_type is (armed, count);
signal state : state_type;
signal counter : unsigned (31 downto 0);
signal event_nr_sync, event_nr : std_logic_vector(7 downto 0);
signal event_detected : std_logic_vector(3 downto 0);
signal event_detected_sync : std_logic_vector(1 downto 0);
constant MAX_COUNT : unsigned(31 downto 0) := to_unsigned(g_XUSER_CLK_FREQ / 100, 32); -- MAX 10ms
begin
-- Process: filter events for matching event_nr register:
---------------------------------------------------------
ext_event_proc : process(clk_evr)
begin
if (rising_edge(clk_evr)) then
-- sync to MGT clock domain:
event_nr_sync <= evr_latency_measure_ctrl.event_nr;
event_nr <= event_nr_sync;
-- check if event has been detected and stretch pulse:
event_detected <= event_detected(2 downto 0) & '0';
if (decoder_event_valid = '1' and decoder_event = event_nr) then
event_detected <= (others=>'1');
end if;
end if;
end process;
-- Process: Counter when configured event has been detected:
------------------------------------------------------------
lat_meas_proc: process(xuser_CLK)
begin
if rising_edge(xuser_CLK) then
-- sync to user clock domain:
event_detected_sync <= event_detected_sync(0) & event_detected(3);
-- counter FSM:
---------------
case state is
-- counter is armed:
when armed =>
counter <= (others=>'0');
-- start counting when event detected (rising edge):
if (event_detected_sync(1) = '0' and event_detected_sync(0) = '1') then
state <= count;
end if;
-- counting:
when count =>
-- count only up to 10ms, and stop:
if (counter < MAX_COUNT) then
counter <= counter + 1;
end if;
if (evr_latency_measure_ctrl.counter_arm = '1') then
state <= armed;
end if;
end case;
end if;
evr_latency_measure_stat.counter_val <= std_logic_vector(counter);
end process;
end block;
-- --------------------------------------------------------------------------
-- port mapping
-- --------------------------------------------------------------------------

12
hdl/evr320_pkg.vhd
View File

@ -52,6 +52,14 @@ package evr320_pkg is
error_ack : std_logic;
end record typ_evt_rec_ctrl;
type typ_rec_latency_measure_ctrl is record
event_nr : std_logic_vector(7 downto 0);
counter_arm : std_logic;
end record;
type typ_rec_latency_measure_stat is record
counter_val : std_logic_vector(31 downto 0);
end record;
-- --------------------------------------------------------------------------
-- Type Initialisation
@ -64,6 +72,10 @@ package evr320_pkg is
event_enable => '0',
data_ack => '0',
error_ack => '0');
constant c_INIT_REC_LATENCY_MEASURE_CTRL : typ_rec_latency_measure_ctrl := (event_nr => (others =>'0'),
counter_arm => '1');
constant c_INIT_REC_LATENCY_MEASURE_STAT : typ_rec_latency_measure_stat := (counter_val => (others =>'0'));
-- --------------------------------------------------------------------------
-- Function Prototypes
-- --------------------------------------------------------------------------

55
hdl/evr320_tmem.vhd
View File

@ -38,6 +38,8 @@ entity evr320_tmem is
evr_frequency_i : in std_logic_vector(31 downto 0);
evr_evt_rec_status_i : in typ_evt_rec_status;
evr_evt_rec_control_o : out typ_evt_rec_ctrl;
evr_latency_measure_stat_i : in typ_rec_latency_measure_stat;
evr_latency_measure_ctrl_o : out typ_rec_latency_measure_ctrl;
mgt_status_i : in std_logic_vector(31 downto 0);
mgt_reset_o : out std_logic;
mem_clk_o : out std_logic;
@ -93,6 +95,11 @@ architecture rtl of evr320_tmem is
signal er_handshake_status : std_logic_vector(31 downto 0) := (others => '0');
signal er_control_concat : std_logic_vector(31 downto 0) := (others => '0');
-- latency measurement
signal lat_counter_arm : std_logic := '0';
signal lat_event_nr : std_logic_vector(7 downto 0) := x"26"; -- default SOS event
signal lat_counter_val : std_logic_vector(31 downto 0) := (others=>'0');
-- signal evr_force : std_logic_vector(3 downto 0) := (others => '0');
-- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback
-- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0'));
@ -112,7 +119,7 @@ begin
event_numbers_concat <= event_numbers(3) & event_numbers(2) & event_numbers(1) & event_numbers(0);
er_handshake_status <= X"0000" & bit2byte(er_status.data_error) & bit2byte(er_status.data_valid);
er_control_concat <= X"0000" & er_event_number & bit2byte(er_event_enable);
lat_counter_val <= evr_latency_measure_stat_i.counter_val;
-- --------------------------------------------------------------------------
-- Synchronisation to xuser_CLK
@ -138,26 +145,26 @@ begin
end if;
end process;
-- --------------------------------------------------------------------------
-- Read operation
-- --------------------------------------------------------------------------
read_tmem_evr: process(xuser_CLK)
begin
if (rising_edge(xuser_CLK)) then
lat_counter_arm <= '0';
if (xuser_TMEM_ENA_reg = '1') then
if (xuser_TMEM_ADD_reg(13 downto REG_ADDR_WIDTH) = c_LOW(13 downto REG_ADDR_WIDTH)) then
case xuser_TMEM_ADD_reg(REG_ADDR_MSB downto TMEM_ADDR_LSB) is
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ... evr_force
when X"3" => xuser_TMEM_DATR <= evr_frequency & reserved(31 downto 0); -- 64bit / ByteAddr 018 --> 0x018 = Implementation Options + c_EVR_Location_vec
when X"4" => xuser_TMEM_DATR <= cs_min_time & cs_min_cnt; -- 64bit / ByteAddr 020
when X"5" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 028
when X"6" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 030
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 038
when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
when X"0" => xuser_TMEM_DATR <= event_numbers_concat & X"0000" & mgt_status_evr; -- 64bit / ByteAddr 000
when X"1" => xuser_TMEM_DATR <= reserved(63 downto 32) & X"0000_00" & bit2byte(mgt_reset); -- 64bit / ByteAddr 008 --> 0x00C = not implemented in ifc1210
when X"2" => xuser_TMEM_DATR <= reserved(63 downto 32) & bit2byte(event_enable); -- 64bit / ByteAddr 010 --> 0x014 = Bit0 SW Trigger Event 0, Bit8 SW Trigger Event 1, ... evr_force
when X"3" => xuser_TMEM_DATR <= evr_frequency & reserved(31 downto 0); -- 64bit / ByteAddr 018 --> 0x018 = Implementation Options + c_EVR_Location_vec
when X"4" => xuser_TMEM_DATR <= cs_min_time & cs_min_cnt; -- 64bit / ByteAddr 020
when X"5" => xuser_TMEM_DATR <= reserved(63 downto 0); -- 64bit / ByteAddr 028
when X"6" => xuser_TMEM_DATR <= lat_counter_val & X"000000" & lat_event_nr; -- 64bit / ByteAddr 030
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
when others => xuser_TMEM_DATR <= (others => '0');
end case;
else --> 0x0080-0x4000
@ -226,6 +233,17 @@ begin
if xuser_TMEM_WE_reg(7) = '1' then cs_min_time(31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"6" then --ByteAddr 030 Latency Measurement
if xuser_TMEM_WE_reg(0) = '1' then lat_event_nr ( 7 downto 0) <= xuser_TMEM_DATW_reg( 7 downto 0); end if;
-- if xuser_TMEM_WE_reg(1) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(15 downto 8); end if;
-- if xuser_TMEM_WE_reg(2) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(23 downto 16); end if;
-- if xuser_TMEM_WE_reg(3) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(31 downto 24); end if;
-- if xuser_TMEM_WE_reg(4) = '1' then -reserved- ( 7 downto 0) <= xuser_TMEM_DATW_reg(39 downto 32); end if;
-- if xuser_TMEM_WE_reg(5) = '1' then -reserved- (15 downto 8) <= xuser_TMEM_DATW_reg(47 downto 40); end if;
-- if xuser_TMEM_WE_reg(6) = '1' then -reserved- (23 downto 16) <= xuser_TMEM_DATW_reg(55 downto 48); end if;
-- if xuser_TMEM_WE_reg(7) = '1' then -reserved- (31 downto 24) <= xuser_TMEM_DATW_reg(63 downto 56); end if;
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"8" then --ByteAddr 040
if xuser_TMEM_WE_reg(0) = '1' then er_event_enable <= xuser_TMEM_DATW_reg(0); end if;
if xuser_TMEM_WE_reg(1) = '1' then er_event_number <= xuser_TMEM_DATW_reg(15 downto 8); end if;
@ -245,15 +263,16 @@ begin
-- --------------------------------------------------------------------------
-- Port mapping
-- --------------------------------------------------------------------------
mem_clk_o <= xuser_CLK;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
mem_clk_o <= xuser_CLK;
mem_addr_o <= std_logic_vector(unsigned(xuser_TMEM_ADD) - unsigned(MEM_ADDR_START));
evr_params_o <= (event_numbers, event_enable, cs_min_cnt, cs_min_time);
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
evr_latency_measure_ctrl_o <= (lat_event_nr, lat_counter_arm);
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------