AEK_8220_Libraries/firmware_vhdl_evr320
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BUGFIX: inserted address delay for read data mux

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This commit is contained in:
bucher_p1
2019-10-24 17:00:10 +02:00
parent c846a32902
commit 740c93fd7a
2 changed files with 47 additions and 15 deletions
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31
hdl/evr320_decoder.vhd
View File

@ -173,6 +173,7 @@ architecture behavioral of evr320_decoder is
signal mem_fsm : std_logic_vector( 1 downto 0) := "00";
-- Data memory address
signal mem_addr : std_logic_vector(11 downto 0);
signal mem_addr_dly : std_logic_vector(11 downto 0);
-- Data memory write
signal mem_data_wren : std_logic := '0';
signal mem_data_wr_addr : std_logic_vector(10 downto 0) := (others => '0');
@ -706,14 +707,24 @@ begin
mem_data_wr_addr <= frame_data_rd_addr;
mem_data_wr_byte <= frame_data_rd_byte;
-----------------------------------------------------------------------------
-- Address delay for read data mux
-----------------------------------------------------------------------------
process(i_usr_clk)
begin
if (i_usr_clk'event and (i_usr_clk = '1')) then
mem_addr_dly <= mem_addr;
end if;
end process;
-----------------------------------------------------------------------------
-- Data memory selector
-----------------------------------------------------------------------------
o_mem_data <= mem_data_dpram when (mem_addr(11 downto 9) = "000") else
mem_data_event0 when (mem_addr(11 downto 9) = "001") else
mem_data_event1 when (mem_addr(11 downto 9) = "010") else
mem_data_event2 when (mem_addr(11 downto 9) = "011") else
mem_data_event3 when (mem_addr(11 downto 9) = "100") else
o_mem_data <= mem_data_dpram when (mem_addr_dly(11 downto 9) = "000") else
mem_data_event0 when (mem_addr_dly(11 downto 9) = "001") else
mem_data_event1 when (mem_addr_dly(11 downto 9) = "010") else
mem_data_event2 when (mem_addr_dly(11 downto 9) = "011") else
mem_data_event3 when (mem_addr_dly(11 downto 9) = "100") else
mem_data_event_recorder;
-----------------------------------------------------------------------------
@ -1026,11 +1037,11 @@ begin
--------------------------------------------------------------------------
-- Memory Selector Event Recorder
--------------------------------------------------------------------------
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr(11 downto 9) = B"101") else -- 2K
mem_data_event_nr_timestamp when (mem_addr(11 downto 8) = B"1100") else -- 1K
mem_data_segment_timestamp when (mem_addr(11 downto 7) = B"1101_0") else -- 512B
mem_data_event_nr when (mem_addr(11 downto 6) = B"1101_10") else -- 256B
mem_data_event_flag when (mem_addr(11 downto 6) = B"1101_11") else -- 256B
mem_data_event_recorder <= mem_data_dpram_sos when (mem_addr_dly(11 downto 9) = B"101") else -- 2K
mem_data_event_nr_timestamp when (mem_addr_dly(11 downto 8) = B"1100") else -- 1K
mem_data_segment_timestamp when (mem_addr_dly(11 downto 7) = B"1101_0") else -- 512B
mem_data_event_nr when (mem_addr_dly(11 downto 6) = B"1101_10") else -- 256B
mem_data_event_flag when (mem_addr_dly(11 downto 6) = B"1101_11") else -- 256B
(others => '0');

31
tb/evr320_decoder_tb.vhd
View File

@ -484,15 +484,36 @@ begin
----------------------------------------------------------------------
log(ID_DATA, "Check expected Event Flags after SOS Event detected");
----------------------------------------------------------------------
wait until rising_edge(usr_clk);
for addr in 0 to 63 loop
wait until rising_edge(usr_clk);
mem_addr <= C_EVENT_REC_FLAGS & std_logic_vector(to_unsigned(addr, 6));
wait until rising_edge(usr_clk);
await_value(mem_data(0), all_expected_events(4*addr), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr) & " Flag");
await_value(mem_data(8), all_expected_events(4*addr + 1), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 1) & " Flag");
await_value(mem_data(16), all_expected_events(4*addr + 2), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 2) & " Flag");
await_value(mem_data(24), all_expected_events(4*addr + 3), 0 ns, 1 ns, ERROR, "Event " & to_string(4*addr + 3) & " Flag");
end loop;
----------------------------------------------------------------------
log(ID_DATA, "Check Memory block border");
----------------------------------------------------------------------
-- read data mux switching made visible with delayed address.
mem_addr <= C_EVENT_REC_FLAGS & "000000";
wait until rising_edge(usr_clk);
wait for C_USRCLK_CYCLE/4;
for addr in 62 to 65 loop
mem_addr <= (C_EVENT_REC_FLAGS & "000000") + std_logic_vector(to_unsigned(addr, 7));
wait until rising_edge(usr_clk);
check_value(mem_data(0), all_expected_events(4*addr), ERROR, "Event " & to_string(4*addr) & " Flag");
check_value(mem_data(8), all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
check_stable(mem_data, C_USRCLK_CYCLE, ERROR, "Read Data stable on Output");
wait for C_USRCLK_CYCLE/4;
if (addr < 64) then
check_value(mem_data(0), all_expected_events(4*addr), ERROR, "Event " & to_string(4*addr) & " Flag");
check_value(mem_data(8), all_expected_events(4*addr + 1), ERROR, "Event " & to_string(4*addr + 1) & " Flag");
check_value(mem_data(16), all_expected_events(4*addr + 2), ERROR, "Event " & to_string(4*addr + 2) & " Flag");
check_value(mem_data(24), all_expected_events(4*addr + 3), ERROR, "Event " & to_string(4*addr + 3) & " Flag");
else
check_value(mem_data, X"0000_0000", ERROR, "After Event Recorder Mem Map");
end if;
end loop;
----------------------------------------------------------------------