AEK_8220_Libraries/firmware_vhdl_evr320
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FEATURE: add to TMEM interface regiter width & delay

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This commit is contained in:
stef_b
2019-11-29 15:13:46 +01:00
parent 6b1f4fbcbc
commit 5a060a160c
8 changed files with 4248 additions and 4875 deletions
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doc/evr320.pdf
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doc/evr320.rtf
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doc/evr320.vsd
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hdl/evr320_ifc1210_wrapper.vhd
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@ -31,47 +31,47 @@ entity evr320_ifc1210_wrapper is
-- ------------------------------------------------------------------------
-- Debug interface
-- ------------------------------------------------------------------------
debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0);
debug_clk : out std_logic;
debug : out std_logic_vector(127 downto 0);
-- ------------------------------------------------------------------------
-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
-- ------------------------------------------------------------------------
xuser_CLK : in std_logic;
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector(7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
xuser_CLK : in std_logic;
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector(7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
mgt_refclk_i : in std_logic; -- MGT Reference Clock
mgt_sfp_los_i : in std_logic; -- SFP Loss of Signal (light on receiver)
mgt_rx_n : in std_logic; -- MGT RX N
mgt_rx_p : in std_logic; -- MGT RX P
mgt_tx_n : out std_logic; -- MGT TX N
mgt_tx_p : out std_logic; -- MGT TX P
mgt_status_o : out std_logic_vector(31 downto 0); -- MGT Status
mgt_control_i : in std_logic_vector(31 downto 0); -- MGT Control
---------------------------------------------------------------------------
-- User interface MGT clock
---------------------------------------------------------------------------
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay
sos_event_o : out std_logic; -- Start-of-Sequence Event
clk_evr_o : out std_logic; -- Recovered parallel clock from MGT
usr_events_o : out std_logic_vector(3 downto 0); -- User defined event pulses with one clock cycles length & no delay
sos_event_o : out std_logic; -- Start-of-Sequence Event
--*** new features adjusted in delay & length ***
usr_event_width_i : in typ_arr_width; --output extend in clock recovery clock cycles event 0,1,2,3
usr_event_delay_i : in typ_arr_delay; -- delay in recovery clock cycles event sos,0,1,2,3
usr_events_adj_o : out std_logic_vector(3 downto 0); -- User defined event pulses adjusted in delay & length
sos_events_adj_o : out std_logic; -- Start-of-Sequence adjusted in delay & length
--usr_event_width_i : in typ_arr_width; --output extend in clock recovery clock cycles event 0,1,2,3
--usr_event_delay_i : in typ_arr_delay; -- delay in recovery clock cycles event sos,0,1,2,3
usr_events_adj_o : out std_logic_vector(3 downto 0); -- User defined event pulses adjusted in delay & length
sos_events_adj_o : out std_logic; -- Start-of-Sequence adjusted in delay & length
--------------------------------------------------------------------------
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
);
end evr320_ifc1210_wrapper;
@ -117,11 +117,14 @@ architecture rtl of evr320_ifc1210_wrapper is
-- --------------------------------------------------------------------------
-- Attribute definitions
-- --------------------------------------------------------------------------
attribute keep : string;
attribute keep : string;
attribute keep of clk_evr : signal is "TRUE";
attribute keep of debug_data : signal is "TRUE";
signal usr_events_s : std_logic_vector(3 downto 0);
signal sos_event_s : std_logic;
signal usr_events_s : std_logic_vector(3 downto 0);
signal sos_event_s : std_logic;
signal evr_rst_s : std_logic;
signal usr_event_delay_s : typ_arr_delay;
signal usr_event_width_s : typ_arr_width;
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
@ -222,7 +225,8 @@ begin
-- --------------------------------------------------------------------------
-- TMEM
-- --------------------------------------------------------------------------
-- --------------------------------------------------------------------------
--formatter:off
evr320_tmem_inst : entity work.evr320_tmem
port map(
-- TOSCA2 TMEM Interface
@ -244,8 +248,12 @@ begin
mgt_reset_o => mgt_reset_tmem_evr,
mem_clk_o => mem_clk,
mem_addr_o => mem_addr_tosca,
mem_data_i => mem_data
);
mem_data_i => mem_data,
--
evr_clk_i => clk_evr,
evr_rst_i => evr_rst_s,
evr_pulse_delay_o => usr_event_delay_s,
evr_pulse_width_o => usr_event_width_s);
-- --------------------------------------------------------------------------
-- Measure EVR Clock (based on xuser_CLK)
@ -346,6 +354,8 @@ begin
end if;
end process;
evr_rst_s <= rst1_s;
usr_events_concat_s <= usr_events_s & sos_event_s;
gene_adj_out : for i in 0 to 4 generate
@ -358,7 +368,7 @@ begin
RstPol_g => '1')
port map(clk_i => clk_evr,
rst_i => rst1_s,
width_i => usr_event_width_i(i),
width_i => usr_event_width_s(i),
dat_i => usr_events_concat_s(i),
dat_o => usr_evt_shaped_s(i));
@ -371,12 +381,12 @@ begin
RStPol_g => '1',
RstState_g => True,
RamBehavior_g => "RBW")
port map(clk_i => clk_evr,
rst_i => rst1_s,
str_i => '1',
del_i => usr_event_delay_i(i),
dat_o(0) => usr_events_adj_s(i),
dat_i(0) => usr_evt_shaped_s(i)
port map(clk_i => clk_evr,
rst_i => rst1_s,
str_i => '1',
del_i => usr_event_delay_s(i),
dat_o(0) => usr_events_adj_s(i),
dat_i(0) => usr_evt_shaped_s(i)
);
end generate;

4
hdl/evr320_pkg.vhd
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@ -63,8 +63,8 @@ package evr320_pkg is
end record;
--*** Type record and constant for new feature pulse width & delay ***
constant MaxDuration_c : positive := 64; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles
constant MaxDelay_c : positive := 32; -- defines maximum delay to add on user events pulse output, in recovery clock cycles
constant MaxDuration_c : positive := 2**16-1; -- defines maximum pulse width to add on user events pulse output, in recovery clock cycles
constant MaxDelay_c : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles
type typ_arr_width is array (4 downto 0) of std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0);
type typ_arr_delay is array (4 downto 0) of std_logic_vector(log2ceil(MaxDelay_c)-1 downto 0);
type typ_arr_nat is array (4 downto 0) of natural;

88
hdl/evr320_tmem.vhd
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@ -2,9 +2,9 @@
-- Paul Scherrer Institute (PSI)
-- ---------------------------------------------------------------------------
-- Unit : evr320_tmem.vhd
-- Author : Patric Bucher
-- Author : Patric Bucher, Benoit Stef
-- ---------------------------------------------------------------------------
-- Copyright© PSI, Section DSV
-- Copyright (c) PSI, Section DSV
-- ---------------------------------------------------------------------------
-- Comment : TMEM address decoding for register and memory access to evr320.
-- ---------------------------------------------------------------------------
@ -18,7 +18,6 @@ use tosca2.tosca2_glb_pkg.all;
use work.evr320_pkg.all;
entity evr320_tmem is
port(
-- ------------------------------------------------------------------------
@ -44,7 +43,14 @@ entity evr320_tmem is
mgt_reset_o : out std_logic;
mem_clk_o : out std_logic;
mem_addr_o : out std_logic_vector(10 downto 0);
mem_data_i : in std_logic_vector(63 downto 0)
mem_data_i : in std_logic_vector(63 downto 0);
---------------------------------------------------------------------------
-- EVR320 pulse output paremters
---------------------------------------------------------------------------
evr_clk_i : in std_logic;
evr_rst_i : in std_logic;
evr_pulse_delay_o : out typ_arr_delay;
evr_pulse_width_o : out typ_arr_width
);
end evr320_tmem;
@ -104,7 +110,10 @@ architecture rtl of evr320_tmem is
-- signal evr_force_rd : std_logic_vector(3 downto 0) := (others => '0'); -- readback
-- signal evr_force_pulse : typ_arr4(3 downto 0) := (others => (others => '0'));
-- event pulse config
signal evr_puls_width_cfg_s : typ_arr_width;
signal evr_puls_delay_cfg_s : typ_arr_delay;
-- ----------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
@ -165,6 +174,9 @@ begin
when X"7" => xuser_TMEM_DATR <= reserved(63 downto 32) & lat_counter_val; lat_counter_arm <= '1'; -- 64bit / ByteAddr 038
when X"8" => xuser_TMEM_DATR <= er_handshake_status & er_control_concat; -- 64bit / ByteAddr 040
when X"9" => xuser_TMEM_DATR <= reserved(63 downto 32) & er_status.usr_events_counter; -- 64bit / ByteAddr 048
when X"A" => xuser_TMEM_DATR <= evr_puls_delay_cfg_s(4) & evr_puls_delay_cfg_s(3) & evr_puls_delay_cfg_s(2) & evr_puls_delay_cfg_s(1) ; -- 64bit / ByteAddr 050
when X"B" => xuser_TMEM_DATR <= evr_puls_width_cfg_s(4) & evr_puls_width_cfg_s(3) & evr_puls_width_cfg_s(2) & evr_puls_width_cfg_s(1) ; --64 bit / ByteAddr 054
when X"C" => xuser_TMEM_DATR <= reserved(63 downto 32) & evr_puls_width_cfg_s(0) & evr_puls_delay_cfg_s(0); -- 64bit / ByteAddr 058
when others => xuser_TMEM_DATR <= (others => '0');
end case;
else --> 0x0080-0x4000
@ -255,6 +267,24 @@ begin
if xuser_TMEM_WE_reg(7) = '1' and xuser_TMEM_DATW_reg(56) = '1' then er_error_ack <= (others => '1'); end if;
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"A" then --ByteAddr 050
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 del
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_delay_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 del
if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_delay_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 del
if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_delay_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 del
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"B" then --ByteAddr 058
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_width_cfg_s(1) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- usr evt 0 width
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(2) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- usr evt 1 width
if xuser_TMEM_WE_reg(5 downto 4) = "11" then evr_puls_width_cfg_s(3) <= xuser_TMEM_DATW_reg(47 downto 32); end if; -- usr evt 2 width
if xuser_TMEM_WE_reg(7 downto 6) = "11" then evr_puls_width_cfg_s(4) <= xuser_TMEM_DATW_reg(63 downto 48); end if; -- usr evt 3 width
end if;
-----------------------------------------------------------------------------------------------------------------
if xuser_TMEM_ADD_reg(6 downto 3) = X"C" then --ByteAddr 060
if xuser_TMEM_WE_reg(1 downto 0) = "11" then evr_puls_delay_cfg_s(0) <= xuser_TMEM_DATW_reg(15 downto 0); end if; -- sos evt del
if xuser_TMEM_WE_reg(3 downto 2) = "11" then evr_puls_width_cfg_s(0) <= xuser_TMEM_DATW_reg(31 downto 16); end if; -- sos evt width
end if;
end if;
end if;
end process;
@ -269,9 +299,55 @@ begin
evr_evt_rec_control_o <= (er_event_number, er_event_enable, er_data_ack(3), er_error_ack(3));
mgt_reset_o <= mgt_reset;
evr_latency_measure_ctrl_o <= (lat_event_nr, lat_counter_arm);
-- --------------------------------------------------------------------------
-- add CDC output
-- --------------------------------------------------------------------------
block_cdc_evr_puls_param : block
signal input_s, output_s : std_logic_vector(10 * 16 - 1 downto 0);
begin
-- ------------------------------------------------------------------------
-- Assemble Input
-- ------------------------------------------------------------------------
--** pulse delay parameters **
input_s(15 downto 0) <= evr_puls_delay_cfg_s(0);
input_s(31 downto 16) <= evr_puls_delay_cfg_s(1);
input_s(47 downto 32) <= evr_puls_delay_cfg_s(2);
input_s(63 downto 48) <= evr_puls_delay_cfg_s(3);
input_s(79 downto 64) <= evr_puls_delay_cfg_s(4);
--** pulse width parameters **
input_s(95 downto 80) <= evr_puls_width_cfg_s(0);
input_s(111 downto 96) <= evr_puls_width_cfg_s(1);
input_s(127 downto 112) <= evr_puls_width_cfg_s(2);
input_s(143 downto 128) <= evr_puls_width_cfg_s(3);
input_s(159 downto 144) <= evr_puls_width_cfg_s(4);
-- Instance
inst_cdc_fast_stat : entity work.psi_common_status_cc
generic map(DataWidth_g => input_s'length)
port map(ClkA => xuser_CLK,
RstInA => xuser_RESET,
DataA => input_s,
ClkB => evr_clk_i,
RstInB => evr_rst_i,
DataB => output_s);
-- ------------------------------------------------------------------------
-- Disassemble Output
-- ------------------------------------------------------------------------
--** pulse delay parameters **
evr_pulse_delay_o(0) <= output_s(15 downto 0);
evr_pulse_delay_o(1) <= output_s(31 downto 16);
evr_pulse_delay_o(2) <= output_s(47 downto 32);
evr_pulse_delay_o(3) <= output_s(63 downto 48);
evr_pulse_delay_o(4) <= output_s(79 downto 64);
--** pulse width parameters **
evr_pulse_width_o(0) <= output_s(95 downto 80);
evr_pulse_width_o(1) <= output_s(111 downto 96);
evr_pulse_width_o(2) <= output_s(127 downto 112);
evr_pulse_width_o(3) <= output_s(143 downto 128);
evr_pulse_width_o(4) <= output_s(159 downto 144);
end block;
end rtl;
-- ----------------------------------------------------------------------------
-- ////////////////////////////////////////////////////////////////////////////

2
sim/config.tcl
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@ -35,6 +35,8 @@ add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
psi_common_clk_meas.vhd \
psi_common_pulse_shaper2.vhd \
psi_common_delay2.vhd \
psi_common_simple_cc.vhd \
psi_common_status_cc.vhd \
} -tag psi_common
# EVR320 Decoder

105
tb/evr320_ifc1210_wrapper_tb.vhd
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@ -143,8 +143,6 @@ begin
--------------------------------------------------------------------------
-- Debug interface
--------------------------------------------------------------------------
usr_event_width_i => usr_event_width_sti,
usr_event_delay_i => usr_event_delay_sti,
debug_clk => open,
debug => open,
--------------------------------------------------------------------------
@ -381,9 +379,110 @@ begin
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- ---------------------------------------------------------
-- send delay and width parameters:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0050",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0005_0004_0003_0002",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
check_value(tmem_data_rd, x"0000_0000_0000_2001", ERROR, "TMEM Write/Read check: EVR SOS Event Cfg");
wait for 20 ns;
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0050",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0005_0004_0003_0002", ERROR, "TMEM Write/Read check: EVR Puls delay Event Cfg");
-- ---------------------------------------------------------
-- ---------------------------------------------------------
-- send width and width parameters:
TMEM_BUS_WRITE(seqid => "A00_003",
tmem_add => x"00_0058",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0009_0008_0007_0006",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_003",
tmem_add => x"00_0058",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0009_0008_0007_0006", ERROR, "TMEM Write/Read check: EVR Puls Width Event Cfg");
-- ---------------------------------------------------------
-- ---------------------------------------------------------
-- send width and width parameters for SOS:
TMEM_BUS_WRITE(seqid => "A00_004",
tmem_add => x"00_0060",
tmem_we => x"FF",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0001_0001",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back delay parameters:
TMEM_BUS_READ(seqid => "A00_004",
tmem_add => x"00_0060",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
check_value(tmem_data_rd, x"0000_0000_0001_0001", ERROR, "TMEM Write/Read check: SOS width & delay Event Cfg");
-- ---------------------------------------------------------
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_we => x"0F",
tmem_burst => 1,
tmem_data_wr => x"0000_0000_0000_0020",
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- read back sos event and event number:
TMEM_BUS_READ(seqid => "A00_002",
tmem_add => x"00_0030",
tmem_burst => 1,
tmem_data_rd => tmem_data_rd,
xuser_clk_i => tmem_clk,
xuser_tmem_bus_o => tmem_i,
xuser_tmem_bus_i => tmem_o);
wait for 20 ns;
-- latency measurement: set event nr:
TMEM_BUS_WRITE(seqid => "A00_002",
tmem_add => x"00_0030",