Add robustness to comma-detection and reset generation.
This patch addresses issues I occasionally observed: a) I have seen occurrences when the GTX deasserts RXBYTEISALIGNED while the RXLOSSOFSYNC is *not* asserted. The comma-alignment state machine can be stuck in 'idle' believing all is well when in fact RXBYTEISALIGNED is deasserted. The proposed patch monitors RXBYTEISALIGNED in addition to RXLOSSOFSYNC in 'idle' state. b) The synchronizer (inst_cdc_fast_stat) which takes the pulse width/delay to the EVR clock domain relies on a proper reset sequence for correct operation. It is possible, however, that the 'evr_clk' (which is generated from the recovered RX clock) is not ticking at all when 'xuser_RESET' resets said synchronizer. If e.g., there is no GTX reference clock present (because it requires i2c initialization which is performed later) then the EVR clock may not be ticking and prevent the destination side of the synchronizer from being reset. This has the consequence of 'width' and 'delay' *never* being updated. The proposed patch asserts the synchronizer reset while the RX PLL and/or MMCM are not locked.
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@ -341,13 +341,21 @@ begin
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signal usr_evt_shaped_s : std_logic_vector(4 downto 0);
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signal usr_events_adj_s : std_logic_vector(4 downto 0);
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signal usr_events_concat_s : std_logic_vector(4 downto 0);
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signal mmcm_locked : std_logic;
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signal rxpll_locked : std_logic;
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signal evr_rst_in : std_logic;
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begin
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rxpll_locked <= mgt_status(1);
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mmcm_locked <= mgt_status(2);
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evr_rst_in <= xuser_RESET or (not rxpll_locked) or (not mmcm_locked);
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--*** double stage sync for reset ***--
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proc_rst : process(clk_evr)
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begin
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if rising_edge(clk_evr) then
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rst0_s <= xuser_RESET;
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rst0_s <= evr_rst_in;
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rst1_s <= rst0_s;
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end if;
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end process;
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@ -260,7 +260,7 @@ begin
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else
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case s_align_fsm is
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when align_idle =>
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if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' then
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if o_mgt.rx.RXLOSSOFSYNC( 1) = '1' or o_mgt.rx.RXBYTEISALIGNED = '0' then
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s_align_fsm <= align_slide;
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end if;
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when align_slide =>
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