change: split streaming port to data and address

This commit is contained in:
2018-12-06 10:00:53 +01:00
parent 84f23d13ab
commit 82c023c610
4 changed files with 26 additions and 17 deletions

View File

@ -20,7 +20,8 @@ entity evr320_data_filter is
port (
-- User stream interface
i_stream_clk : in std_logic; -- user clock
i_stream_data : in std_logic_vector(11+8-1 downto 0); -- | byte-address (12bit) | data buffer (8bit) |
i_stream_data : in std_logic_vector(7 downto 0);
i_stream_addr : in std_logic_vector(10 downto 0);
i_stream_valid : in std_logic;
-- filter output:
o_data : out std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
@ -44,8 +45,8 @@ begin
o_valid <= '0';
if (i_stream_valid = '1') then
addr := i_stream_data(i_stream_data'high downto 8);
data := i_stream_data(7 downto 0);
addr := i_stream_addr;
data := i_stream_data;
if (addr = ADDRESS(10 downto 0) or match = '1') then
match <= '1';

View File

@ -54,7 +54,8 @@ entity evr320_decoder is
-- User stream interface User clock
--------------------------------------------------------------------------
i_stream_clk : in std_logic;
o_stream_data : out std_logic_vector(18 downto 0); -- | addr 11bit | data 8bit |
o_stream_data : out std_logic_vector(7 downto 0);
o_stream_addr : out std_logic_vector(10 downto 0);
o_stream_valid : out std_logic;
--------------------------------------------------------------------------
-- User interface MGT clock
@ -209,7 +210,7 @@ architecture behavioral of evr320_decoder is
signal mem_data_event_nr_timestamp : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_dpram_sos : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal mem_data_segment_timestamp : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
signal stream_raw : std_logic_vector(18 downto 0);
-- attribute safe_implementation: string;
-- attribute safe_implementation of frame_fsm : signal is "yes";
-- attribute safe_implementation of mem_fsm : signal is "yes";
@ -859,7 +860,7 @@ begin
InRdy => open,
-- Output Data
OutData => o_stream_data,
OutData => stream_raw,
OutVld => o_stream_valid,
OutRdy => '1',
@ -878,6 +879,8 @@ begin
OutLevel => open
);
o_stream_data <= stream_raw(7 downto 0);
o_stream_addr <= stream_raw(18 downto 8);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- EVENT RECORDER

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@ -37,13 +37,13 @@ entity evr320_ifc1210_wrapper is
-- ------------------------------------------------------------------------
-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
-- ------------------------------------------------------------------------
xuser_CLK : in std_logic;
xuser_RESET : in std_logic;
xuser_TMEM_ENA : in std_logic;
xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
xuser_CLK: in std_logic;
xuser_RESET: in std_logic;
xuser_TMEM_ENA: in std_logic;
xuser_TMEM_WE: in std_logic_vector( 7 downto 0);
xuser_TMEM_ADD: in std_logic_vector(13 downto 3);
xuser_TMEM_DATW: in std_logic_vector(63 downto 0);
xuser_TMEM_DATR: out std_logic_vector(63 downto 0);
-- ------------------------------------------------------------------------
-- MGT Interface
-- ------------------------------------------------------------------------
@ -66,7 +66,8 @@ entity evr320_ifc1210_wrapper is
-- Decoder axi stream interface, User clock
--------------------------------------------------------------------------
stream_clk_i : in std_logic := '0';
stream_data_o : out std_logic_vector(18 downto 0); -- | addr 11bit | data 8bit |
stream_data_o : out std_logic_vector(7 downto 0);
stream_addr_o : out std_logic_vector(10 downto 0);
stream_valid_o : out std_logic
);
end evr320_ifc1210_wrapper;
@ -187,6 +188,7 @@ begin
-- user stream interface, user clock
i_stream_clk => stream_clk_i,
o_stream_data => stream_data_o,
o_stream_addr => stream_addr_o,
o_stream_valid => stream_valid_o,
-- User interface MGT clock
o_usr_events => usr_events_o,

View File

@ -77,7 +77,8 @@ architecture testbench of evr320_decoder_tb is
end record dec_stream_type;
type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
signal dec_stream_data : std_logic_vector(11+8-1 downto 0) := (others => '0');
signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
signal dec_stream_valid : std_logic;
signal dec_stream_check : dec_stream_check_arr(0 to 2047);
signal dec_stream_recv_bytes : integer range 0 to 2047;
@ -132,6 +133,7 @@ begin
--------------------------------------------------------------------------
i_stream_clk => usr_clk,
o_stream_data => dec_stream_data,
o_stream_addr => dec_stream_addr,
o_stream_valid => dec_stream_valid,
--------------------------------------------------------------------------
-- User interface MGT clock
@ -149,6 +151,7 @@ begin
port map (
i_stream_clk => usr_clk,
i_stream_data => dec_stream_data,
i_stream_addr => dec_stream_addr,
i_stream_valid => dec_stream_valid,
o_data => filter_data,
o_valid => filter_valid
@ -181,8 +184,8 @@ begin
begin
wait until rising_edge(usr_clk);
if (dec_stream_valid = '1') then
addr := dec_stream_data(18 downto 8);
data := dec_stream_data(7 downto 0);
addr := dec_stream_addr;
data := dec_stream_data;
i := to_integer(unsigned(addr)) - to_integer(unsigned(segment_addr))*16;
-- save stream for later comparision:
dec_stream_check(i).addr <= addr;