change: split streaming port to data and address
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@ -20,7 +20,8 @@ entity evr320_data_filter is
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port (
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-- User stream interface
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i_stream_clk : in std_logic; -- user clock
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i_stream_data : in std_logic_vector(11+8-1 downto 0); -- | byte-address (12bit) | data buffer (8bit) |
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i_stream_data : in std_logic_vector(7 downto 0);
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i_stream_addr : in std_logic_vector(10 downto 0);
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i_stream_valid : in std_logic;
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-- filter output:
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o_data : out std_logic_vector(NUM_BYTES*8-1 downto 0) := (others=>'0');
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@ -44,8 +45,8 @@ begin
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o_valid <= '0';
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if (i_stream_valid = '1') then
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addr := i_stream_data(i_stream_data'high downto 8);
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data := i_stream_data(7 downto 0);
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addr := i_stream_addr;
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data := i_stream_data;
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if (addr = ADDRESS(10 downto 0) or match = '1') then
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match <= '1';
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@ -54,7 +54,8 @@ entity evr320_decoder is
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-- User stream interface User clock
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--------------------------------------------------------------------------
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i_stream_clk : in std_logic;
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o_stream_data : out std_logic_vector(18 downto 0); -- | addr 11bit | data 8bit |
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o_stream_data : out std_logic_vector(7 downto 0);
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o_stream_addr : out std_logic_vector(10 downto 0);
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o_stream_valid : out std_logic;
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--------------------------------------------------------------------------
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-- User interface MGT clock
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@ -209,7 +210,7 @@ architecture behavioral of evr320_decoder is
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signal mem_data_event_nr_timestamp : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
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signal mem_data_dpram_sos : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
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signal mem_data_segment_timestamp : std_logic_vector(MEM_DATA_WIDTH - 1 downto 0) := (others => '0');
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signal stream_raw : std_logic_vector(18 downto 0);
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-- attribute safe_implementation: string;
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-- attribute safe_implementation of frame_fsm : signal is "yes";
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-- attribute safe_implementation of mem_fsm : signal is "yes";
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@ -859,7 +860,7 @@ begin
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InRdy => open,
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-- Output Data
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OutData => o_stream_data,
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OutData => stream_raw,
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OutVld => o_stream_valid,
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OutRdy => '1',
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@ -878,6 +879,8 @@ begin
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OutLevel => open
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);
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o_stream_data <= stream_raw(7 downto 0);
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o_stream_addr <= stream_raw(18 downto 8);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- EVENT RECORDER
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@ -37,13 +37,13 @@ entity evr320_ifc1210_wrapper is
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-- ------------------------------------------------------------------------
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-- TOSCA2 TMEM Interface (xuser clock domain, 100-250MHz)
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-- ------------------------------------------------------------------------
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xuser_CLK : in std_logic;
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xuser_RESET : in std_logic;
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xuser_TMEM_ENA : in std_logic;
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xuser_TMEM_WE : in std_logic_vector( 7 downto 0);
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xuser_TMEM_ADD : in std_logic_vector(13 downto 3);
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xuser_TMEM_DATW : in std_logic_vector(63 downto 0);
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xuser_TMEM_DATR : out std_logic_vector(63 downto 0);
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xuser_CLK: in std_logic;
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xuser_RESET: in std_logic;
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xuser_TMEM_ENA: in std_logic;
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xuser_TMEM_WE: in std_logic_vector( 7 downto 0);
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xuser_TMEM_ADD: in std_logic_vector(13 downto 3);
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xuser_TMEM_DATW: in std_logic_vector(63 downto 0);
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xuser_TMEM_DATR: out std_logic_vector(63 downto 0);
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-- ------------------------------------------------------------------------
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-- MGT Interface
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-- ------------------------------------------------------------------------
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@ -66,7 +66,8 @@ entity evr320_ifc1210_wrapper is
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-- Decoder axi stream interface, User clock
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--------------------------------------------------------------------------
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stream_clk_i : in std_logic := '0';
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stream_data_o : out std_logic_vector(18 downto 0); -- | addr 11bit | data 8bit |
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stream_data_o : out std_logic_vector(7 downto 0);
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stream_addr_o : out std_logic_vector(10 downto 0);
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stream_valid_o : out std_logic
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);
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end evr320_ifc1210_wrapper;
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@ -187,6 +188,7 @@ begin
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-- user stream interface, user clock
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i_stream_clk => stream_clk_i,
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o_stream_data => stream_data_o,
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o_stream_addr => stream_addr_o,
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o_stream_valid => stream_valid_o,
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-- User interface MGT clock
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o_usr_events => usr_events_o,
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@ -77,7 +77,8 @@ architecture testbench of evr320_decoder_tb is
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end record dec_stream_type;
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type dec_stream_check_arr is array (natural range <>) of dec_stream_type;
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signal dec_stream_data : std_logic_vector(11+8-1 downto 0) := (others => '0');
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signal dec_stream_data : std_logic_vector(7 downto 0) := (others => '0');
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signal dec_stream_addr : std_logic_vector(10 downto 0) := (others => '0');
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signal dec_stream_valid : std_logic;
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signal dec_stream_check : dec_stream_check_arr(0 to 2047);
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signal dec_stream_recv_bytes : integer range 0 to 2047;
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@ -132,6 +133,7 @@ begin
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--------------------------------------------------------------------------
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i_stream_clk => usr_clk,
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o_stream_data => dec_stream_data,
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o_stream_addr => dec_stream_addr,
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o_stream_valid => dec_stream_valid,
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--------------------------------------------------------------------------
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-- User interface MGT clock
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@ -149,6 +151,7 @@ begin
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port map (
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i_stream_clk => usr_clk,
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i_stream_data => dec_stream_data,
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i_stream_addr => dec_stream_addr,
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i_stream_valid => dec_stream_valid,
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o_data => filter_data,
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o_valid => filter_valid
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@ -181,8 +184,8 @@ begin
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begin
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wait until rising_edge(usr_clk);
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if (dec_stream_valid = '1') then
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addr := dec_stream_data(18 downto 8);
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data := dec_stream_data(7 downto 0);
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addr := dec_stream_addr;
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data := dec_stream_data;
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i := to_integer(unsigned(addr)) - to_integer(unsigned(segment_addr))*16;
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-- save stream for later comparision:
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dec_stream_check(i).addr <= addr;
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