AEK_8220_Libraries/firmware_vhdl_evr320
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DPDCY: due to change in PSI_COMMON suffix 2 -> cfg in ifc1210 wrapper

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stef_b
2019-12-02 15:12:27 +01:00
parent 5a060a160c
commit 071cf50ded
4 changed files with 14 additions and 15 deletions
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22
hdl/evr320_ifc1210_wrapper.vhd
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@ -21,11 +21,10 @@ use work.v6vlx_gtxe1_pkg.all;
entity evr320_ifc1210_wrapper is
generic(
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000; -- Xuser Clk Frequency in Hz
g_EVT_HOLDOFF : typ_arr_nat := (0, 0, 0, 0, 0) -- Minimum number of clock cycles between input pulses event sos,0,1,2,3
g_MGT_LOCATION : string := "GTXE1_X0Y16"; -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY : string := "SFEL"; -- "HIPA" | "SFEL"
g_EVENT_RECORDER : boolean := false; -- enable/disable Event Recorder functionality
g_XUSER_CLK_FREQ : natural := 125000000 -- Xuser Clk Frequency in Hz
);
port(
-- ------------------------------------------------------------------------
@ -344,6 +343,7 @@ begin
signal usr_evt_shaped_s : std_logic_vector(4 downto 0);
signal usr_events_adj_s : std_logic_vector(4 downto 0);
signal usr_events_concat_s : std_logic_vector(4 downto 0);
begin
--*** double stage sync for reset ***--
proc_rst : process(clk_evr)
@ -361,19 +361,21 @@ begin
gene_adj_out : for i in 0 to 4 generate
--*** Adjust pulse length in clk cycles EVENT 0,1,2,3 ***
inst_pulslength_evt0 : entity work.psi_common_pulse_shaper2
inst_pulslength_evt0 : entity work.psi_common_pulse_shaper_cfg
generic map(HoldIn_g => false,
HoldOff_g => g_EVT_HOLDOFF(i),
HoldOffEna_g => false,
MaxHoldOff_g => 10,
MaxDuration_g => MaxDuration_c,
RstPol_g => '1')
port map(clk_i => clk_evr,
rst_i => rst1_s,
width_i => usr_event_width_s(i),
hold_i => (others => '0'),
dat_i => usr_events_concat_s(i),
dat_o => usr_evt_shaped_s(i));
--*** delay adjust EVENT 0,1,2,3***
inst_adjdelay_evt0 : entity work.psi_common_delay2
inst_adjdelay_evt0 : entity work.psi_common_delay_cfg
generic map(Width_g => 1,
Resource_g => "AUTO",
BramThreshold_g => 128,
@ -385,8 +387,8 @@ begin
rst_i => rst1_s,
str_i => '1',
del_i => usr_event_delay_s(i),
dat_o(0) => usr_events_adj_s(i),
dat_i(0) => usr_evt_shaped_s(i)
dat_o(0) => usr_events_adj_s(i),
dat_i(0) => usr_evt_shaped_s(i)
);
end generate;

2
hdl/evr320_pkg.vhd
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@ -67,8 +67,6 @@ package evr320_pkg is
constant MaxDelay_c : positive := 2**16-1; -- defines maximum delay to add on user events pulse output, in recovery clock cycles
type typ_arr_width is array (4 downto 0) of std_logic_vector(log2ceil(MaxDuration_c)-1 downto 0);
type typ_arr_delay is array (4 downto 0) of std_logic_vector(log2ceil(MaxDelay_c)-1 downto 0);
type typ_arr_nat is array (4 downto 0) of natural;
-- --------------------------------------------------------------------------
-- Type Initialisation

4
sim/config.tcl
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@ -33,8 +33,8 @@ add_sources $LibPath/Firmware/VHDL/psi_common/hdl {
psi_common_pulse_cc.vhd \
psi_common_async_fifo.vhd \
psi_common_clk_meas.vhd \
psi_common_pulse_shaper2.vhd \
psi_common_delay2.vhd \
psi_common_pulse_shaper_cfg.vhd \
psi_common_delay_cfg.vhd \
psi_common_simple_cc.vhd \
psi_common_status_cc.vhd \
} -tag psi_common

1
tb/evr320_ifc1210_wrapper_tb.vhd
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@ -132,7 +132,6 @@ begin
-----------------------------------------------------------------------------
evr320_ifc1210_wrapper_inst : entity work.evr320_ifc1210_wrapper
generic map(
g_EVT_HOLDOFF => (0,0,0,0,0),
g_MGT_LOCATION => "GTXE1_X0Y16", -- "GTXE1_X0Y0" to "GTXE1_X0Y11" | "GTXE1_X0Y16" to "GTXE1_X0Y19"
g_FACILITY => "SFEL", -- "HIPA" | "SFEL"
g_EVENT_RECORDER => C_EVENT_RECORDER, -- enable/disable Event Recorder functionality