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79aef71ce3
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FPGA: spot_finder added
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2023-09-26 18:54:31 +02:00 |
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84bf69b8a6
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FPGA: frame generator reads from HBM (work in progress)
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2023-09-26 13:14:43 +02:00 |
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7e3b9cfeba
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Revert "FPGA: add spot finder to the design"
This reverts commit df0b0d8b96.
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2023-09-25 21:52:55 +02:00 |
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027b3aa943
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Revert "FPGA: add register slices"
This reverts commit cf2163a402.
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2023-09-25 21:52:54 +02:00 |
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cf2163a402
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FPGA: add register slices
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2023-09-24 20:28:35 +02:00 |
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df0b0d8b96
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FPGA: add spot finder to the design
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2023-09-24 19:04:58 +02:00 |
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ae6e036628
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FPGA: increase frame_generator memory to 8 MiB
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2023-09-24 14:39:46 +02:00 |
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a70e3cf444
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FPGA: integration & jf_conversion use hbm_size_bytes as external signal - hbm_size_bytes is constant, so to allow constant propagation in synthesis
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2023-09-22 21:49:41 +02:00 |
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2c9d623265
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integration: use separate FIFO for integration results
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2023-09-22 17:49:14 +02:00 |
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2eb85496f2
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FPGA: add integration routine (work in progress)
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2023-09-21 17:12:01 +02:00 |
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4d482e308a
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FPGA: Fix datamover script
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2023-09-19 07:36:56 +02:00 |
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86123eb2fe
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FPGA: Use datamover for save_to_hbm and load_from_hbm
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2023-09-19 07:36:56 +02:00 |
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98877e5bb3
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FPGA: Monitor HBM completion and handle FIFOs
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2023-09-19 07:36:56 +02:00 |
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a80fd362a6
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FPGA: Make sure all HBM handles are accessible - scale FIFOs properly
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2023-09-19 07:36:56 +02:00 |
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a94bdacea9
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Revert "FPGA: use 4 HBM interfaces for load and save to HBM"
This reverts commit 28a29ea3183a35d8ba0dda0628ac727f8bfe4f17.
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2023-09-19 07:36:56 +02:00 |
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1fe5c474ee
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FPGA: use 4 HBM interfaces for load and save to HBM
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2023-09-19 07:36:56 +02:00 |
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5f5b59ef30
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FPGA: Increase FIFO just before save_to_hbm
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2023-09-19 07:36:56 +02:00 |
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e194d31ee1
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FPGA: Add register slices
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2023-09-19 07:36:56 +02:00 |
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36cd247377
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FPGA: Integrate HBM cache into the FPGA
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2023-09-19 07:36:56 +02:00 |
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16bbf54f2a
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Remove open source license (for now)
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2023-09-15 10:47:21 +02:00 |
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362eb62d4b
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FPGA: Use own function to merge streams instead of AXI-Switch + more FIFO status saved
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2023-09-14 23:58:17 +02:00 |
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f3e85deb31
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FPGA: Increase PCIe BAR size to 16 MB
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2023-09-13 20:55:10 +02:00 |
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0c471b3760
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FPGA: Some clean-up of frame generator
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2023-09-13 20:53:55 +02:00 |
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496d016c31
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FPGA: Replace internal_packet_generator with frame_generator (generating UDP packets, instead of internal JFJoch packets)
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2023-09-13 20:06:09 +02:00 |
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b7239331ac
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FPGA: remove script from OC-Accel
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2023-09-12 21:10:15 +02:00 |
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5e137a514a
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FPGA: add more FIFOs to monitoring
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2023-09-12 20:35:48 +02:00 |
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8626195091
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FPGA: fix to deadlock
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2023-09-12 20:09:11 +02:00 |
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9d01630cfc
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FPGA: load calibration works as dedicated function of the card
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2023-09-12 14:34:42 +02:00 |
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8c3a25a8ad
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FPGA: load calibration operates directly on HBM
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2023-09-11 21:47:29 +02:00 |
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05000bab1f
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FPGA: remove transfer to HBM for the time being
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2023-09-11 20:24:20 +02:00 |
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9ff8e039d7
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FPGA: use HBM channels 12 and 13 for save_to_hbm
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2023-09-11 10:50:30 +02:00 |
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36444f4c8f
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FPGA: Use different memory controllers for save to HBM
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2023-09-10 20:19:15 +02:00 |
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175aefc4b8
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FPGA: Save to HBM uses only 2 channels
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2023-09-10 09:54:32 +02:00 |
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929f6c6544
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FPGA: Handle HBM offsets internally in Jungfraujoch logic
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2023-09-09 20:50:41 +02:00 |
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6251c58f32
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FPGA: Add function to transfer data from HBM to AXI-Lite accessible buffer
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2023-09-08 19:08:37 +02:00 |
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e8c0500ea8
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FPGA: Use HBM switch to access full HBM
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2023-09-08 17:09:33 +02:00 |
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c2eaee6d8a
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FPGA: Save to HBM operates in parallel to host writer
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2023-09-08 13:07:49 +02:00 |
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38df621cf6
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FPGA: Add save to HBM (work in progress)
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2023-09-07 22:15:20 +02:00 |
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ae830009c4
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FPGA: Don't override default MAC location in bd_pcie.tcl
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2023-09-07 21:03:08 +02:00 |
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1d1894d7d6
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FPGA: Use only single HBM stack
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2023-09-07 21:03:08 +02:00 |
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35aa21fefe
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FPGA: Increase FIFO size to improve buffering capability
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2023-09-07 12:23:38 +02:00 |
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dd002e3d6d
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FPGA: Build only 100G solution (no bifurcated design)
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2023-09-07 12:10:38 +02:00 |
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a6377239cf
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FPGA: fix script for 2x100G design
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2023-09-06 19:07:20 +02:00 |
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0434207882
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FPGA: use full AXI for internal packet generator
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2023-09-06 18:16:44 +02:00 |
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caf950f99f
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FPGA: Internal packet generator uses external memory to store image, and this memory is accessible via PCIe BAR
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2023-09-06 08:19:03 +02:00 |
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2a0e4b7d4a
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FPGA: Use 200 Hz for 100 Gbit/s design
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2023-08-15 17:31:05 +02:00 |
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f66fc95ecc
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FPGA: Use 250 Hz for 100 Gbit/s design + adjust TCL scripts
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2023-08-15 14:39:04 +02:00 |
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ad5030334a
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FPGA: Add 1 stream design
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2023-08-14 21:55:27 +02:00 |
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3e406f0f46
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FPGA: URAM read latency reduced to 2
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2023-08-12 12:05:53 +02:00 |
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7a98766304
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FPGA: Split receiver and FPGA design directories
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2023-06-07 21:21:22 +02:00 |
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