FPGA: Increase FIFO just before save_to_hbm

2023-09-17 14:29:58 +02:00
parent 95d4844aa4
commit 5f5b59ef30
1 changed files with 2 additions and 2 deletions
@@ -175,8 +175,8 @@ proc create_hier_cell_jungfraujoch { parentCell nameHier } {
  # Create instance: axis_data_fifo_2, and set properties
  set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
  set_property -dict [ list \
-   CONFIG.FIFO_DEPTH {256} \
-   CONFIG.FIFO_MEMORY_TYPE {block} \
+   CONFIG.FIFO_DEPTH {4096} \
+   CONFIG.FIFO_MEMORY_TYPE {ultra} \
 ] $axis_data_fifo_2

  # Create instance: axis_data_fifo_3, and set properties